[llvm-project.git] / llvm / test / Transforms / SLPVectorizer / X86 / minbitwidth-transformed-operand.ll
| blob | 57b5d2af48ee608afd04667d644a396368b7c0f2 |
1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
2 ; RUN: opt -passes=slp-vectorizer -S -slp-threshold=-7 -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
4 define void @test(i64 %d.promoted.i) {
5 ; CHECK-LABEL: define void @test(
6 ; CHECK-SAME: i64 [[D_PROMOTED_I:%.*]]) {
7 ; CHECK-NEXT: entry:
8 ; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> <i64 poison, i64 0>, i64 0, i32 0
9 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> <i64 poison, i64 0>, i64 [[D_PROMOTED_I]], i32 0
10 ; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i64> [[TMP0]], [[TMP1]]
11 ; CHECK-NEXT: [[TMP3:%.*]] = trunc <2 x i64> [[TMP2]] to <2 x i1>
12 ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i1> [[TMP3]], <2 x i1> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
13 ; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <16 x i1> <i1 poison, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 poison, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <16 x i1> [[TMP4]], <16 x i32> <i32 16, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
14 ; CHECK-NEXT: [[TMP6:%.*]] = mul <16 x i1> [[TMP5]], zeroinitializer
15 ; CHECK-NEXT: [[TMP8:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[TMP6]])
16 ; CHECK-NEXT: [[TMP9:%.*]] = zext i1 [[TMP8]] to i32
17 ; CHECK-NEXT: [[TMP10:%.*]] = and i32 [[TMP9]], 0
18 ; CHECK-NEXT: store i32 [[TMP10]], ptr null, align 4
19 ; CHECK-NEXT: ret void
20 ;
21 entry:
22 %add.1.i = add i64 0, 0
23 %and.1.i = and i64 %add.1.i, %d.promoted.i
24 %conv12.1.i = trunc i64 %and.1.i to i32
25 %mul.i.1.i = mul i32 %conv12.1.i, 0
26 %conv12.i = trunc i64 0 to i32
27 %mul.i.i = mul i32 %conv12.i, 0
28 %conv14104.i = or i32 %mul.i.1.i, %mul.i.i
29 %conv12.2.i = trunc i64 0 to i32
30 %mul.i.2.i = mul i32 %conv12.2.i, 0
31 %0 = or i32 %conv14104.i, %mul.i.2.i
32 %conv12.182.i = trunc i64 0 to i32
33 %mul.i.183.i = mul i32 %conv12.182.i, 0
34 %1 = or i32 %0, %mul.i.183.i
35 %conv12.1.1.i = trunc i64 0 to i32
36 %mul.i.1.1.i = mul i32 %conv12.1.1.i, 0
37 %2 = or i32 %1, %mul.i.1.1.i
38 %conv12.2.1.i = trunc i64 0 to i32
39 %mul.i.2.1.i = mul i32 %conv12.2.1.i, 0
40 %3 = or i32 %2, %mul.i.2.1.i
41 %conv12.297.i = trunc i64 0 to i32
42 %mul.i.298.i = mul i32 %conv12.297.i, 0
43 %4 = or i32 %3, %mul.i.298.i
44 %conv12.1.2.i = trunc i64 0 to i32
45 %mul.i.1.2.i = mul i32 %conv12.1.2.i, 0
46 %5 = or i32 %4, %mul.i.1.2.i
47 %add.1.i.1 = add i64 0, 0
48 %and.1.i.1 = and i64 %add.1.i.1, 0
49 %conv12.1.i.1 = trunc i64 %and.1.i.1 to i32
50 %mul.i.1.i.1 = mul i32 %conv12.1.i.1, 0
51 %conv12.i.1 = trunc i64 0 to i32
52 %mul.i.i.1 = mul i32 %conv12.i.1, 0
53 %conv14104.i.1 = or i32 %mul.i.1.i.1, %mul.i.i.1
54 %conv12.2.i.1 = trunc i64 0 to i32
55 %mul.i.2.i.1 = mul i32 %conv12.2.i.1, 0
56 %6 = or i32 %conv14104.i.1, %mul.i.2.i.1
57 %conv12.182.i.1 = trunc i64 0 to i32
58 %mul.i.183.i.1 = mul i32 %conv12.182.i.1, 0
59 %7 = or i32 %6, %mul.i.183.i.1
60 %conv12.1.1.i.1 = trunc i64 0 to i32
61 %mul.i.1.1.i.1 = mul i32 %conv12.1.1.i.1, 0
62 %8 = or i32 %7, %mul.i.1.1.i.1
63 %conv12.2.1.i.1 = trunc i64 0 to i32
64 %mul.i.2.1.i.1 = mul i32 %conv12.2.1.i.1, 0
65 %9 = or i32 %8, %mul.i.2.1.i.1
66 %conv12.297.i.1 = trunc i64 0 to i32
67 %mul.i.298.i.1 = mul i32 %conv12.297.i.1, 0
68 %10 = or i32 %9, %mul.i.298.i.1
69 %conv12.1.2.i.1 = trunc i64 0 to i32
70 %mul.i.1.2.i.1 = mul i32 %conv12.1.2.i.1, 0
71 %11 = or i32 %10, %mul.i.1.2.i.1
72 %12 = or i32 %5, %11
73 %13 = and i32 %12, 0
74 store i32 %13, ptr null, align 4
75 ret void
76 }