clang/test/OpenMP/for_private_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
   3 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s
   4 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
   5 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
   6 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4
   7
   8 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
   9 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s
  10 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  11 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  12 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  13 // expected-no-diagnostics
  14 #ifndef HEADER
  15 #define HEADER
  16
  17 template <class T>
  18 struct S {
  19   T f;
  20   S(T a) : f(a) {}
  21   S() : f() {}
  22   operator T() { return T(); }
  23   ~S() {}
  24 };
  25
  26 volatile double g;
  27 volatile double &g1 = g;
  28
  29 template <typename T>
  30 T tmain() {
  31   S<T> test;
  32   T t_var = T();
  33   T vec[] = {1, 2};
  34   S<T> s_arr[] = {1, 2};
  35   S<T> &var = test;
  36 #pragma omp parallel
  37 #pragma omp for private(t_var, vec, s_arr, s_arr, var, var)
  38   for (int i = 0; i < 2; ++i) {
  39     vec[i] = t_var;
  40     s_arr[i] = var;
  41   }
  42   return T();
  43 }
  44
  45 int main() {
  46   static int svar;
  47 #ifdef LAMBDA
  48   [&]() {
  49   static float sfvar;
  50 #pragma omp parallel
  51 #pragma omp for private(g, g1, svar, sfvar)
  52   for (int i = 0; i < 2; ++i) {
  53     g = 1;
  54     g1 = 1;
  55     svar = 3;
  56     sfvar = 4.0;
  57     [&]() {
  58       g = 2;
  59       g1 = 2;
  60       svar = 4;
  61       sfvar = 8.0;
  62     }();
  63   }
  64   }();
  65   return 0;
  66 #elif defined(BLOCKS)
  67   ^{
  68   static float sfvar;
  69 #pragma omp parallel
  70 #pragma omp for private(g, g1, svar, sfvar)
  71   for (int i = 0; i < 2; ++i) {
  72     g = 1;
  73     g1 = 1;
  74     svar = 2;
  75     sfvar = 3.0;
  76     ^{
  77       g = 2;
  78       g1 = 2;
  79       svar = 4;
  80       sfvar = 9.0;
  81     }();
  82   }
  83   }();
  84   return 0;
  85 #else
  86   S<float> test;
  87   int t_var = 0;
  88   int vec[] = {1, 2};
  89   S<float> s_arr[] = {1, 2};
  90   S<float> &var = test;
  91 #pragma omp parallel
  92 #pragma omp for private(t_var, vec, s_arr, s_arr, var, var, svar)
  93   for (int i = 0; i < 2; ++i) {
  94     vec[i] = t_var;
  95     s_arr[i] = var;
  96   }
  97   int i;
  98 #pragma omp parallel
  99 #pragma omp for private(i)
 100   for (i = 0; i < 2; ++i) {
 101     ;
 102   }
 103   return tmain<int>();
 104 #endif
 105 }
 106
 107
 108 #endif
 109
 110 // CHECK1-LABEL: define {{[^@]+}}@main
 111 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
 112 // CHECK1-NEXT:  entry:
 113 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 114 // CHECK1-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
 115 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 116 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 117 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
 118 // CHECK1-NEXT:    [[VAR:%.*]] = alloca ptr, align 8
 119 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 120 // CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 121 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
 122 // CHECK1-NEXT:    store i32 0, ptr [[T_VAR]], align 4
 123 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false)
 124 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00)
 125 // CHECK1-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1
 126 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)
 127 // CHECK1-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 8
 128 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @main.omp_outlined)
 129 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 0, ptr @main.omp_outlined.1)
 130 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
 131 // CHECK1-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 4
 132 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
 133 // CHECK1-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
 134 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 135 // CHECK1:       arraydestroy.body:
 136 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 137 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 138 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]]
 139 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
 140 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
 141 // CHECK1:       arraydestroy.done1:
 142 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
 143 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4
 144 // CHECK1-NEXT:    ret i32 [[TMP1]]
 145 //
 146 //
 147 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
 148 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
 149 // CHECK1-NEXT:  entry:
 150 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 151 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 152 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 153 // CHECK1-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
 154 // CHECK1-NEXT:    ret void
 155 //
 156 //
 157 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
 158 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 159 // CHECK1-NEXT:  entry:
 160 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 161 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 162 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 163 // CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 164 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 165 // CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 166 // CHECK1-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
 167 // CHECK1-NEXT:    ret void
 168 //
 169 //
 170 // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined
 171 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
 172 // CHECK1-NEXT:  entry:
 173 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 174 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 175 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 176 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 177 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
 178 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 179 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 180 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 181 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 182 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 183 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 184 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
 185 // CHECK1-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
 186 // CHECK1-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 8
 187 // CHECK1-NEXT:    [[SVAR:%.*]] = alloca i32, align 4
 188 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 189 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 190 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 191 // CHECK1-NEXT:    store ptr undef, ptr [[_TMP1]], align 8
 192 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 193 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 194 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 195 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 196 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
 197 // CHECK1-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
 198 // CHECK1-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
 199 // CHECK1:       arrayctor.loop:
 200 // CHECK1-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
 201 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
 202 // CHECK1-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
 203 // CHECK1-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
 204 // CHECK1-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
 205 // CHECK1:       arrayctor.cont:
 206 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
 207 // CHECK1-NEXT:    store ptr [[VAR]], ptr [[_TMP2]], align 8
 208 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 209 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 210 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 211 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 212 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
 213 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 214 // CHECK1:       cond.true:
 215 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 216 // CHECK1:       cond.false:
 217 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 218 // CHECK1-NEXT:    br label [[COND_END]]
 219 // CHECK1:       cond.end:
 220 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
 221 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 222 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 223 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
 224 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 225 // CHECK1:       omp.inner.for.cond:
 226 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 227 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 228 // CHECK1-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
 229 // CHECK1-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
 230 // CHECK1:       omp.inner.for.cond.cleanup:
 231 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
 232 // CHECK1:       omp.inner.for.body:
 233 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 234 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
 235 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 236 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
 237 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4
 238 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4
 239 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
 240 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]
 241 // CHECK1-NEXT:    store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4
 242 // CHECK1-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8
 243 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4
 244 // CHECK1-NEXT:    [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
 245 // CHECK1-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]]
 246 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false)
 247 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 248 // CHECK1:       omp.body.continue:
 249 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 250 // CHECK1:       omp.inner.for.inc:
 251 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 252 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1
 253 // CHECK1-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
 254 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 255 // CHECK1:       omp.inner.for.end:
 256 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 257 // CHECK1:       omp.loop.exit:
 258 // CHECK1-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 259 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4
 260 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]])
 261 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
 262 // CHECK1-NEXT:    [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
 263 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2
 264 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 265 // CHECK1:       arraydestroy.body:
 266 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 267 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 268 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
 269 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
 270 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
 271 // CHECK1:       arraydestroy.done8:
 272 // CHECK1-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 273 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4
 274 // CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP17]])
 275 // CHECK1-NEXT:    ret void
 276 //
 277 //
 278 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
 279 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 280 // CHECK1-NEXT:  entry:
 281 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 282 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 283 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 284 // CHECK1-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
 285 // CHECK1-NEXT:    ret void
 286 //
 287 //
 288 // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.1
 289 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
 290 // CHECK1-NEXT:  entry:
 291 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 292 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 293 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 294 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 295 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 296 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 297 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 298 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 299 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 300 // CHECK1-NEXT:    [[I1:%.*]] = alloca i32, align 4
 301 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 302 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 303 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 304 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 305 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 306 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 307 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 308 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 309 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 310 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 311 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
 312 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 313 // CHECK1:       cond.true:
 314 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 315 // CHECK1:       cond.false:
 316 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 317 // CHECK1-NEXT:    br label [[COND_END]]
 318 // CHECK1:       cond.end:
 319 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
 320 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 321 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 322 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
 323 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 324 // CHECK1:       omp.inner.for.cond:
 325 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 326 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 327 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
 328 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 329 // CHECK1:       omp.inner.for.body:
 330 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 331 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
 332 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 333 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
 334 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 335 // CHECK1:       omp.body.continue:
 336 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 337 // CHECK1:       omp.inner.for.inc:
 338 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 339 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
 340 // CHECK1-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4
 341 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 342 // CHECK1:       omp.inner.for.end:
 343 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 344 // CHECK1:       omp.loop.exit:
 345 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
 346 // CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP1]])
 347 // CHECK1-NEXT:    ret void
 348 //
 349 //
 350 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
 351 // CHECK1-SAME: () #[[ATTR1]] comdat {
 352 // CHECK1-NEXT:  entry:
 353 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 354 // CHECK1-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
 355 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 356 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 357 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
 358 // CHECK1-NEXT:    [[VAR:%.*]] = alloca ptr, align 8
 359 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
 360 // CHECK1-NEXT:    store i32 0, ptr [[T_VAR]], align 4
 361 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
 362 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)
 363 // CHECK1-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1
 364 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
 365 // CHECK1-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 8
 366 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 0, ptr @_Z5tmainIiET_v.omp_outlined)
 367 // CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 368 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
 369 // CHECK1-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
 370 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 371 // CHECK1:       arraydestroy.body:
 372 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 373 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 374 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
 375 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
 376 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
 377 // CHECK1:       arraydestroy.done1:
 378 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
 379 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4
 380 // CHECK1-NEXT:    ret i32 [[TMP1]]
 381 //
 382 //
 383 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
 384 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 385 // CHECK1-NEXT:  entry:
 386 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 387 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 388 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 389 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 390 // CHECK1-NEXT:    store float 0.000000e+00, ptr [[F]], align 4
 391 // CHECK1-NEXT:    ret void
 392 //
 393 //
 394 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
 395 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 396 // CHECK1-NEXT:  entry:
 397 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 398 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 399 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 400 // CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 401 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 402 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 403 // CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 404 // CHECK1-NEXT:    store float [[TMP0]], ptr [[F]], align 4
 405 // CHECK1-NEXT:    ret void
 406 //
 407 //
 408 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
 409 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 410 // CHECK1-NEXT:  entry:
 411 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 412 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 413 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 414 // CHECK1-NEXT:    ret void
 415 //
 416 //
 417 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
 418 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 419 // CHECK1-NEXT:  entry:
 420 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 421 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 422 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 423 // CHECK1-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
 424 // CHECK1-NEXT:    ret void
 425 //
 426 //
 427 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
 428 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 429 // CHECK1-NEXT:  entry:
 430 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 431 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 432 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 433 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
 434 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 435 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 436 // CHECK1-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
 437 // CHECK1-NEXT:    ret void
 438 //
 439 //
 440 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined
 441 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
 442 // CHECK1-NEXT:  entry:
 443 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 444 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 445 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 446 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 447 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
 448 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 449 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 450 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 451 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 452 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 453 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 454 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
 455 // CHECK1-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
 456 // CHECK1-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 8
 457 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 458 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 459 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 460 // CHECK1-NEXT:    store ptr undef, ptr [[_TMP1]], align 8
 461 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 462 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 463 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 464 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 465 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
 466 // CHECK1-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
 467 // CHECK1-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
 468 // CHECK1:       arrayctor.loop:
 469 // CHECK1-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
 470 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
 471 // CHECK1-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1
 472 // CHECK1-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
 473 // CHECK1-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
 474 // CHECK1:       arrayctor.cont:
 475 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
 476 // CHECK1-NEXT:    store ptr [[VAR]], ptr [[_TMP2]], align 8
 477 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 478 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 479 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 480 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 481 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
 482 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 483 // CHECK1:       cond.true:
 484 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 485 // CHECK1:       cond.false:
 486 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 487 // CHECK1-NEXT:    br label [[COND_END]]
 488 // CHECK1:       cond.end:
 489 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
 490 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 491 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 492 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
 493 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 494 // CHECK1:       omp.inner.for.cond:
 495 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 496 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 497 // CHECK1-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
 498 // CHECK1-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
 499 // CHECK1:       omp.inner.for.cond.cleanup:
 500 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
 501 // CHECK1:       omp.inner.for.body:
 502 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 503 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
 504 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 505 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
 506 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4
 507 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4
 508 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
 509 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]
 510 // CHECK1-NEXT:    store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4
 511 // CHECK1-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8
 512 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4
 513 // CHECK1-NEXT:    [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
 514 // CHECK1-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]]
 515 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false)
 516 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 517 // CHECK1:       omp.body.continue:
 518 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 519 // CHECK1:       omp.inner.for.inc:
 520 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 521 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1
 522 // CHECK1-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
 523 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 524 // CHECK1:       omp.inner.for.end:
 525 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 526 // CHECK1:       omp.loop.exit:
 527 // CHECK1-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 528 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4
 529 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]])
 530 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
 531 // CHECK1-NEXT:    [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
 532 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2
 533 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 534 // CHECK1:       arraydestroy.body:
 535 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 536 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 537 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
 538 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
 539 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
 540 // CHECK1:       arraydestroy.done8:
 541 // CHECK1-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 542 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4
 543 // CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP17]])
 544 // CHECK1-NEXT:    ret void
 545 //
 546 //
 547 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
 548 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 549 // CHECK1-NEXT:  entry:
 550 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 551 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 552 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 553 // CHECK1-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
 554 // CHECK1-NEXT:    ret void
 555 //
 556 //
 557 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
 558 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 559 // CHECK1-NEXT:  entry:
 560 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 561 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 562 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 563 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
 564 // CHECK1-NEXT:    store i32 0, ptr [[F]], align 4
 565 // CHECK1-NEXT:    ret void
 566 //
 567 //
 568 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
 569 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 570 // CHECK1-NEXT:  entry:
 571 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 572 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 573 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 574 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
 575 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 576 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
 577 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 578 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
 579 // CHECK1-NEXT:    ret void
 580 //
 581 //
 582 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
 583 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 584 // CHECK1-NEXT:  entry:
 585 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 586 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 587 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 588 // CHECK1-NEXT:    ret void
 589 //
 590 //
 591 // CHECK3-LABEL: define {{[^@]+}}@main
 592 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
 593 // CHECK3-NEXT:  entry:
 594 // CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 595 // CHECK3-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
 596 // CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 597 // CHECK3-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
 598 // CHECK3-NEXT:    ret i32 0
 599 //
 600 //
 601 // CHECK4-LABEL: define {{[^@]+}}@main
 602 // CHECK4-SAME: () #[[ATTR1:[0-9]+]] {
 603 // CHECK4-NEXT:  entry:
 604 // CHECK4-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 605 // CHECK4-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 606 // CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr getelementptr inbounds nuw ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr @__block_literal_global, i32 0, i32 3), align 8
 607 // CHECK4-NEXT:    call void [[TMP0]](ptr noundef @__block_literal_global)
 608 // CHECK4-NEXT:    ret i32 0
 609 //
 610 //
 611 // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke
 612 // CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] {
 613 // CHECK4-NEXT:  entry:
 614 // CHECK4-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8
 615 // CHECK4-NEXT:    [[BLOCK_ADDR:%.*]] = alloca ptr, align 8
 616 // CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
 617 // CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8
 618 // CHECK4-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @__main_block_invoke.omp_outlined)
 619 // CHECK4-NEXT:    ret void
 620 //
 621 //
 622 // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined
 623 // CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
 624 // CHECK4-NEXT:  entry:
 625 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 626 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 627 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 628 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 629 // CHECK4-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
 630 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 631 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 632 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 633 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 634 // CHECK4-NEXT:    [[G:%.*]] = alloca double, align 8
 635 // CHECK4-NEXT:    [[G1:%.*]] = alloca double, align 8
 636 // CHECK4-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 8
 637 // CHECK4-NEXT:    [[SVAR:%.*]] = alloca i32, align 4
 638 // CHECK4-NEXT:    [[SFVAR:%.*]] = alloca float, align 4
 639 // CHECK4-NEXT:    [[I:%.*]] = alloca i32, align 4
 640 // CHECK4-NEXT:    [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, align 8
 641 // CHECK4-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 642 // CHECK4-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 643 // CHECK4-NEXT:    store ptr undef, ptr [[_TMP1]], align 8
 644 // CHECK4-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 645 // CHECK4-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 646 // CHECK4-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 647 // CHECK4-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 648 // CHECK4-NEXT:    store ptr [[G1]], ptr [[_TMP2]], align 8
 649 // CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 650 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 651 // CHECK4-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 652 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 653 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
 654 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 655 // CHECK4:       cond.true:
 656 // CHECK4-NEXT:    br label [[COND_END:%.*]]
 657 // CHECK4:       cond.false:
 658 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 659 // CHECK4-NEXT:    br label [[COND_END]]
 660 // CHECK4:       cond.end:
 661 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
 662 // CHECK4-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 663 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 664 // CHECK4-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
 665 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 666 // CHECK4:       omp.inner.for.cond:
 667 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 668 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 669 // CHECK4-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
 670 // CHECK4-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 671 // CHECK4:       omp.inner.for.body:
 672 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 673 // CHECK4-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
 674 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 675 // CHECK4-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
 676 // CHECK4-NEXT:    store double 1.000000e+00, ptr [[G]], align 8
 677 // CHECK4-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8
 678 // CHECK4-NEXT:    store volatile double 1.000000e+00, ptr [[TMP8]], align 8
 679 // CHECK4-NEXT:    store i32 2, ptr [[SVAR]], align 4
 680 // CHECK4-NEXT:    store float 3.000000e+00, ptr [[SFVAR]], align 4
 681 // CHECK4-NEXT:    [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 0
 682 // CHECK4-NEXT:    store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8
 683 // CHECK4-NEXT:    [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 1
 684 // CHECK4-NEXT:    store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8
 685 // CHECK4-NEXT:    [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 2
 686 // CHECK4-NEXT:    store i32 0, ptr [[BLOCK_RESERVED]], align 4
 687 // CHECK4-NEXT:    [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 3
 688 // CHECK4-NEXT:    store ptr @g1_block_invoke_2, ptr [[BLOCK_INVOKE]], align 8
 689 // CHECK4-NEXT:    [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 4
 690 // CHECK4-NEXT:    store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR]], align 8
 691 // CHECK4-NEXT:    [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 5
 692 // CHECK4-NEXT:    [[TMP9:%.*]] = load volatile double, ptr [[G]], align 8
 693 // CHECK4-NEXT:    store volatile double [[TMP9]], ptr [[BLOCK_CAPTURED]], align 8
 694 // CHECK4-NEXT:    [[BLOCK_CAPTURED4:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 6
 695 // CHECK4-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8
 696 // CHECK4-NEXT:    store ptr [[TMP10]], ptr [[BLOCK_CAPTURED4]], align 8
 697 // CHECK4-NEXT:    [[BLOCK_CAPTURED5:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 7
 698 // CHECK4-NEXT:    [[TMP11:%.*]] = load i32, ptr [[SVAR]], align 4
 699 // CHECK4-NEXT:    store i32 [[TMP11]], ptr [[BLOCK_CAPTURED5]], align 8
 700 // CHECK4-NEXT:    [[BLOCK_CAPTURED6:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 8
 701 // CHECK4-NEXT:    [[TMP12:%.*]] = load float, ptr [[SFVAR]], align 4
 702 // CHECK4-NEXT:    store float [[TMP12]], ptr [[BLOCK_CAPTURED6]], align 4
 703 // CHECK4-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3
 704 // CHECK4-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8
 705 // CHECK4-NEXT:    call void [[TMP14]](ptr noundef [[BLOCK]])
 706 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 707 // CHECK4:       omp.body.continue:
 708 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 709 // CHECK4:       omp.inner.for.inc:
 710 // CHECK4-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 711 // CHECK4-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP15]], 1
 712 // CHECK4-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4
 713 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]]
 714 // CHECK4:       omp.inner.for.end:
 715 // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 716 // CHECK4:       omp.loop.exit:
 717 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
 718 // CHECK4-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP1]])
 719 // CHECK4-NEXT:    ret void
 720 //
 721 //
 722 // CHECK4-LABEL: define {{[^@]+}}@g1_block_invoke_2
 723 // CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {
 724 // CHECK4-NEXT:  entry:
 725 // CHECK4-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8
 726 // CHECK4-NEXT:    [[BLOCK_ADDR:%.*]] = alloca ptr, align 8
 727 // CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
 728 // CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8
 729 // CHECK4-NEXT:    [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5
 730 // CHECK4-NEXT:    store double 2.000000e+00, ptr [[BLOCK_CAPTURE_ADDR]], align 8
 731 // CHECK4-NEXT:    [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6
 732 // CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR1]], align 8
 733 // CHECK4-NEXT:    store double 2.000000e+00, ptr [[TMP0]], align 8
 734 // CHECK4-NEXT:    [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7
 735 // CHECK4-NEXT:    store i32 4, ptr [[BLOCK_CAPTURE_ADDR2]], align 8
 736 // CHECK4-NEXT:    [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 8
 737 // CHECK4-NEXT:    store float 9.000000e+00, ptr [[BLOCK_CAPTURE_ADDR3]], align 4
 738 // CHECK4-NEXT:    ret void
 739 //