llvm/test/MC/AMDGPU/gfx10_unsupported_dpp.s

   1 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
   2 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
   3 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1013 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
   4
   5 v_add_co_u32_dpp v255, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
   6 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
   7
   8 v_ashrrev_i16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
   9 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  10
  11 v_ceil_f64_dpp v[0:1], v[2:3] quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf
  12 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  13
  14 v_cmp_class_f16_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
  15 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  16
  17 v_cmp_class_f32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
  18 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  19
  20 v_cmp_eq_f16_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
  21 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  22
  23 v_cmp_eq_f32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
  24 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  25
  26 v_cmp_eq_i16_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
  27 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  28
  29 v_cmp_eq_i32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
  30 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  31
  32 v_cmp_eq_u16_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
  33 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  34
  35 v_cmp_eq_u32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
  36 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  37
  38 v_cmp_f_f16_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
  39 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  40
  41 v_cmp_f_f32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
  42 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  43
  44 v_cmp_f_i32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
  45 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  46
  47 v_cmp_f_u32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
  48 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  49
  50 v_cmp_ge_f16_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
  51 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  52
  53 v_cmp_ge_f32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
  54 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  55
  56 v_cmp_ge_i16_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
  57 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  58
  59 v_cmp_ge_i32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
  60 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  61
  62 v_cmp_ge_u16_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
  63 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  64
  65 v_cmp_ge_u32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
  66 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  67
  68 v_cmp_gt_f16_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
  69 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  70
  71 v_cmp_gt_f32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
  72 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  73
  74 v_cmp_gt_i16_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
  75 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  76
  77 v_cmp_gt_i32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
  78 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  79
  80 v_cmp_gt_u16_dpp v1, v2 row_shl:0x7 row_mask:0x0 bank_mask:0x0 fi:1
  81 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  82
  83 v_cmp_gt_u32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
  84 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  85
  86 v_cmp_le_f16_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
  87 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  88
  89 v_cmp_le_f32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
  90 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  91
  92 v_cmp_le_i16_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
  93 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  94
  95 v_cmp_le_i32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
  96 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
  97
  98 v_cmp_le_u16_dpp v1, v2 dpp8:[7,7,7,3,4,4,6,7] fi:1
  99 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 100
 101 v_cmp_le_u32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 102 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 103
 104 v_cmp_lg_f16_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 105 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 106
 107 v_cmp_lg_f32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 108 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 109
 110 v_cmp_lt_f16_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 111 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 112
 113 v_cmp_lt_f32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 114 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 115
 116 v_cmp_lt_i16_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 117 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 118
 119 v_cmp_lt_i32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 120 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 121
 122 v_cmp_lt_u16_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 123 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 124
 125 v_cmp_lt_u32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 126 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 127
 128 v_cmp_ne_i16_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 129 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 130
 131 v_cmp_ne_i32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 132 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 133
 134 v_cmp_ne_u16_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 135 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 136
 137 v_cmp_ne_u32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 138 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 139
 140 v_cmp_neq_f16_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 141 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 142
 143 v_cmp_neq_f32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 144 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 145
 146 v_cmp_nge_f16_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 147 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 148
 149 v_cmp_nge_f32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 150 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 151
 152 v_cmp_ngt_f16_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 153 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 154
 155 v_cmp_ngt_f32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 156 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 157
 158 v_cmp_nle_f16_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 159 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 160
 161 v_cmp_nle_f32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 162 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 163
 164 v_cmp_nlg_f16_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 165 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 166
 167 v_cmp_nlg_f32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 168 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 169
 170 v_cmp_nlt_f16_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 171 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 172
 173 v_cmp_nlt_f32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 174 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 175
 176 v_cmp_o_f16_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 177 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 178
 179 v_cmp_o_f32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 180 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 181
 182 v_cmp_t_i32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 183 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 184
 185 v_cmp_t_u32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 186 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 187
 188 v_cmp_tru_f16_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 189 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 190
 191 v_cmp_tru_f32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 192 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 193
 194 v_cmp_u_f16_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 195 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 196
 197 v_cmp_u_f32_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 198 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 199
 200 v_cmpx_class_f16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 201 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 202
 203 v_cmpx_class_f32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 204 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 205
 206 v_cmpx_eq_f16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 207 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 208
 209 v_cmpx_eq_f32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 210 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 211
 212 v_cmpx_eq_i16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 213 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 214
 215 v_cmpx_eq_i32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 216 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 217
 218 v_cmpx_eq_u16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 219 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 220
 221 v_cmpx_eq_u32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 222 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 223
 224 v_cmpx_f_f16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 225 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 226
 227 v_cmpx_f_f32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 228 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 229
 230 v_cmpx_f_i32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 231 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 232
 233 v_cmpx_f_u32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 234 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 235
 236 v_cmpx_ge_f16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 237 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 238
 239 v_cmpx_ge_f32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 240 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 241
 242 v_cmpx_ge_i16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 243 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 244
 245 v_cmpx_ge_i32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 246 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 247
 248 v_cmpx_ge_u16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 249 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 250
 251 v_cmpx_ge_u32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 252 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 253
 254 v_cmpx_gt_f16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 255 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 256
 257 v_cmpx_gt_f32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 258 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 259
 260 v_cmpx_gt_i16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 261 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 262
 263 v_cmpx_gt_i32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 264 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 265
 266 v_cmpx_gt_u16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 267 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 268
 269 v_cmpx_gt_u32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 270 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 271
 272 v_cmpx_le_f16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 273 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 274
 275 v_cmpx_le_f32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 276 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 277
 278 v_cmpx_le_i16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 279 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 280
 281 v_cmpx_le_i32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 282 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 283
 284 v_cmpx_le_u16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 285 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 286
 287 v_cmpx_le_u32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 288 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 289
 290 v_cmpx_lg_f16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 291 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 292
 293 v_cmpx_lg_f32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 294 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 295
 296 v_cmpx_lt_f16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 297 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 298
 299 v_cmpx_lt_f32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 300 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 301
 302 v_cmpx_lt_i16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 303 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 304
 305 v_cmpx_lt_i32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 306 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 307
 308 v_cmpx_lt_u16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 309 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 310
 311 v_cmpx_lt_u32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 312 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 313
 314 v_cmpx_ne_i16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 315 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 316
 317 v_cmpx_ne_i32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 318 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 319
 320 v_cmpx_ne_u16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 321 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 322
 323 v_cmpx_ne_u32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 324 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 325
 326 v_cmpx_neq_f16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 327 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 328
 329 v_cmpx_neq_f32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 330 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 331
 332 v_cmpx_nge_f16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 333 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 334
 335 v_cmpx_nge_f32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 336 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 337
 338 v_cmpx_ngt_f16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 339 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 340
 341 v_cmpx_ngt_f32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 342 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 343
 344 v_cmpx_nle_f16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 345 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 346
 347 v_cmpx_nle_f32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 348 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 349
 350 v_cmpx_nlg_f16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 351 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 352
 353 v_cmpx_nlg_f32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 354 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 355
 356 v_cmpx_nlt_f16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 357 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 358
 359 v_cmpx_nlt_f32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 360 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 361
 362 v_cmpx_o_f16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 363 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 364
 365 v_cmpx_o_f32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 366 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 367
 368 v_cmpx_t_i32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 369 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 370
 371 v_cmpx_t_u32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 372 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 373
 374 v_cmpx_tru_f16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 375 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 376
 377 v_cmpx_tru_f32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 378 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 379
 380 v_cmpx_u_f16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 381 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 382
 383 v_cmpx_u_f32_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 384 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 385
 386 v_cvt_f32_f64_dpp v5, v[2:3] row_newbcast:1 row_mask:0xf bank_mask:0xf
 387 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 388
 389 v_cvt_i32_f64_dpp v5, v[2:3] row_newbcast:1 row_mask:0xf bank_mask:0xf
 390 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 391
 392 v_cvt_u32_f64_dpp v5, v[2:3] row_newbcast:1 row_mask:0xf bank_mask:0xf
 393 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 394
 395 v_floor_f64_dpp v[10:11], v[2:3] row_newbcast:1 row_mask:0xf bank_mask:0xf
 396 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 397
 398 v_fract_f64_dpp v[10:11], v[2:3] row_newbcast:1 row_mask:0xf bank_mask:0xf
 399 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 400
 401 v_frexp_exp_i32_f64_dpp v5, v[2:3] row_newbcast:1 row_mask:0xf bank_mask:0xf
 402 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 403
 404 v_frexp_mant_f64_dpp v[10:11], v[2:3] row_newbcast:1 row_mask:0xf bank_mask:0xf
 405 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 406
 407 v_lshlrev_b16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 408 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 409
 410 v_lshrrev_b16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 411 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 412
 413 v_max_i16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 414 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 415
 416 v_max_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 417 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 418
 419 v_min_i16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 420 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 421
 422 v_min_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 423 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 424
 425 v_mul_lo_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 426 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 427
 428 v_sub_co_u32_dpp v255, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 429 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 430
 431 v_subrev_co_u32_dpp v255, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 432 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 433
 434 v_trunc_f64_dpp v[10:11], v[2:3] row_newbcast:1 row_mask:0xf bank_mask:0xf
 435 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported