[RemoveDIs][DebugInfo] Update SROA to handle DPVAssigns (#78475)
[llvm-project.git] / llvm / test / MC / AMDGPU / gfx11_asm_vinterp_err.s
blob66b04c0d90869c235e972794f70ecdd53861d2ef
1 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck %s -check-prefix=GCN-ERR --implicit-check-not=error: --strict-whitespace
2 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 %s 2>&1 | FileCheck %s -check-prefix=GCN-ERR --implicit-check-not=error: --strict-whitespace
4 //===----------------------------------------------------------------------===//
5 // VINTERP src operands must be VGPRs.
6 // Check that other operand kinds are rejected by assembler.
7 //===----------------------------------------------------------------------===//
9 v_interp_p10_f32 v0, s1, v2, v3
10 // GCN-ERR: :[[@LINE-1]]:22: error: invalid operand for instruction
12 v_interp_p10_f32 v0, v1, s2, v3
13 // GCN-ERR: :[[@LINE-1]]:26: error: invalid operand for instruction
15 v_interp_p10_f32 v0, v1, v2, s3
16 // GCN-ERR: :[[@LINE-1]]:30: error: invalid operand for instruction
18 v_interp_p2_f32 v0, 1, v2, v3
19 // GCN-ERR: :[[@LINE-1]]:21: error: invalid operand for instruction
21 v_interp_p2_f32 v0, v1, 2, v3
22 // GCN-ERR: :[[@LINE-1]]:25: error: invalid operand for instruction
24 v_interp_p2_f32 v0, v1, v2, 3
25 // GCN-ERR: :[[@LINE-1]]:29: error: invalid operand for instruction
27 v_interp_p10_f16_f32 v0, s1, v2, v3
28 // GCN-ERR: :[[@LINE-1]]:26: error: invalid operand for instruction
30 v_interp_p10_f16_f32 v0, v1, s2, v3
31 // GCN-ERR: :[[@LINE-1]]:30: error: invalid operand for instruction
33 v_interp_p10_f16_f32 v0, v1, v2, s3
34 // GCN-ERR: :[[@LINE-1]]:34: error: invalid operand for instruction
36 v_interp_p2_f16_f32 v0, 1, v2, v3
37 // GCN-ERR: :[[@LINE-1]]:25: error: invalid operand for instruction
39 v_interp_p2_f16_f32 v0, v1, 2, v3
40 // GCN-ERR: :[[@LINE-1]]:29: error: invalid operand for instruction
42 v_interp_p2_f16_f32 v0, v1, v2, 3
43 // GCN-ERR: :[[@LINE-1]]:33: error: invalid operand for instruction