llvm/test/MC/AMDGPU/vop2-err.s

   1 // RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck --implicit-check-not=error: %s
   2 // RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck --implicit-check-not=error: %s
   3
   4 //===----------------------------------------------------------------------===//
   5 // Generic checks
   6 //===----------------------------------------------------------------------===//
   7
   8 v_mul_i32_i24 v1, v2, 100
   9 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: literal operands are not supported
  10
  11 //===----------------------------------------------------------------------===//
  12 // _e32 checks
  13 //===----------------------------------------------------------------------===//
  14
  15 // Immediate src1
  16 v_mul_i32_i24_e32 v1, v2, 100
  17 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  18
  19 // sgpr src1
  20 v_mul_i32_i24_e32 v1, v2, s3
  21 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  22
  23 v_cndmask_b32_e32 v1, v2, v3, s[0:1]
  24 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  25
  26 //===----------------------------------------------------------------------===//
  27 // _e64 checks
  28 //===----------------------------------------------------------------------===//
  29
  30 // Immediate src0
  31 v_mul_i32_i24_e64 v1, 100, v3
  32 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: literal operands are not supported
  33
  34 // Immediate src1
  35 v_mul_i32_i24_e64 v1, v2, 100
  36 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: literal operands are not supported
  37
  38 v_add_i32_e32 v1, s[0:1], v2, v3
  39 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  40
  41 v_addc_u32_e32 v1, vcc, v2, v3, s[2:3]
  42 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  43
  44 v_addc_u32_e32 v1, s[0:1], v2, v3, s[2:3]
  45 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  46
  47 v_addc_u32_e32 v1, vcc, v2, v3, -1
  48 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  49
  50 v_addc_u32_e32 v1, vcc, v2, v3, 123
  51 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  52
  53 v_addc_u32_e32 v1, vcc, v2, v3, s0
  54 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  55
  56 v_addc_u32_e32 v1, -1, v2, v3, s0
  57 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  58
  59 v_addc_u32 v1, -1, v2, v3, vcc
  60 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  61
  62 v_addc_u32 v1, vcc, v2, v3, 0
  63 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  64
  65 v_addc_u32_e64 v1, s[0:1], v2, v3, 123
  66 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  67
  68 v_addc_u32_e64 v1, 0, v2, v3, s[0:1]
  69 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  70
  71 v_addc_u32_e64 v1, s[0:1], v2, v3, 0
  72 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  73
  74 v_addc_u32 v1, s[0:1], v2, v3, 123
  75 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  76
  77 // TODO: Constant bus restrictions