1 // RUN
: not llvm-mc
-triple
=amdgcn
-mcpu
=tonga
-show-encoding
%s | FileCheck
%s
--check-prefixes
=VI
,VI9
2 // RUN
: not llvm-mc
-triple
=amdgcn
-mcpu
=gfx900
-show-encoding
%s | FileCheck
%s
--check-prefixes
=GFX9
,VI9
4 // RUN
: not llvm-mc
-triple
=amdgcn
%s
2>&1 | FileCheck
%s
--check-prefixes
=NOSI
,NOSICI
--implicit-check-
not=error
:
5 // RUN
: not llvm-mc
-triple
=amdgcn
-mcpu
=tahiti
%s
2>&1 | FileCheck
%s
--check-prefixes
=NOSI
,NOSICI
--implicit-check-
not=error
:
6 // RUN
: not llvm-mc
-triple
=amdgcn
-mcpu
=bonaire
%s
2>&1 | FileCheck
%s
--check-prefixes
=NOSICI
,NOCI
--implicit-check-
not=error
:
7 // RUN
: not llvm-mc
-triple
=amdgcn
-mcpu
=tonga
%s
2>&1 | FileCheck
%s
--check-prefix
=NOVI
--implicit-check-
not=error
:
8 // RUN
: not llvm-mc
-triple
=amdgcn
-mcpu
=gfx900
%s
2>&1 | FileCheck
%s
--check-prefix
=NOGFX9
--implicit-check-
not=error
:
10 //===----------------------------------------------------------------------===//
11 // Check dpp_ctrl values
12 //===----------------------------------------------------------------------===//
14 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
15 // VI9
: v_mov_b32_dpp v0
, v0 quad_perm
:[0,2,1,1] row_mask
:0xf bank_mask
:0xf ; encoding
: [0xfa,0x02,0x00,0x7e,0x00,0x58,0x00,0xff]
16 v_mov_b32 v0
, v0 quad_perm
:[0,2,1,1]
18 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
19 // VI9
: v_mov_b32_dpp v0
, v0 row_shl
:1 row_mask
:0xf bank_mask
:0xf ; encoding
: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x01,0xff]
20 v_mov_b32 v0
, v0 row_shl
:1
22 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
23 // VI9
: v_mov_b32_dpp v0
, v0 row_shr
:15 row_mask
:0xf bank_mask
:0xf ; encoding
: [0xfa,0x02,0x00,0x7e,0x00,0x1f,0x01,0xff]
24 v_mov_b32 v0
, v0 row_shr
:0xf
26 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
27 // VI9
: v_mov_b32_dpp v0
, v0 row_ror
:12 row_mask
:0xf bank_mask
:0xf ; encoding
: [0xfa,0x02,0x00,0x7e,0x00,0x2c,0x01,0xff]
28 v_mov_b32 v0
, v0 row_ror
:0xc
30 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
31 // VI9
: v_mov_b32_dpp v0
, v0 wave_shl
:1 row_mask
:0xf bank_mask
:0xf ; encoding
: [0xfa,0x02,0x00,0x7e,0x00,0x30,0x01,0xff]
32 v_mov_b32 v0
, v0 wave_shl
:1
34 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
35 // VI9
: v_mov_b32_dpp v0
, v0 wave_rol
:1 row_mask
:0xf bank_mask
:0xf ; encoding
: [0xfa,0x02,0x00,0x7e,0x00,0x34,0x01,0xff]
36 v_mov_b32 v0
, v0 wave_rol
:1
38 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
39 // VI9
: v_mov_b32_dpp v0
, v0 wave_shr
:1 row_mask
:0xf bank_mask
:0xf ; encoding
: [0xfa,0x02,0x00,0x7e,0x00,0x38,0x01,0xff]
40 v_mov_b32 v0
, v0 wave_shr
:1
42 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
43 // VI9
: v_mov_b32_dpp v0
, v0 wave_ror
:1 row_mask
:0xf bank_mask
:0xf ; encoding
: [0xfa,0x02,0x00,0x7e,0x00,0x3c,0x01,0xff]
44 v_mov_b32 v0
, v0 wave_ror
:1
46 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: invalid operand for instruction
47 // VI9
: v_mov_b32_dpp v0
, v0 row_mirror row_mask
:0xf bank_mask
:0xf ; encoding
: [0xfa,0x02,0x00,0x7e,0x00,0x40,0x01,0xff]
48 v_mov_b32 v0
, v0 row_mirror
50 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: invalid operand for instruction
51 // VI9
: v_mov_b32_dpp v0
, v0 row_half_mirror row_mask
:0xf bank_mask
:0xf ; encoding
: [0xfa,0x02,0x00,0x7e,0x00,0x41,0x01,0xff]
52 v_mov_b32 v0
, v0 row_half_mirror
54 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
55 // VI9
: v_mov_b32_dpp v0
, v0 row_bcast
:15 row_mask
:0xf bank_mask
:0xf ; encoding
: [0xfa,0x02,0x00,0x7e,0x00,0x42,0x01,0xff]
56 v_mov_b32 v0
, v0 row_bcast
:15
58 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
59 // VI9
: v_mov_b32_dpp v0
, v0 row_bcast
:31 row_mask
:0xf bank_mask
:0xf ; encoding
: [0xfa,0x02,0x00,0x7e,0x00,0x43,0x01,0xff]
60 v_mov_b32 v0
, v0 row_bcast
:31
62 //===----------------------------------------------------------------------===//
63 // Check bound_control modifier.
64 // Both bound_ctrl
:0 and bound_ctrl
:1 are legal
and encoded as
1.
65 // See bug
35397 for details.
66 //===----------------------------------------------------------------------===//
68 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
69 // VI9
: v_mov_b32_dpp v0
, v0 quad_perm
:[1,3,0,1] row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xa1]
70 v_mov_b32 v0
, v0 quad_perm
:[1,3,0,1] row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
72 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
73 // VI9
: v_mov_b32_dpp v0
, v0 quad_perm
:[1,3,0,1] row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xa1]
74 v_mov_b32 v0
, v0 quad_perm
:[1,3,0,1] row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1
76 // NOSICI
: :[[@LINE+
3]]:{{[0-9]+}}: error
: not a valid operand.
77 // NOGFX9
: :[[@LINE+
2]]:{{[0-9]+}}: error
: invalid bound_ctrl value.
78 // NOVI
: :[[@LINE+
1]]:{{[0-9]+}}: error
: invalid bound_ctrl value.
79 v_mov_b32 v0
, v0 quad_perm
:[1,3,0,1] row_mask
:0xa bank_mask
:0x1 bound_ctrl
:-1
81 // NOSICI
: :[[@LINE+
3]]:{{[0-9]+}}: error
: not a valid operand.
82 // NOGFX9
: :[[@LINE+
2]]:{{[0-9]+}}: error
: invalid bound_ctrl value.
83 // NOVI
: :[[@LINE+
1]]:{{[0-9]+}}: error
: invalid bound_ctrl value.
84 v_mov_b32 v0
, v0 quad_perm
:[1,3,0,1] row_mask
:0xa bank_mask
:0x1 bound_ctrl
:2
86 //===----------------------------------------------------------------------===//
87 // Check optional fields
88 //===----------------------------------------------------------------------===//
90 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
91 // VI9
: v_mov_b32_dpp v0
, v0 quad_perm
:[1,3,0,1] row_mask
:0xa bank_mask
:0xf ; encoding
: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x00,0xaf]
92 v_mov_b32 v0
, v0 quad_perm
:[1,3,0,1] row_mask
:0xa
94 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
95 // VI9
: v_mov_b32_dpp v0
, v0 quad_perm
:[1,3,0,1] row_mask
:0xf bank_mask
:0x1 ; encoding
: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x00,0xf1]
96 v_mov_b32 v0
, v0 quad_perm
:[1,3,0,1] bank_mask
:0x1
98 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
99 // VI9
: v_mov_b32_dpp v0
, v0 quad_perm
:[1,3,0,1] row_mask
:0xf bank_mask
:0xf bound_ctrl
:1 ; encoding
: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xff]
100 v_mov_b32 v0
, v0 quad_perm
:[1,3,0,1] bound_ctrl
:0
102 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
103 // VI9
: v_mov_b32_dpp v0
, v0 quad_perm
:[1,3,0,1] row_mask
:0xa bank_mask
:0x1 ; encoding
: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x00,0xa1]
104 v_mov_b32 v0
, v0 quad_perm
:[1,3,0,1] row_mask
:0xa bank_mask
:0x1
106 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
107 // VI9
: v_mov_b32_dpp v0
, v0 quad_perm
:[1,3,0,1] row_mask
:0xa bank_mask
:0xf bound_ctrl
:1 ; encoding
: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xaf]
108 v_mov_b32 v0
, v0 quad_perm
:[1,3,0,1] row_mask
:0xa bound_ctrl
:0
110 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
111 // VI9
: v_mov_b32_dpp v0
, v0 quad_perm
:[1,3,0,1] row_mask
:0xf bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xf1]
112 v_mov_b32 v0
, v0 quad_perm
:[1,3,0,1] bank_mask
:0x1 bound_ctrl
:0
114 //===----------------------------------------------------------------------===//
116 //===----------------------------------------------------------------------===//
118 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
119 // VI9
: v_add_f32_dpp v0
, -v0
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x00,0x00,0x02,0x00,0x01,0x19,0xa1]
120 v_add_f32 v0
, -v0
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
122 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
123 // VI9
: v_add_f32_dpp v0
, v0
, |v0| row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x00,0x00,0x02,0x00,0x01,0x89,0xa1]
124 v_add_f32 v0
, v0
, |v0| row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
126 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
127 // VI9
: v_add_f32_dpp v0
, -v0
, |v0| row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x00,0x00,0x02,0x00,0x01,0x99,0xa1]
128 v_add_f32 v0
, -v0
, |v0| row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
130 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
131 // VI9
: v_add_f32_dpp v0
, |v0|
, -v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x00,0x00,0x02,0x00,0x01,0x69,0xa1]
132 v_add_f32 v0
, |v0|
, -v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
134 //===----------------------------------------------------------------------===//
135 // Check VOP1 opcodes
136 //===----------------------------------------------------------------------===//
138 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
139 // GCN
: v_nop row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x00,0x00,0x7e,0x00,0x01,0x09,0xa1]
140 v_nop row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
142 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
143 // VI9
: v_cvt_u32_f32_dpp v0
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x0e,0x00,0x7e,0x00,0x01,0x09,0xa1]
144 v_cvt_u32_f32 v0
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
146 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
147 // VI9
: v_fract_f32_dpp v0
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x36,0x00,0x7e,0x00,0x01,0x09,0xa1]
148 v_fract_f32 v0
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
150 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
151 // VI9
: v_sin_f32_dpp v0
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x52,0x00,0x7e,0x00,0x01,0x09,0xa1]
152 v_sin_f32 v0
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
154 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
155 // VI9
: v_mov_b32_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x02,0x02,0x7e,0x00,0x01,0x09,0xa1]
156 v_mov_b32 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
158 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
159 // VI9
: v_cvt_f32_i32_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x0a,0x02,0x7e,0x00,0x01,0x09,0xa1]
160 v_cvt_f32_i32 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
162 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
163 // VI9
: v_cvt_f32_u32_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x0c,0x02,0x7e,0x00,0x01,0x09,0xa1]
164 v_cvt_f32_u32 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
166 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
167 // VI9
: v_cvt_i32_f32_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x10,0x02,0x7e,0x00,0x01,0x09,0xa1]
168 v_cvt_i32_f32 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
170 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
171 // VI9
: v_cvt_f16_f32_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x14,0x02,0x7e,0x00,0x01,0x09,0xa1]
172 v_cvt_f16_f32 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
174 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
175 // VI9
: v_cvt_f32_f16_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x16,0x02,0x7e,0x00,0x01,0x09,0xa1]
176 v_cvt_f32_f16 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
178 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
179 // VI9
: v_cvt_rpi_i32_f32_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x18,0x02,0x7e,0x00,0x01,0x09,0xa1]
180 v_cvt_rpi_i32_f32 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
182 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
183 // VI9
: v_cvt_flr_i32_f32_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x1a,0x02,0x7e,0x00,0x01,0x09,0xa1]
184 v_cvt_flr_i32_f32 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
186 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
187 // VI9
: v_cvt_off_f32_i4_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x1c,0x02,0x7e,0x00,0x01,0x09,0xa1]
188 v_cvt_off_f32_i4 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
190 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
191 // VI9
: v_cvt_f32_ubyte0_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x22,0x02,0x7e,0x00,0x01,0x09,0xa1]
192 v_cvt_f32_ubyte0 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
194 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
195 // VI9
: v_cvt_f32_ubyte1_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x24,0x02,0x7e,0x00,0x01,0x09,0xa1]
196 v_cvt_f32_ubyte1 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
198 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
199 // VI9
: v_cvt_f32_ubyte2_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x26,0x02,0x7e,0x00,0x01,0x09,0xa1]
200 v_cvt_f32_ubyte2 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
202 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
203 // VI9
: v_cvt_f32_ubyte3_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x28,0x02,0x7e,0x00,0x01,0x09,0xa1]
204 v_cvt_f32_ubyte3 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
206 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
207 // VI9
: v_trunc_f32_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x38,0x02,0x7e,0x00,0x01,0x09,0xa1]
208 v_trunc_f32 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
210 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
211 // VI9
: v_ceil_f32_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x3a,0x02,0x7e,0x00,0x01,0x09,0xa1]
212 v_ceil_f32 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
214 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
215 // VI9
: v_rndne_f32_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x3c,0x02,0x7e,0x00,0x01,0x09,0xa1]
216 v_rndne_f32 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
218 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
219 // VI9
: v_floor_f32_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x3e,0x02,0x7e,0x00,0x01,0x09,0xa1]
220 v_floor_f32 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
222 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
223 // VI9
: v_exp_f32_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x40,0x02,0x7e,0x00,0x01,0x09,0xa1]
224 v_exp_f32 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
226 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
227 // VI9
: v_log_f32_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x42,0x02,0x7e,0x00,0x01,0x09,0xa1]
228 v_log_f32 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
230 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
231 // VI9
: v_rcp_f32_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x44,0x02,0x7e,0x00,0x01,0x09,0xa1]
232 v_rcp_f32 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
234 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
235 // VI9
: v_rcp_iflag_f32_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x46,0x02,0x7e,0x00,0x01,0x09,0xa1]
236 v_rcp_iflag_f32 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
238 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
239 // VI9
: v_rsq_f32_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x48,0x02,0x7e,0x00,0x01,0x09,0xa1]
240 v_rsq_f32 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
242 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
243 // VI9
: v_sqrt_f32_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x4e,0x02,0x7e,0x00,0x01,0x09,0xa1]
244 v_sqrt_f32 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
246 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
247 // VI9
: v_cos_f32_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x54,0x02,0x7e,0x00,0x01,0x09,0xa1]
248 v_cos_f32 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
250 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
251 // VI9
: v_not_b32_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x56,0x02,0x7e,0x00,0x01,0x09,0xa1]
252 v_not_b32 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
254 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
255 // VI9
: v_bfrev_b32_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x58,0x02,0x7e,0x00,0x01,0x09,0xa1]
256 v_bfrev_b32 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
258 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
259 // VI9
: v_ffbh_u32_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x5a,0x02,0x7e,0x00,0x01,0x09,0xa1]
260 v_ffbh_u32 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
262 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
263 // VI9
: v_ffbl_b32_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x5c,0x02,0x7e,0x00,0x01,0x09,0xa1]
264 v_ffbl_b32 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
266 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
267 // VI9
: v_ffbh_i32_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x5e,0x02,0x7e,0x00,0x01,0x09,0xa1]
268 v_ffbh_i32 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
270 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
271 // VI9
: v_frexp_exp_i32_f32_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x66,0x02,0x7e,0x00,0x01,0x09,0xa1]
272 v_frexp_exp_i32_f32 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
274 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
275 // VI9
: v_frexp_mant_f32_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x68,0x02,0x7e,0x00,0x01,0x09,0xa1]
276 v_frexp_mant_f32 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
278 // VI9
: v_log_legacy_f32_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x98,0x02,0x7e,0x00,0x01,0x09,0xa1]
279 // NOSI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
280 // NOCI
: :[[@LINE+
1]]:{{[0-9]+}}: error
: not a valid operand.
281 v_log_legacy_f32 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
283 // VI9
: v_exp_legacy_f32_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x96,0x02,0x7e,0x00,0x01,0x09,0xa1]
284 // NOSI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
285 // NOCI
: :[[@LINE+
1]]:{{[0-9]+}}: error
: not a valid operand.
286 v_exp_legacy_f32 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
288 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
289 // VI9
: v_cvt_f16_u16_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x72,0x02,0x7e,0x00,0x01,0x09,0xa1]
290 v_cvt_f16_u16 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
292 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
293 // VI9
: v_cvt_f16_i16_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x74,0x02,0x7e,0x00,0x01,0x09,0xa1]
294 v_cvt_f16_i16 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
296 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
297 // VI9
: v_cvt_u16_f16_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x76,0x02,0x7e,0x00,0x01,0x09,0xa1]
298 v_cvt_u16_f16 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
300 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
301 // VI9
: v_cvt_i16_f16_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x78,0x02,0x7e,0x00,0x01,0x09,0xa1]
302 v_cvt_i16_f16 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
304 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
305 // VI9
: v_rcp_f16_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x7a,0x02,0x7e,0x00,0x01,0x09,0xa1]
306 v_rcp_f16 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
308 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
309 // VI9
: v_sqrt_f16_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x7c,0x02,0x7e,0x00,0x01,0x09,0xa1]
310 v_sqrt_f16 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
312 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
313 // VI9
: v_rsq_f16_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x7e,0x02,0x7e,0x00,0x01,0x09,0xa1]
314 v_rsq_f16 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
316 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
317 // VI9
: v_log_f16_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x80,0x02,0x7e,0x00,0x01,0x09,0xa1]
318 v_log_f16 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
320 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
321 // VI9
: v_exp_f16_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x82,0x02,0x7e,0x00,0x01,0x09,0xa1]
322 v_exp_f16 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
324 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
325 // VI9
: v_frexp_mant_f16_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x84,0x02,0x7e,0x00,0x01,0x09,0xa1]
326 v_frexp_mant_f16 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
328 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
329 // VI9
: v_frexp_exp_i16_f16_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x86,0x02,0x7e,0x00,0x01,0x09,0xa1]
330 v_frexp_exp_i16_f16 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
332 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
333 // VI9
: v_floor_f16_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x88,0x02,0x7e,0x00,0x01,0x09,0xa1]
334 v_floor_f16 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
336 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
337 // VI9
: v_ceil_f16_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x8a,0x02,0x7e,0x00,0x01,0x09,0xa1]
338 v_ceil_f16 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
340 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
341 // VI9
: v_trunc_f16_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x8c,0x02,0x7e,0x00,0x01,0x09,0xa1]
342 v_trunc_f16 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
344 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
345 // VI9
: v_rndne_f16_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x8e,0x02,0x7e,0x00,0x01,0x09,0xa1]
346 v_rndne_f16 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
348 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
349 // VI9
: v_fract_f16_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x90,0x02,0x7e,0x00,0x01,0x09,0xa1]
350 v_fract_f16 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
352 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
353 // VI9
: v_sin_f16_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x92,0x02,0x7e,0x00,0x01,0x09,0xa1]
354 v_sin_f16 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
356 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
357 // VI9
: v_cos_f16_dpp v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x94,0x02,0x7e,0x00,0x01,0x09,0xa1]
358 v_cos_f16 v1
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
360 // GFX9
: v_cvt_norm_i16_f16_dpp v5
, |v1| quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0 ; encoding
: [0xfa,0x9a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
361 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
362 // NOVI
: error
: instruction
not supported on this GPU
363 v_cvt_norm_i16_f16_dpp v5
, |v1| quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
365 // GFX9
: v_cvt_norm_u16_f16_dpp v5
, v1 quad_perm
:[3,2,1,0] row_mask
:0x0 bank_mask
:0x0 ; encoding
: [0xfa,0x9c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
366 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
367 // NOVI
: error
: instruction
not supported on this GPU
368 v_cvt_norm_u16_f16_dpp v5
, v1 quad_perm
:[3,2,1,0] row_mask
:0x0 bank_mask
:0x0
370 // GFX9
: v_sat_pk_u8_i16_dpp v5
, v1 row_ror
:15 row_mask
:0x0 bank_mask
:0x0 ; encoding
: [0xfa,0x9e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
371 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
372 // NOVI
: error
: instruction
not supported on this GPU
373 v_sat_pk_u8_i16_dpp v5
, v1 row_ror
:15 row_mask
:0x0 bank_mask
:0x0
375 // NOSICI
: :[[@LINE+
3]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
376 // NOVI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
377 // GFX9
: v_screen_partition_4se_b32_dpp v5
, v1 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0 bound_ctrl
:1 ; encoding
: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
378 v_screen_partition_4se_b32_dpp v5
, v1 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0 bound_ctrl
:0
380 //===----------------------------------------------------------------------===//
381 // Check VOP2 opcodes
382 //===----------------------------------------------------------------------===//
383 // ToDo
: VOP2bInst instructions
: v_add_u32
, v_sub_u32
... (vcc and ApplyMnemonic in AsmMatcherEmitter.cpp)
385 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
386 // VI9
: v_mac_f32_dpp v0
, v0
, v0 row_shl
:1 row_mask
:0xf bank_mask
:0xf ; encoding
: [0xfa,0x00,0x00,0x2c,0x00,0x01,0x01,0xff]
387 v_mac_f32 v0
, v0
, v0 row_shl
:1
389 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
390 // VI9
: v_mac_f32_dpp v0
, v0
, v0 row_shr
:15 row_mask
:0xf bank_mask
:0xf ; encoding
: [0xfa,0x00,0x00,0x2c,0x00,0x1f,0x01,0xff]
391 v_mac_f32 v0
, v0
, v0 row_shr
:0xf
393 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
394 // VI9
: v_mac_f32_dpp v0
, v0
, v0 quad_perm
:[1,3,0,1] row_mask
:0xa bank_mask
:0xf bound_ctrl
:1 ; encoding
: [0xfa,0x00,0x00,0x2c,0x00,0x4d,0x08,0xaf]
395 v_mac_f32 v0
, v0
, v0 quad_perm
:[1,3,0,1] row_mask
:0xa bound_ctrl
:0
397 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
398 // VI9
: v_add_f32_dpp v0
, v0
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x00,0x00,0x02,0x00,0x01,0x09,0xa1]
399 v_add_f32 v0
, v0
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
401 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
402 // VI9
: v_min_f32_dpp v0
, v0
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x00,0x00,0x14,0x00,0x01,0x09,0xa1]
403 v_min_f32 v0
, v0
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
405 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
406 // VI9
: v_and_b32_dpp v0
, v0
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x00,0x00,0x26,0x00,0x01,0x09,0xa1]
407 v_and_b32 v0
, v0
, v0 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
409 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
410 // VI9
: v_mul_i32_i24_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x0c,0x02,0x01,0x09,0xa1]
411 v_mul_i32_i24 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
413 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
414 // VI9
: v_sub_f32_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x04,0x02,0x01,0x09,0xa1]
415 v_sub_f32 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
417 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
418 // VI9
: v_subrev_f32_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x06,0x02,0x01,0x09,0xa1]
419 v_subrev_f32 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
421 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
422 // VI9
: v_mul_f32_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x0a,0x02,0x01,0x09,0xa1]
423 v_mul_f32 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
425 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
426 // VI9
: v_mul_hi_i32_i24_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x0e,0x02,0x01,0x09,0xa1]
427 v_mul_hi_i32_i24 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
429 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
430 // VI9
: v_mul_u32_u24_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x10,0x02,0x01,0x09,0xa1]
431 v_mul_u32_u24 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
433 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
434 // VI9
: v_mul_hi_u32_u24_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x12,0x02,0x01,0x09,0xa1]
435 v_mul_hi_u32_u24 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
437 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
438 // VI9
: v_max_f32_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x16,0x02,0x01,0x09,0xa1]
439 v_max_f32 v1
, v2 v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
441 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
442 // VI9
: v_min_i32_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x18,0x02,0x01,0x09,0xa1]
443 v_min_i32 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
445 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
446 // VI9
: v_max_i32_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x1a,0x02,0x01,0x09,0xa1]
447 v_max_i32 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
449 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
450 // VI9
: v_min_u32_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x1c,0x02,0x01,0x09,0xa1]
451 v_min_u32 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
453 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
454 // VI9
: v_max_u32_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x1e,0x02,0x01,0x09,0xa1]
455 v_max_u32 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
457 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
458 // VI9
: v_lshrrev_b32_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x20,0x02,0x01,0x09,0xa1]
459 v_lshrrev_b32 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
461 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
462 // VI9
: v_ashrrev_i32_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x22,0x02,0x01,0x09,0xa1]
463 v_ashrrev_i32 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
465 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
466 // VI9
: v_lshlrev_b32_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x24,0x02,0x01,0x09,0xa1]
467 v_lshlrev_b32 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
469 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
470 // VI9
: v_or_b32_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x28,0x02,0x01,0x09,0xa1]
471 v_or_b32 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
473 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
474 // VI9
: v_xor_b32_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x2a,0x02,0x01,0x09,0xa1]
475 v_xor_b32 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
477 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
478 // VI9
: v_add_f16_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x3e,0x02,0x01,0x09,0xa1]
479 v_add_f16 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
481 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
482 // VI9
: v_sub_f16_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x40,0x02,0x01,0x09,0xa1]
483 v_sub_f16 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
485 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
486 // VI9
: v_subrev_f16_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x42,0x02,0x01,0x09,0xa1]
487 v_subrev_f16 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
489 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
490 // VI9
: v_mul_f16_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x44,0x02,0x01,0x09,0xa1]
491 v_mul_f16 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
493 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
494 // VI9
: v_mac_f16_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x46,0x02,0x01,0x09,0xa1]
495 v_mac_f16 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
497 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
498 // VI9
: v_add_u16_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x4c,0x02,0x01,0x09,0xa1]
499 v_add_u16 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
501 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
502 // VI9
: v_sub_u16_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x4e,0x02,0x01,0x09,0xa1]
503 v_sub_u16 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
505 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
506 // VI9
: v_subrev_u16_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x50,0x02,0x01,0x09,0xa1]
507 v_subrev_u16 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
509 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
510 // VI9
: v_mul_lo_u16_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x52,0x02,0x01,0x09,0xa1]
511 v_mul_lo_u16 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
513 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
514 // VI9
: v_lshlrev_b16_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x54,0x02,0x01,0x09,0xa1]
515 v_lshlrev_b16 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
517 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
518 // VI9
: v_lshrrev_b16_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x56,0x02,0x01,0x09,0xa1]
519 v_lshrrev_b16 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
521 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
522 // VI9
: v_ashrrev_i16_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x58,0x02,0x01,0x09,0xa1]
523 v_ashrrev_i16 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
525 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
526 // VI9
: v_max_f16_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x5a,0x02,0x01,0x09,0xa1]
527 v_max_f16 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
529 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
530 // VI9
: v_min_f16_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x5c,0x02,0x01,0x09,0xa1]
531 v_min_f16 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
533 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
534 // VI9
: v_max_u16_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x5e,0x02,0x01,0x09,0xa1]
535 v_max_u16 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
537 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
538 // VI9
: v_max_i16_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x60,0x02,0x01,0x09,0xa1]
539 v_max_i16 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
541 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
542 // VI9
: v_min_u16_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x62,0x02,0x01,0x09,0xa1]
543 v_min_u16 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
545 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
546 // VI9
: v_min_i16_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x64,0x02,0x01,0x09,0xa1]
547 v_min_i16 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
549 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
550 // VI9
: v_ldexp_f16_dpp v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x66,0x02,0x01,0x09,0xa1]
551 v_ldexp_f16 v1
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
553 // NOSICI
: :[[@LINE+
3]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
554 // NOGFX9
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
555 // VI
: v_add_u32_dpp v1
, vcc
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x32,0x02,0x01,0x09,0xa1]
556 v_add_u32 v1
, vcc
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
558 // NOSICI
: :[[@LINE+
3]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
559 // NOGFX9
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
560 // VI
: v_sub_u32_dpp v1
, vcc
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x34,0x02,0x01,0x09,0xa1]
561 v_sub_u32 v1
, vcc
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
563 // NOSICI
: :[[@LINE+
3]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
564 // NOGFX9
: :[[@LINE+
2]]:{{[0-9]+}}: error
: not a valid operand.
565 // VI
: v_subrev_u32_dpp v1
, vcc
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x36,0x02,0x01,0x09,0xa1]
566 v_subrev_u32 v1
, vcc
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
568 // NOSICI
: :[[@LINE+
3]]:{{[0-9]+}}: error
: not a valid operand.
569 // NOGFX9
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
570 // VI
: v_addc_u32_dpp v1
, vcc
, v2
, v3
, vcc row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x38,0x02,0x01,0x09,0xa1]
571 v_addc_u32 v1
, vcc
, v2
, v3
, vcc row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
573 // NOSICI
: :[[@LINE+
3]]:{{[0-9]+}}: error
: not a valid operand.
574 // NOGFX9
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
575 // VI
: v_subb_u32_dpp v1
, vcc
, v2
, v3
, vcc row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x3a,0x02,0x01,0x09,0xa1]
576 v_subb_u32 v1
, vcc
, v2
, v3
, vcc row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
578 // NOSICI
: :[[@LINE+
3]]:{{[0-9]+}}: error
: not a valid operand.
579 // NOGFX9
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
580 // VI
: v_subbrev_u32_dpp v1
, vcc
, v2
, v3
, vcc row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x3c,0x02,0x01,0x09,0xa1]
581 v_subbrev_u32 v1
, vcc
, v2
, v3
, vcc row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
583 // NOSICI
: :[[@LINE+
3]]:{{[0-9]+}}: error
: not a valid operand.
584 // NOVI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
585 // GFX9
: v_add_co_u32_dpp v1
, vcc
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x32,0x02,0x01,0x09,0xa1]
586 v_add_co_u32 v1
, vcc
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
588 // NOSICI
: :[[@LINE+
3]]:{{[0-9]+}}: error
: not a valid operand.
589 // NOVI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
590 // GFX9
: v_sub_co_u32_dpp v1
, vcc
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x34,0x02,0x01,0x09,0xa1]
591 v_sub_co_u32 v1
, vcc
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
593 // NOSICI
: :[[@LINE+
3]]:{{[0-9]+}}: error
: not a valid operand.
594 // NOVI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
595 // GFX9
: v_subrev_co_u32_dpp v1
, vcc
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x36,0x02,0x01,0x09,0xa1]
596 v_subrev_co_u32 v1
, vcc
, v2
, v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
598 // NOSICI
: :[[@LINE+
3]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
599 // NOVI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
600 // GFX9
: v_addc_co_u32_dpp v1
, vcc
, v2
, v3
, vcc row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x38,0x02,0x01,0x09,0xa1]
601 v_addc_co_u32 v1
, vcc
, v2
, v3
, vcc row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
603 // NOSICI
: :[[@LINE+
3]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
604 // NOVI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
605 // GFX9
: v_subb_co_u32_dpp v1
, vcc
, v2
, v3
, vcc row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x3a,0x02,0x01,0x09,0xa1]
606 v_subb_co_u32 v1
, vcc
, v2
, v3
, vcc row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
608 // NOSICI
: :[[@LINE+
3]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
609 // NOVI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
610 // GFX9
: v_subbrev_co_u32_dpp v1
, vcc
, v2
, v3
, vcc row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:1 ; encoding
: [0xfa,0x06,0x02,0x3c,0x02,0x01,0x09,0xa1]
611 v_subbrev_co_u32 v1
, vcc
, v2
, v3
, vcc row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
613 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: dpp variant of this instruction is
not supported
614 // VI9
: v_cndmask_b32_dpp v5
, v1
, v2
, vcc quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0 ; encoding
: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x00]
615 v_cndmask_b32_dpp v5
, v1
, v2
, vcc quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
617 // NOSICI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: dpp variant of this instruction is
not supported
618 // VI9
: v_cndmask_b32_dpp v5
, v1
, v2
, vcc row_shl
:15 row_mask
:0x0 bank_mask
:0x0 ; encoding
: [0xfa,0x04,0x0a,0x00,0x01,0x0f,0x01,0x00]
619 v_cndmask_b32_dpp v5
, v1
, v2
, vcc row_shl
:15 row_mask
:0x0 bank_mask
:0x0
621 //===----------------------------------------------------------------------===//
622 // Check that immediates
and scalar regs are
not supported
623 //===----------------------------------------------------------------------===//
625 // NOSICI
: :[[@LINE+
3]]:{{[0-9]+}}: error
: not a valid operand
626 // NOVI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: invalid operand for instruction
627 // NOGFX9
: :[[@LINE+
1]]:{{[0-9]+}}: error
: invalid operand for instruction
628 v_mov_b32 v0
, 1 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
630 // NOSICI
: :[[@LINE+
3]]:{{[0-9]+}}: error
: not a valid operand
631 // NOVI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: invalid operand for instruction
632 // NOGFX9
: :[[@LINE+
1]]:{{[0-9]+}}: error
: invalid operand for instruction
633 v_and_b32 v0
, 42, v1 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
635 // NOSICI
: :[[@LINE+
3]]:{{[0-9]+}}: error
: not a valid operand.
636 // NOVI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: invalid operand for instruction
637 // NOGFX9
: :[[@LINE+
1]]:{{[0-9]+}}: error
: invalid operand for instruction
638 v_add_f32 v0
, v1
, 345 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
640 // NOSICI
: :[[@LINE+
3]]:{{[0-9]+}}: error
: not a valid operand
641 // NOVI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: invalid operand for instruction
642 // NOGFX9
: :[[@LINE+
1]]:{{[0-9]+}}: error
: invalid operand for instruction
643 v_mov_b32 v0
, s1 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
645 // NOSICI
: :[[@LINE+
3]]:{{[0-9]+}}: error
: not a valid operand
646 // NOVI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: invalid operand for instruction
647 // NOGFX9
: :[[@LINE+
1]]:{{[0-9]+}}: error
: invalid operand for instruction
648 v_and_b32 v0
, s42
, v1 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
650 // NOSICI
: :[[@LINE+
3]]:{{[0-9]+}}: error
: not a valid operand.
651 // NOVI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: invalid operand for instruction
652 // NOGFX9
: :[[@LINE+
1]]:{{[0-9]+}}: error
: invalid operand for instruction
653 v_add_f32 v0
, v1
, s45 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
655 //===----------------------------------------------------------------------===//
656 // Validate register size checks
(bug
37943)
657 //===----------------------------------------------------------------------===//
659 // NOSICI
: :[[@LINE+
3]]:{{[0-9]+}}: error
: dpp variant of this instruction is
not supported
660 // NOVI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: invalid operand for instruction
661 // NOGFX9
: :[[@LINE+
1]]:{{[0-9]+}}: error
: invalid operand for instruction
662 v_add_f32_dpp v5
, v
[1:2], v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
664 // NOSICI
: :[[@LINE+
3]]:{{[0-9]+}}: error
: dpp variant of this instruction is
not supported
665 // NOVI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: invalid operand for instruction
666 // NOGFX9
: :[[@LINE+
1]]:{{[0-9]+}}: error
: invalid operand for instruction
667 v_add_f32_dpp v5
, v
[1:3], v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
669 // NOSICI
: :[[@LINE+
3]]:{{[0-9]+}}: error
: dpp variant of this instruction is
not supported
670 // NOVI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: invalid operand for instruction
671 // NOGFX9
: :[[@LINE+
1]]:{{[0-9]+}}: error
: invalid operand for instruction
672 v_add_f32_dpp v5
, v1
, v
[1:2] quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
674 // NOSICI
: :[[@LINE+
3]]:{{[0-9]+}}: error
: dpp variant of this instruction is
not supported
675 // NOVI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: invalid operand for instruction
676 // NOGFX9
: :[[@LINE+
1]]:{{[0-9]+}}: error
: invalid operand for instruction
677 v_add_f32_dpp v5
, v1
, v
[1:4] quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
679 // NOSICI
: :[[@LINE+
3]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
680 // NOVI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: invalid operand for instruction
681 // NOGFX9
: :[[@LINE+
1]]:{{[0-9]+}}: error
: invalid operand for instruction
682 v_add_f16 v1
, v
[2:3], v3 row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0
684 // NOSICI
: :[[@LINE+
3]]:{{[0-9]+}}: error
: instruction
not supported on this GPU
685 // NOVI
: :[[@LINE+
2]]:{{[0-9]+}}: error
: invalid operand for instruction
686 // NOGFX9
: :[[@LINE+
1]]:{{[0-9]+}}: error
: invalid operand for instruction
687 v_add_f16 v1
, v3
, v
[2:3] row_shl
:1 row_mask
:0xa bank_mask
:0x1 bound_ctrl
:0