llvm/lib/Target/ARM/ARMISelLowering.h

   1 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the interfaces that ARM uses to lower LLVM code into a
  10 // selection DAG.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
  15 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
  16
  17 #include "MCTargetDesc/ARMBaseInfo.h"
  18 #include "llvm/ADT/SmallVector.h"
  19 #include "llvm/ADT/StringRef.h"
  20 #include "llvm/CodeGen/CallingConvLower.h"
  21 #include "llvm/CodeGen/ISDOpcodes.h"
  22 #include "llvm/CodeGen/MachineFunction.h"
  23 #include "llvm/CodeGen/SelectionDAGNodes.h"
  24 #include "llvm/CodeGen/TargetLowering.h"
  25 #include "llvm/CodeGen/ValueTypes.h"
  26 #include "llvm/IR/Attributes.h"
  27 #include "llvm/IR/CallingConv.h"
  28 #include "llvm/IR/Function.h"
  29 #include "llvm/IR/IRBuilder.h"
  30 #include "llvm/IR/InlineAsm.h"
  31 #include "llvm/Support/CodeGen.h"
  32 #include "llvm/Support/MachineValueType.h"
  33 #include <utility>
  34
  35 namespace llvm {
  36
  37 class ARMSubtarget;
  38 class DataLayout;
  39 class FastISel;
  40 class FunctionLoweringInfo;
  41 class GlobalValue;
  42 class InstrItineraryData;
  43 class Instruction;
  44 class MachineBasicBlock;
  45 class MachineInstr;
  46 class SelectionDAG;
  47 class TargetLibraryInfo;
  48 class TargetMachine;
  49 class TargetRegisterInfo;
  50 class VectorType;
  51
  52   namespace ARMISD {
  53
  54   // ARM Specific DAG Nodes
  55   enum NodeType : unsigned {
  56     // Start the numbering where the builtin ops and target ops leave off.
  57     FIRST_NUMBER = ISD::BUILTIN_OP_END,
  58
  59     Wrapper,    // Wrapper - A wrapper node for TargetConstantPool,
  60                 // TargetExternalSymbol, and TargetGlobalAddress.
  61     WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
  62                 // PIC mode.
  63     WrapperJT,  // WrapperJT - A wrapper node for TargetJumpTable
  64
  65     // Add pseudo op to model memcpy for struct byval.
  66     COPY_STRUCT_BYVAL,
  67
  68     CALL,        // Function call.
  69     CALL_PRED,   // Function call that's predicable.
  70     CALL_NOLINK, // Function call with branch not branch-and-link.
  71     tSECALL,     // CMSE non-secure function call.
  72     BRCOND,      // Conditional branch.
  73     BR_JT,       // Jumptable branch.
  74     BR2_JT,      // Jumptable branch (2 level - jumptable entry is a jump).
  75     RET_FLAG,    // Return with a flag operand.
  76     SERET_FLAG,  // CMSE Entry function return with a flag operand.
  77     INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
  78
  79     PIC_ADD, // Add with a PC operand and a PIC label.
  80
  81     ASRL, // MVE long arithmetic shift right.
  82     LSRL, // MVE long shift right.
  83     LSLL, // MVE long shift left.
  84
  85     CMP,      // ARM compare instructions.
  86     CMN,      // ARM CMN instructions.
  87     CMPZ,     // ARM compare that sets only Z flag.
  88     CMPFP,    // ARM VFP compare instruction, sets FPSCR.
  89     CMPFPE,   // ARM VFP signalling compare instruction, sets FPSCR.
  90     CMPFPw0,  // ARM VFP compare against zero instruction, sets FPSCR.
  91     CMPFPEw0, // ARM VFP signalling compare against zero instruction, sets
  92               // FPSCR.
  93     FMSTAT,   // ARM fmstat instruction.
  94
  95     CMOV, // ARM conditional move instructions.
  96     SUBS, // Flag-setting subtraction.
  97
  98     SSAT, // Signed saturation
  99     USAT, // Unsigned saturation
 100
 101     BCC_i64,
 102
 103     SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
 104     SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
 105     RRX,      // V = RRX X, Flag     -> srl X, 1 + shift in carry flag.
 106
 107     ADDC, // Add with carry
 108     ADDE, // Add using carry
 109     SUBC, // Sub with carry
 110     SUBE, // Sub using carry
 111     LSLS, // Shift left producing carry
 112
 113     VMOVRRD, // double to two gprs.
 114     VMOVDRR, // Two gprs to double.
 115     VMOVSR,  // move gpr to single, used for f32 literal constructed in a gpr
 116
 117     EH_SJLJ_SETJMP,         // SjLj exception handling setjmp.
 118     EH_SJLJ_LONGJMP,        // SjLj exception handling longjmp.
 119     EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
 120
 121     TC_RETURN, // Tail call return pseudo.
 122
 123     THREAD_POINTER,
 124
 125     DYN_ALLOC, // Dynamic allocation on the stack.
 126
 127     MEMBARRIER_MCR, // Memory barrier (MCR)
 128
 129     PRELOAD, // Preload
 130
 131     WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
 132     WIN__DBZCHK, // Windows' divide by zero check
 133
 134     WLS, // Low-overhead loops, While Loop Start branch. See t2WhileLoopStart
 135     WLSSETUP, // Setup for the iteration count of a WLS. See t2WhileLoopSetup.
 136     LOOP_DEC, // Really a part of LE, performs the sub
 137     LE,       // Low-overhead loops, Loop End
 138
 139     PREDICATE_CAST,  // Predicate cast for MVE i1 types
 140     VECTOR_REG_CAST, // Reinterpret the current contents of a vector register
 141
 142     MVESEXT,  // Legalization aids for extending a vector into two/four vectors.
 143     MVEZEXT,  //  or truncating two/four vectors into one. Eventually becomes
 144     MVETRUNC, //  stack store/load sequence, if not optimized to anything else.
 145
 146     VCMP,  // Vector compare.
 147     VCMPZ, // Vector compare to zero.
 148     VTST,  // Vector test bits.
 149
 150     // Vector shift by vector
 151     VSHLs, // ...left/right by signed
 152     VSHLu, // ...left/right by unsigned
 153
 154     // Vector shift by immediate:
 155     VSHLIMM,  // ...left
 156     VSHRsIMM, // ...right (signed)
 157     VSHRuIMM, // ...right (unsigned)
 158
 159     // Vector rounding shift by immediate:
 160     VRSHRsIMM, // ...right (signed)
 161     VRSHRuIMM, // ...right (unsigned)
 162     VRSHRNIMM, // ...right narrow
 163
 164     // Vector saturating shift by immediate:
 165     VQSHLsIMM,   // ...left (signed)
 166     VQSHLuIMM,   // ...left (unsigned)
 167     VQSHLsuIMM,  // ...left (signed to unsigned)
 168     VQSHRNsIMM,  // ...right narrow (signed)
 169     VQSHRNuIMM,  // ...right narrow (unsigned)
 170     VQSHRNsuIMM, // ...right narrow (signed to unsigned)
 171
 172     // Vector saturating rounding shift by immediate:
 173     VQRSHRNsIMM,  // ...right narrow (signed)
 174     VQRSHRNuIMM,  // ...right narrow (unsigned)
 175     VQRSHRNsuIMM, // ...right narrow (signed to unsigned)
 176
 177     // Vector shift and insert:
 178     VSLIIMM, // ...left
 179     VSRIIMM, // ...right
 180
 181     // Vector get lane (VMOV scalar to ARM core register)
 182     // (These are used for 8- and 16-bit element types only.)
 183     VGETLANEu, // zero-extend vector extract element
 184     VGETLANEs, // sign-extend vector extract element
 185
 186     // Vector move immediate and move negated immediate:
 187     VMOVIMM,
 188     VMVNIMM,
 189
 190     // Vector move f32 immediate:
 191     VMOVFPIMM,
 192
 193     // Move H <-> R, clearing top 16 bits
 194     VMOVrh,
 195     VMOVhr,
 196
 197     // Vector duplicate:
 198     VDUP,
 199     VDUPLANE,
 200
 201     // Vector shuffles:
 202     VEXT,   // extract
 203     VREV64, // reverse elements within 64-bit doublewords
 204     VREV32, // reverse elements within 32-bit words
 205     VREV16, // reverse elements within 16-bit halfwords
 206     VZIP,   // zip (interleave)
 207     VUZP,   // unzip (deinterleave)
 208     VTRN,   // transpose
 209     VTBL1,  // 1-register shuffle with mask
 210     VTBL2,  // 2-register shuffle with mask
 211     VMOVN,  // MVE vmovn
 212
 213     // MVE Saturating truncates
 214     VQMOVNs, // Vector (V) Saturating (Q) Move and Narrow (N), signed (s)
 215     VQMOVNu, // Vector (V) Saturating (Q) Move and Narrow (N), unsigned (u)
 216
 217     // MVE float <> half converts
 218     VCVTN, // MVE vcvt f32 -> f16, truncating into either the bottom or top
 219            // lanes
 220     VCVTL, // MVE vcvt f16 -> f32, extending from either the bottom or top lanes
 221
 222     // MVE VIDUP instruction, taking a start value and increment.
 223     VIDUP,
 224
 225     // Vector multiply long:
 226     VMULLs, // ...signed
 227     VMULLu, // ...unsigned
 228
 229     VQDMULH, // MVE vqdmulh instruction
 230
 231     // MVE reductions
 232     VADDVs,  // sign- or zero-extend the elements of a vector to i32,
 233     VADDVu,  //   add them all together, and return an i32 of their sum
 234     VADDVps, // Same as VADDV[su] but with a v4i1 predicate mask
 235     VADDVpu,
 236     VADDLVs,  // sign- or zero-extend elements to i64 and sum, returning
 237     VADDLVu,  //   the low and high 32-bit halves of the sum
 238     VADDLVAs, // Same as VADDLV[su] but also add an input accumulator
 239     VADDLVAu, //   provided as low and high halves
 240     VADDLVps, // Same as VADDLV[su] but with a v4i1 predicate mask
 241     VADDLVpu,
 242     VADDLVAps, // Same as VADDLVp[su] but with a v4i1 predicate mask
 243     VADDLVApu,
 244     VMLAVs, // sign- or zero-extend the elements of two vectors to i32, multiply
 245             // them
 246     VMLAVu, //   and add the results together, returning an i32 of their sum
 247     VMLAVps, // Same as VMLAV[su] with a v4i1 predicate mask
 248     VMLAVpu,
 249     VMLALVs,  // Same as VMLAV but with i64, returning the low and
 250     VMLALVu,  //   high 32-bit halves of the sum
 251     VMLALVps, // Same as VMLALV[su] with a v4i1 predicate mask
 252     VMLALVpu,
 253     VMLALVAs,  // Same as VMLALV but also add an input accumulator
 254     VMLALVAu,  //   provided as low and high halves
 255     VMLALVAps, // Same as VMLALVA[su] with a v4i1 predicate mask
 256     VMLALVApu,
 257     VMINVu, // Find minimum unsigned value of a vector and register
 258     VMINVs, // Find minimum signed value of a vector and register
 259     VMAXVu, // Find maximum unsigned value of a vector and register
 260     VMAXVs, // Find maximum signed value of a vector and register
 261
 262     SMULWB,  // Signed multiply word by half word, bottom
 263     SMULWT,  // Signed multiply word by half word, top
 264     UMLAL,   // 64bit Unsigned Accumulate Multiply
 265     SMLAL,   // 64bit Signed Accumulate Multiply
 266     UMAAL,   // 64-bit Unsigned Accumulate Accumulate Multiply
 267     SMLALBB, // 64-bit signed accumulate multiply bottom, bottom 16
 268     SMLALBT, // 64-bit signed accumulate multiply bottom, top 16
 269     SMLALTB, // 64-bit signed accumulate multiply top, bottom 16
 270     SMLALTT, // 64-bit signed accumulate multiply top, top 16
 271     SMLALD,  // Signed multiply accumulate long dual
 272     SMLALDX, // Signed multiply accumulate long dual exchange
 273     SMLSLD,  // Signed multiply subtract long dual
 274     SMLSLDX, // Signed multiply subtract long dual exchange
 275     SMMLAR,  // Signed multiply long, round and add
 276     SMMLSR,  // Signed multiply long, subtract and round
 277
 278     // Single Lane QADD8 and QADD16. Only the bottom lane. That's what the b
 279     // stands for.
 280     QADD8b,
 281     QSUB8b,
 282     QADD16b,
 283     QSUB16b,
 284     UQADD8b,
 285     UQSUB8b,
 286     UQADD16b,
 287     UQSUB16b,
 288
 289     // Operands of the standard BUILD_VECTOR node are not legalized, which
 290     // is fine if BUILD_VECTORs are always lowered to shuffles or other
 291     // operations, but for ARM some BUILD_VECTORs are legal as-is and their
 292     // operands need to be legalized.  Define an ARM-specific version of
 293     // BUILD_VECTOR for this purpose.
 294     BUILD_VECTOR,
 295
 296     // Bit-field insert
 297     BFI,
 298
 299     // Vector OR with immediate
 300     VORRIMM,
 301     // Vector AND with NOT of immediate
 302     VBICIMM,
 303
 304     // Pseudo vector bitwise select
 305     VBSP,
 306
 307     // Pseudo-instruction representing a memory copy using ldm/stm
 308     // instructions.
 309     MEMCPY,
 310
 311     // Pseudo-instruction representing a memory copy using a tail predicated
 312     // loop
 313     MEMCPYLOOP,
 314     // Pseudo-instruction representing a memset using a tail predicated
 315     // loop
 316     MEMSETLOOP,
 317
 318     // V8.1MMainline condition select
 319     CSINV, // Conditional select invert.
 320     CSNEG, // Conditional select negate.
 321     CSINC, // Conditional select increment.
 322
 323     // Vector load N-element structure to all lanes:
 324     VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
 325     VLD2DUP,
 326     VLD3DUP,
 327     VLD4DUP,
 328
 329     // NEON loads with post-increment base updates:
 330     VLD1_UPD,
 331     VLD2_UPD,
 332     VLD3_UPD,
 333     VLD4_UPD,
 334     VLD2LN_UPD,
 335     VLD3LN_UPD,
 336     VLD4LN_UPD,
 337     VLD1DUP_UPD,
 338     VLD2DUP_UPD,
 339     VLD3DUP_UPD,
 340     VLD4DUP_UPD,
 341     VLD1x2_UPD,
 342     VLD1x3_UPD,
 343     VLD1x4_UPD,
 344
 345     // NEON stores with post-increment base updates:
 346     VST1_UPD,
 347     VST2_UPD,
 348     VST3_UPD,
 349     VST4_UPD,
 350     VST2LN_UPD,
 351     VST3LN_UPD,
 352     VST4LN_UPD,
 353     VST1x2_UPD,
 354     VST1x3_UPD,
 355     VST1x4_UPD,
 356
 357     // Load/Store of dual registers
 358     LDRD,
 359     STRD
 360   };
 361
 362   } // end namespace ARMISD
 363
 364   namespace ARM {
 365   /// Possible values of current rounding mode, which is specified in bits
 366   /// 23:22 of FPSCR.
 367   enum Rounding {
 368     RN = 0,    // Round to Nearest
 369     RP = 1,    // Round towards Plus infinity
 370     RM = 2,    // Round towards Minus infinity
 371     RZ = 3,    // Round towards Zero
 372     rmMask = 3 // Bit mask selecting rounding mode
 373   };
 374
 375   // Bit position of rounding mode bits in FPSCR.
 376   const unsigned RoundingBitsPos = 22;
 377   } // namespace ARM
 378
 379   /// Define some predicates that are used for node matching.
 380   namespace ARM {
 381
 382     bool isBitFieldInvertedMask(unsigned v);
 383
 384   } // end namespace ARM
 385
 386   //===--------------------------------------------------------------------===//
 387   //  ARMTargetLowering - ARM Implementation of the TargetLowering interface
 388
 389   class ARMTargetLowering : public TargetLowering {
 390   public:
 391     explicit ARMTargetLowering(const TargetMachine &TM,
 392                                const ARMSubtarget &STI);
 393
 394     unsigned getJumpTableEncoding() const override;
 395     bool useSoftFloat() const override;
 396
 397     SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 398
 399     /// ReplaceNodeResults - Replace the results of node with an illegal result
 400     /// type with new values built out of custom code.
 401     void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
 402                             SelectionDAG &DAG) const override;
 403
 404     const char *getTargetNodeName(unsigned Opcode) const override;
 405
 406     bool isSelectSupported(SelectSupportKind Kind) const override {
 407       // ARM does not support scalar condition selects on vectors.
 408       return (Kind != ScalarCondVectorVal);
 409     }
 410
 411     bool isReadOnly(const GlobalValue *GV) const;
 412
 413     /// getSetCCResultType - Return the value type to use for ISD::SETCC.
 414     EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
 415                            EVT VT) const override;
 416
 417     MachineBasicBlock *
 418     EmitInstrWithCustomInserter(MachineInstr &MI,
 419                                 MachineBasicBlock *MBB) const override;
 420
 421     void AdjustInstrPostInstrSelection(MachineInstr &MI,
 422                                        SDNode *Node) const override;
 423
 424     SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
 425     SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
 426     SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
 427     SDValue PerformIntrinsicCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 428     SDValue PerformMVEExtCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 429     SDValue PerformMVETruncCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 430     SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
 431
 432     bool SimplifyDemandedBitsForTargetNode(SDValue Op,
 433                                            const APInt &OriginalDemandedBits,
 434                                            const APInt &OriginalDemandedElts,
 435                                            KnownBits &Known,
 436                                            TargetLoweringOpt &TLO,
 437                                            unsigned Depth) const override;
 438
 439     bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
 440
 441     /// allowsMisalignedMemoryAccesses - Returns true if the target allows
 442     /// unaligned memory accesses of the specified type. Returns whether it
 443     /// is "fast" by reference in the second argument.
 444     bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
 445                                         Align Alignment,
 446                                         MachineMemOperand::Flags Flags,
 447                                         bool *Fast) const override;
 448
 449     EVT getOptimalMemOpType(const MemOp &Op,
 450                             const AttributeList &FuncAttributes) const override;
 451
 452     bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
 453     bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
 454     bool isZExtFree(SDValue Val, EVT VT2) const override;
 455     bool shouldSinkOperands(Instruction *I,
 456                             SmallVectorImpl<Use *> &Ops) const override;
 457     Type* shouldConvertSplatType(ShuffleVectorInst* SVI) const override;
 458
 459     bool isFNegFree(EVT VT) const override;
 460
 461     bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
 462
 463     bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
 464
 465
 466     /// isLegalAddressingMode - Return true if the addressing mode represented
 467     /// by AM is legal for this target, for a load/store of the specified type.
 468     bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
 469                                Type *Ty, unsigned AS,
 470                                Instruction *I = nullptr) const override;
 471
 472     /// getScalingFactorCost - Return the cost of the scaling used in
 473     /// addressing mode represented by AM.
 474     /// If the AM is supported, the return value must be >= 0.
 475     /// If the AM is not supported, the return value must be negative.
 476     InstructionCost getScalingFactorCost(const DataLayout &DL,
 477                                          const AddrMode &AM, Type *Ty,
 478                                          unsigned AS) const override;
 479
 480     bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
 481
 482     /// Returns true if the addressing mode representing by AM is legal
 483     /// for the Thumb1 target, for a load/store of the specified type.
 484     bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
 485
 486     /// isLegalICmpImmediate - Return true if the specified immediate is legal
 487     /// icmp immediate, that is the target has icmp instructions which can
 488     /// compare a register against the immediate without having to materialize
 489     /// the immediate into a register.
 490     bool isLegalICmpImmediate(int64_t Imm) const override;
 491
 492     /// isLegalAddImmediate - Return true if the specified immediate is legal
 493     /// add immediate, that is the target has add instructions which can
 494     /// add a register and the immediate without having to materialize
 495     /// the immediate into a register.
 496     bool isLegalAddImmediate(int64_t Imm) const override;
 497
 498     /// getPreIndexedAddressParts - returns true by value, base pointer and
 499     /// offset pointer and addressing mode by reference if the node's address
 500     /// can be legally represented as pre-indexed load / store address.
 501     bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
 502                                    ISD::MemIndexedMode &AM,
 503                                    SelectionDAG &DAG) const override;
 504
 505     /// getPostIndexedAddressParts - returns true by value, base pointer and
 506     /// offset pointer and addressing mode by reference if this node can be
 507     /// combined with a load / store to form a post-indexed load / store.
 508     bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
 509                                     SDValue &Offset, ISD::MemIndexedMode &AM,
 510                                     SelectionDAG &DAG) const override;
 511
 512     void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
 513                                        const APInt &DemandedElts,
 514                                        const SelectionDAG &DAG,
 515                                        unsigned Depth) const override;
 516
 517     bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits,
 518                                       const APInt &DemandedElts,
 519                                       TargetLoweringOpt &TLO) const override;
 520
 521     bool ExpandInlineAsm(CallInst *CI) const override;
 522
 523     ConstraintType getConstraintType(StringRef Constraint) const override;
 524
 525     /// Examine constraint string and operand type and determine a weight value.
 526     /// The operand object must already have been set up with the operand type.
 527     ConstraintWeight getSingleConstraintMatchWeight(
 528       AsmOperandInfo &info, const char *constraint) const override;
 529
 530     std::pair<unsigned, const TargetRegisterClass *>
 531     getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
 532                                  StringRef Constraint, MVT VT) const override;
 533
 534     const char *LowerXConstraint(EVT ConstraintVT) const override;
 535
 536     /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
 537     /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
 538     /// true it means one of the asm constraint of the inline asm instruction
 539     /// being processed is 'm'.
 540     void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
 541                                       std::vector<SDValue> &Ops,
 542                                       SelectionDAG &DAG) const override;
 543
 544     unsigned
 545     getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
 546       if (ConstraintCode == "Q")
 547         return InlineAsm::Constraint_Q;
 548       else if (ConstraintCode.size() == 2) {
 549         if (ConstraintCode[0] == 'U') {
 550           switch(ConstraintCode[1]) {
 551           default:
 552             break;
 553           case 'm':
 554             return InlineAsm::Constraint_Um;
 555           case 'n':
 556             return InlineAsm::Constraint_Un;
 557           case 'q':
 558             return InlineAsm::Constraint_Uq;
 559           case 's':
 560             return InlineAsm::Constraint_Us;
 561           case 't':
 562             return InlineAsm::Constraint_Ut;
 563           case 'v':
 564             return InlineAsm::Constraint_Uv;
 565           case 'y':
 566             return InlineAsm::Constraint_Uy;
 567           }
 568         }
 569       }
 570       return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
 571     }
 572
 573     const ARMSubtarget* getSubtarget() const {
 574       return Subtarget;
 575     }
 576
 577     /// getRegClassFor - Return the register class that should be used for the
 578     /// specified value type.
 579     const TargetRegisterClass *
 580     getRegClassFor(MVT VT, bool isDivergent = false) const override;
 581
 582     bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
 583                                 unsigned &PrefAlign) const override;
 584
 585     /// createFastISel - This method returns a target specific FastISel object,
 586     /// or null if the target does not support "fast" ISel.
 587     FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
 588                              const TargetLibraryInfo *libInfo) const override;
 589
 590     Sched::Preference getSchedulingPreference(SDNode *N) const override;
 591
 592     bool preferZeroCompareBranch() const override { return true; }
 593
 594     bool
 595     isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
 596     bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
 597
 598     /// isFPImmLegal - Returns true if the target can instruction select the
 599     /// specified FP immediate natively. If false, the legalizer will
 600     /// materialize the FP immediate as a load from a constant pool.
 601     bool isFPImmLegal(const APFloat &Imm, EVT VT,
 602                       bool ForCodeSize = false) const override;
 603
 604     bool getTgtMemIntrinsic(IntrinsicInfo &Info,
 605                             const CallInst &I,
 606                             MachineFunction &MF,
 607                             unsigned Intrinsic) const override;
 608
 609     /// Returns true if it is beneficial to convert a load of a constant
 610     /// to just the constant itself.
 611     bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
 612                                            Type *Ty) const override;
 613
 614     /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
 615     /// with this index.
 616     bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
 617                                  unsigned Index) const override;
 618
 619     bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
 620                               bool MathUsed) const override {
 621       // Using overflow ops for overflow checks only should beneficial on ARM.
 622       return TargetLowering::shouldFormOverflowOp(Opcode, VT, true);
 623     }
 624
 625     /// Returns true if an argument of type Ty needs to be passed in a
 626     /// contiguous block of registers in calling convention CallConv.
 627     bool functionArgumentNeedsConsecutiveRegisters(
 628         Type *Ty, CallingConv::ID CallConv, bool isVarArg,
 629         const DataLayout &DL) const override;
 630
 631     /// If a physical register, this returns the register that receives the
 632     /// exception address on entry to an EH pad.
 633     Register
 634     getExceptionPointerRegister(const Constant *PersonalityFn) const override;
 635
 636     /// If a physical register, this returns the register that receives the
 637     /// exception typeid on entry to a landing pad.
 638     Register
 639     getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
 640
 641     Instruction *makeDMB(IRBuilderBase &Builder, ARM_MB::MemBOpt Domain) const;
 642     Value *emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr,
 643                           AtomicOrdering Ord) const override;
 644     Value *emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr,
 645                                 AtomicOrdering Ord) const override;
 646
 647     void
 648     emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override;
 649
 650     Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst,
 651                                   AtomicOrdering Ord) const override;
 652     Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst,
 653                                    AtomicOrdering Ord) const override;
 654
 655     unsigned getMaxSupportedInterleaveFactor() const override;
 656
 657     bool lowerInterleavedLoad(LoadInst *LI,
 658                               ArrayRef<ShuffleVectorInst *> Shuffles,
 659                               ArrayRef<unsigned> Indices,
 660                               unsigned Factor) const override;
 661     bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
 662                                unsigned Factor) const override;
 663
 664     bool shouldInsertFencesForAtomic(const Instruction *I) const override;
 665     TargetLoweringBase::AtomicExpansionKind
 666     shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
 667     bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
 668     TargetLoweringBase::AtomicExpansionKind
 669     shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
 670     TargetLoweringBase::AtomicExpansionKind
 671     shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
 672
 673     bool useLoadStackGuardNode() const override;
 674
 675     void insertSSPDeclarations(Module &M) const override;
 676     Value *getSDagStackGuard(const Module &M) const override;
 677     Function *getSSPStackGuardCheck(const Module &M) const override;
 678
 679     bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
 680                                    unsigned &Cost) const override;
 681
 682     bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
 683                           const MachineFunction &MF) const override {
 684       // Do not merge to larger than i32.
 685       return (MemVT.getSizeInBits() <= 32);
 686     }
 687
 688     bool isCheapToSpeculateCttz() const override;
 689     bool isCheapToSpeculateCtlz() const override;
 690
 691     bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
 692       return VT.isScalarInteger();
 693     }
 694
 695     bool supportSwiftError() const override {
 696       return true;
 697     }
 698
 699     bool hasStandaloneRem(EVT VT) const override {
 700       return HasStandaloneRem;
 701     }
 702
 703     bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override;
 704
 705     CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const;
 706     CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const;
 707
 708     /// Returns true if \p VecTy is a legal interleaved access type. This
 709     /// function checks the vector element type and the overall width of the
 710     /// vector.
 711     bool isLegalInterleavedAccessType(unsigned Factor, FixedVectorType *VecTy,
 712                                       Align Alignment,
 713                                       const DataLayout &DL) const;
 714
 715     bool isMulAddWithConstProfitable(const SDValue &AddNode,
 716                                      const SDValue &ConstNode) const override;
 717
 718     bool alignLoopsWithOptSize() const override;
 719
 720     /// Returns the number of interleaved accesses that will be generated when
 721     /// lowering accesses of the given type.
 722     unsigned getNumInterleavedAccesses(VectorType *VecTy,
 723                                        const DataLayout &DL) const;
 724
 725     void finalizeLowering(MachineFunction &MF) const override;
 726
 727     /// Return the correct alignment for the current calling convention.
 728     Align getABIAlignmentForCallingConv(Type *ArgTy,
 729                                         const DataLayout &DL) const override;
 730
 731     bool isDesirableToCommuteWithShift(const SDNode *N,
 732                                        CombineLevel Level) const override;
 733
 734     bool shouldFoldConstantShiftPairToMask(const SDNode *N,
 735                                            CombineLevel Level) const override;
 736
 737     bool preferIncOfAddToSubOfNot(EVT VT) const override;
 738
 739   protected:
 740     std::pair<const TargetRegisterClass *, uint8_t>
 741     findRepresentativeClass(const TargetRegisterInfo *TRI,
 742                             MVT VT) const override;
 743
 744   private:
 745     /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
 746     /// make the right decision when generating code for different targets.
 747     const ARMSubtarget *Subtarget;
 748
 749     const TargetRegisterInfo *RegInfo;
 750
 751     const InstrItineraryData *Itins;
 752
 753     /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
 754     unsigned ARMPCLabelIndex;
 755
 756     // TODO: remove this, and have shouldInsertFencesForAtomic do the proper
 757     // check.
 758     bool InsertFencesForAtomic;
 759
 760     bool HasStandaloneRem = true;
 761
 762     void addTypeForNEON(MVT VT, MVT PromotedLdStVT);
 763     void addDRTypeForNEON(MVT VT);
 764     void addQRTypeForNEON(MVT VT);
 765     std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
 766
 767     using RegsToPassVector = SmallVector<std::pair<unsigned, SDValue>, 8>;
 768
 769     void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
 770                           SDValue &Arg, RegsToPassVector &RegsToPass,
 771                           CCValAssign &VA, CCValAssign &NextVA,
 772                           SDValue &StackPtr,
 773                           SmallVectorImpl<SDValue> &MemOpChains,
 774                           bool IsTailCall,
 775                           int SPDiff) const;
 776     SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
 777                                  SDValue &Root, SelectionDAG &DAG,
 778                                  const SDLoc &dl) const;
 779
 780     CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
 781                                             bool isVarArg) const;
 782     CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
 783                                   bool isVarArg) const;
 784     std::pair<SDValue, MachinePointerInfo>
 785     computeAddrForCallArg(const SDLoc &dl, SelectionDAG &DAG,
 786                           const CCValAssign &VA, SDValue StackPtr,
 787                           bool IsTailCall, int SPDiff) const;
 788     SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
 789     SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
 790     SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
 791     SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG,
 792                                     const ARMSubtarget *Subtarget) const;
 793     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
 794                                     const ARMSubtarget *Subtarget) const;
 795     SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
 796     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
 797     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
 798     SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
 799     SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
 800     SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
 801     SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
 802     SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
 803                                             SelectionDAG &DAG) const;
 804     SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
 805                                  SelectionDAG &DAG,
 806                                  TLSModel::Model model) const;
 807     SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
 808     SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
 809     SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
 810     SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
 811     SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const;
 812     SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const;
 813     SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
 814     SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
 815     SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
 816     SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
 817     SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
 818     SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
 819     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
 820     SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
 821     SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
 822     SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
 823     SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
 824     SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
 825                             const ARMSubtarget *ST) const;
 826     SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
 827                               const ARMSubtarget *ST) const;
 828     SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
 829     SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
 830     SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
 831     SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
 832     void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
 833                            SmallVectorImpl<SDValue> &Results) const;
 834     SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG,
 835                           const ARMSubtarget *Subtarget) const;
 836     SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
 837                                    SDValue &Chain) const;
 838     SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
 839     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
 840     SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
 841     SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
 842     SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
 843     SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
 844     SDValue LowerFSETCC(SDValue Op, SelectionDAG &DAG) const;
 845     void lowerABS(SDNode *N, SmallVectorImpl<SDValue> &Results,
 846                   SelectionDAG &DAG) const;
 847     void LowerLOAD(SDNode *N, SmallVectorImpl<SDValue> &Results,
 848                    SelectionDAG &DAG) const;
 849
 850     Register getRegisterByName(const char* RegName, LLT VT,
 851                                const MachineFunction &MF) const override;
 852
 853     SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
 854                           SmallVectorImpl<SDNode *> &Created) const override;
 855
 856     bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
 857                                     EVT VT) const override;
 858
 859     SDValue MoveToHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT, MVT ValVT,
 860                       SDValue Val) const;
 861     SDValue MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT,
 862                         MVT ValVT, SDValue Val) const;
 863
 864     SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
 865
 866     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
 867                             CallingConv::ID CallConv, bool isVarArg,
 868                             const SmallVectorImpl<ISD::InputArg> &Ins,
 869                             const SDLoc &dl, SelectionDAG &DAG,
 870                             SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
 871                             SDValue ThisVal) const;
 872
 873     bool supportSplitCSR(MachineFunction *MF) const override {
 874       return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
 875           MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
 876     }
 877
 878     void initializeSplitCSR(MachineBasicBlock *Entry) const override;
 879     void insertCopiesSplitCSR(
 880       MachineBasicBlock *Entry,
 881       const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
 882
 883     bool
 884     splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val,
 885                                 SDValue *Parts, unsigned NumParts, MVT PartVT,
 886                                 Optional<CallingConv::ID> CC) const override;
 887
 888     SDValue
 889     joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL,
 890                                const SDValue *Parts, unsigned NumParts,
 891                                MVT PartVT, EVT ValueVT,
 892                                Optional<CallingConv::ID> CC) const override;
 893
 894     SDValue
 895     LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
 896                          const SmallVectorImpl<ISD::InputArg> &Ins,
 897                          const SDLoc &dl, SelectionDAG &DAG,
 898                          SmallVectorImpl<SDValue> &InVals) const override;
 899
 900     int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
 901                        SDValue &Chain, const Value *OrigArg,
 902                        unsigned InRegsParamRecordIdx, int ArgOffset,
 903                        unsigned ArgSize) const;
 904
 905     void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
 906                               const SDLoc &dl, SDValue &Chain,
 907                               unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
 908                               bool ForceMutable = false) const;
 909
 910     SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
 911                       SmallVectorImpl<SDValue> &InVals) const override;
 912
 913     /// HandleByVal - Target-specific cleanup for ByVal support.
 914     void HandleByVal(CCState *, unsigned &, Align) const override;
 915
 916     /// IsEligibleForTailCallOptimization - Check whether the call is eligible
 917     /// for tail call optimization. Targets which want to do tail call
 918     /// optimization should implement this function.
 919     bool IsEligibleForTailCallOptimization(
 920         SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
 921         bool isCalleeStructRet, bool isCallerStructRet,
 922         const SmallVectorImpl<ISD::OutputArg> &Outs,
 923         const SmallVectorImpl<SDValue> &OutVals,
 924         const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG,
 925         const bool isIndirect) const;
 926
 927     bool CanLowerReturn(CallingConv::ID CallConv,
 928                         MachineFunction &MF, bool isVarArg,
 929                         const SmallVectorImpl<ISD::OutputArg> &Outs,
 930                         LLVMContext &Context) const override;
 931
 932     SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
 933                         const SmallVectorImpl<ISD::OutputArg> &Outs,
 934                         const SmallVectorImpl<SDValue> &OutVals,
 935                         const SDLoc &dl, SelectionDAG &DAG) const override;
 936
 937     bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
 938
 939     bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
 940
 941     bool shouldConsiderGEPOffsetSplit() const override { return true; }
 942
 943     bool isUnsupportedFloatingType(EVT VT) const;
 944
 945     SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
 946                     SDValue ARMcc, SDValue CCR, SDValue Cmp,
 947                     SelectionDAG &DAG) const;
 948     SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
 949                       SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
 950     SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
 951                       const SDLoc &dl, bool Signaling = false) const;
 952     SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
 953
 954     SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
 955
 956     void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
 957                                 MachineBasicBlock *DispatchBB, int FI) const;
 958
 959     void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const;
 960
 961     bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const;
 962
 963     MachineBasicBlock *EmitStructByval(MachineInstr &MI,
 964                                        MachineBasicBlock *MBB) const;
 965
 966     MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,
 967                                            MachineBasicBlock *MBB) const;
 968     MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,
 969                                            MachineBasicBlock *MBB) const;
 970     void addMVEVectorTypes(bool HasMVEFP);
 971     void addAllExtLoads(const MVT From, const MVT To, LegalizeAction Action);
 972     void setAllExpand(MVT VT);
 973   };
 974
 975   enum VMOVModImmType {
 976     VMOVModImm,
 977     VMVNModImm,
 978     MVEVMVNModImm,
 979     OtherModImm
 980   };
 981
 982   namespace ARM {
 983
 984     FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
 985                              const TargetLibraryInfo *libInfo);
 986
 987   } // end namespace ARM
 988
 989 } // end namespace llvm
 990
 991 #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H