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[sanitizer] Improve FreeBSD ASLR detection
[llvm-project.git] / libunwind / include / libunwind.h
blob9a74faa48d6ffc0d72a8c7cb41d50c6e50d317fe
1 //===----------------------------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //
8 // Compatible with libunwind API documented at:
9 // http://www.nongnu.org/libunwind/man/libunwind(3).html
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef __LIBUNWIND__
14 #define __LIBUNWIND__
15
16 #include <__libunwind_config.h>
17
18 #include <stdint.h>
19 #include <stddef.h>
20
21 #ifdef __APPLE__
22 #if __clang__
23 #if __has_include(<Availability.h>)
24 #include <Availability.h>
25 #endif
26 #elif __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ >= 1050
27 #include <Availability.h>
28 #endif
29
30 #ifdef __arm__
31 #define LIBUNWIND_AVAIL __attribute__((unavailable))
32 #elif defined(__OSX_AVAILABLE_STARTING)
33 #define LIBUNWIND_AVAIL __OSX_AVAILABLE_STARTING(__MAC_10_6, __IPHONE_5_0)
34 #else
35 #include <AvailabilityMacros.h>
36 #ifdef AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER
37 #define LIBUNWIND_AVAIL AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER
38 #else
39 #define LIBUNWIND_AVAIL __attribute__((unavailable))
40 #endif
41 #endif
42 #else
43 #define LIBUNWIND_AVAIL
44 #endif
45
46 #if defined(_WIN32) && defined(__SEH__)
47 #define LIBUNWIND_CURSOR_ALIGNMENT_ATTR __attribute__((__aligned__(16)))
48 #else
49 #define LIBUNWIND_CURSOR_ALIGNMENT_ATTR
50 #endif
51
52 /* error codes */
53 enum {
54 UNW_ESUCCESS = 0, /* no error */
55 UNW_EUNSPEC = -6540, /* unspecified (general) error */
56 UNW_ENOMEM = -6541, /* out of memory */
57 UNW_EBADREG = -6542, /* bad register number */
58 UNW_EREADONLYREG = -6543, /* attempt to write read-only register */
59 UNW_ESTOPUNWIND = -6544, /* stop unwinding */
60 UNW_EINVALIDIP = -6545, /* invalid IP */
61 UNW_EBADFRAME = -6546, /* bad frame */
62 UNW_EINVAL = -6547, /* unsupported operation or bad value */
63 UNW_EBADVERSION = -6548, /* unwind info has unsupported version */
64 UNW_ENOINFO = -6549 /* no unwind info found */
65 #if defined(_LIBUNWIND_TARGET_AARCH64) && !defined(_LIBUNWIND_IS_NATIVE_ONLY)
66 , UNW_ECROSSRASIGNING = -6550 /* cross unwind with return address signing */
67 #endif
68 };
69
70 struct unw_context_t {
71 uint64_t data[_LIBUNWIND_CONTEXT_SIZE];
72 };
73 typedef struct unw_context_t unw_context_t;
74
75 struct unw_cursor_t {
76 uint64_t data[_LIBUNWIND_CURSOR_SIZE];
77 } LIBUNWIND_CURSOR_ALIGNMENT_ATTR;
78 typedef struct unw_cursor_t unw_cursor_t;
79
80 typedef struct unw_addr_space *unw_addr_space_t;
81
82 typedef int unw_regnum_t;
83 typedef uintptr_t unw_word_t;
84 #if defined(__arm__) && !defined(__ARM_DWARF_EH__)
85 typedef uint64_t unw_fpreg_t;
86 #else
87 typedef double unw_fpreg_t;
88 #endif
89
90 struct unw_proc_info_t {
91 unw_word_t start_ip; /* start address of function */
92 unw_word_t end_ip; /* address after end of function */
93 unw_word_t lsda; /* address of language specific data area, */
94 /* or zero if not used */
95 unw_word_t handler; /* personality routine, or zero if not used */
96 unw_word_t gp; /* not used */
97 unw_word_t flags; /* not used */
98 uint32_t format; /* compact unwind encoding, or zero if none */
99 uint32_t unwind_info_size; /* size of DWARF unwind info, or zero if none */
100 unw_word_t unwind_info; /* address of DWARF unwind info, or zero */
101 unw_word_t extra; /* mach_header of mach-o image containing func */
102 };
103 typedef struct unw_proc_info_t unw_proc_info_t;
104
105 #ifdef __cplusplus
106 extern "C" {
107 #endif
108
109 extern int unw_getcontext(unw_context_t *) LIBUNWIND_AVAIL;
110 extern int unw_init_local(unw_cursor_t *, unw_context_t *) LIBUNWIND_AVAIL;
111 extern int unw_step(unw_cursor_t *) LIBUNWIND_AVAIL;
112 extern int unw_get_reg(unw_cursor_t *, unw_regnum_t, unw_word_t *) LIBUNWIND_AVAIL;
113 extern int unw_get_fpreg(unw_cursor_t *, unw_regnum_t, unw_fpreg_t *) LIBUNWIND_AVAIL;
114 extern int unw_set_reg(unw_cursor_t *, unw_regnum_t, unw_word_t) LIBUNWIND_AVAIL;
115 extern int unw_set_fpreg(unw_cursor_t *, unw_regnum_t, unw_fpreg_t) LIBUNWIND_AVAIL;
116 extern int unw_resume(unw_cursor_t *) LIBUNWIND_AVAIL;
117
118 #ifdef __arm__
119 /* Save VFP registers in FSTMX format (instead of FSTMD). */
120 extern void unw_save_vfp_as_X(unw_cursor_t *) LIBUNWIND_AVAIL;
121 #endif
122
123
124 extern const char *unw_regname(unw_cursor_t *, unw_regnum_t) LIBUNWIND_AVAIL;
125 extern int unw_get_proc_info(unw_cursor_t *, unw_proc_info_t *) LIBUNWIND_AVAIL;
126 extern int unw_is_fpreg(unw_cursor_t *, unw_regnum_t) LIBUNWIND_AVAIL;
127 extern int unw_is_signal_frame(unw_cursor_t *) LIBUNWIND_AVAIL;
128 extern int unw_get_proc_name(unw_cursor_t *, char *, size_t, unw_word_t *) LIBUNWIND_AVAIL;
129 //extern int unw_get_save_loc(unw_cursor_t*, int, unw_save_loc_t*);
130
131 extern unw_addr_space_t unw_local_addr_space;
132
133 #ifdef __cplusplus
134 }
135 #endif
136
137 // architecture independent register numbers
138 enum {
139 UNW_REG_IP = -1, // instruction pointer
140 UNW_REG_SP = -2, // stack pointer
141 };
142
143 // 32-bit x86 registers
144 enum {
145 UNW_X86_EAX = 0,
146 UNW_X86_ECX = 1,
147 UNW_X86_EDX = 2,
148 UNW_X86_EBX = 3,
149 UNW_X86_EBP = 4,
150 UNW_X86_ESP = 5,
151 UNW_X86_ESI = 6,
152 UNW_X86_EDI = 7
153 };
154
155 // 64-bit x86_64 registers
156 enum {
157 UNW_X86_64_RAX = 0,
158 UNW_X86_64_RDX = 1,
159 UNW_X86_64_RCX = 2,
160 UNW_X86_64_RBX = 3,
161 UNW_X86_64_RSI = 4,
162 UNW_X86_64_RDI = 5,
163 UNW_X86_64_RBP = 6,
164 UNW_X86_64_RSP = 7,
165 UNW_X86_64_R8 = 8,
166 UNW_X86_64_R9 = 9,
167 UNW_X86_64_R10 = 10,
168 UNW_X86_64_R11 = 11,
169 UNW_X86_64_R12 = 12,
170 UNW_X86_64_R13 = 13,
171 UNW_X86_64_R14 = 14,
172 UNW_X86_64_R15 = 15,
173 UNW_X86_64_RIP = 16,
174 UNW_X86_64_XMM0 = 17,
175 UNW_X86_64_XMM1 = 18,
176 UNW_X86_64_XMM2 = 19,
177 UNW_X86_64_XMM3 = 20,
178 UNW_X86_64_XMM4 = 21,
179 UNW_X86_64_XMM5 = 22,
180 UNW_X86_64_XMM6 = 23,
181 UNW_X86_64_XMM7 = 24,
182 UNW_X86_64_XMM8 = 25,
183 UNW_X86_64_XMM9 = 26,
184 UNW_X86_64_XMM10 = 27,
185 UNW_X86_64_XMM11 = 28,
186 UNW_X86_64_XMM12 = 29,
187 UNW_X86_64_XMM13 = 30,
188 UNW_X86_64_XMM14 = 31,
189 UNW_X86_64_XMM15 = 32,
190 };
191
192
193 // 32-bit ppc register numbers
194 enum {
195 UNW_PPC_R0 = 0,
196 UNW_PPC_R1 = 1,
197 UNW_PPC_R2 = 2,
198 UNW_PPC_R3 = 3,
199 UNW_PPC_R4 = 4,
200 UNW_PPC_R5 = 5,
201 UNW_PPC_R6 = 6,
202 UNW_PPC_R7 = 7,
203 UNW_PPC_R8 = 8,
204 UNW_PPC_R9 = 9,
205 UNW_PPC_R10 = 10,
206 UNW_PPC_R11 = 11,
207 UNW_PPC_R12 = 12,
208 UNW_PPC_R13 = 13,
209 UNW_PPC_R14 = 14,
210 UNW_PPC_R15 = 15,
211 UNW_PPC_R16 = 16,
212 UNW_PPC_R17 = 17,
213 UNW_PPC_R18 = 18,
214 UNW_PPC_R19 = 19,
215 UNW_PPC_R20 = 20,
216 UNW_PPC_R21 = 21,
217 UNW_PPC_R22 = 22,
218 UNW_PPC_R23 = 23,
219 UNW_PPC_R24 = 24,
220 UNW_PPC_R25 = 25,
221 UNW_PPC_R26 = 26,
222 UNW_PPC_R27 = 27,
223 UNW_PPC_R28 = 28,
224 UNW_PPC_R29 = 29,
225 UNW_PPC_R30 = 30,
226 UNW_PPC_R31 = 31,
227 UNW_PPC_F0 = 32,
228 UNW_PPC_F1 = 33,
229 UNW_PPC_F2 = 34,
230 UNW_PPC_F3 = 35,
231 UNW_PPC_F4 = 36,
232 UNW_PPC_F5 = 37,
233 UNW_PPC_F6 = 38,
234 UNW_PPC_F7 = 39,
235 UNW_PPC_F8 = 40,
236 UNW_PPC_F9 = 41,
237 UNW_PPC_F10 = 42,
238 UNW_PPC_F11 = 43,
239 UNW_PPC_F12 = 44,
240 UNW_PPC_F13 = 45,
241 UNW_PPC_F14 = 46,
242 UNW_PPC_F15 = 47,
243 UNW_PPC_F16 = 48,
244 UNW_PPC_F17 = 49,
245 UNW_PPC_F18 = 50,
246 UNW_PPC_F19 = 51,
247 UNW_PPC_F20 = 52,
248 UNW_PPC_F21 = 53,
249 UNW_PPC_F22 = 54,
250 UNW_PPC_F23 = 55,
251 UNW_PPC_F24 = 56,
252 UNW_PPC_F25 = 57,
253 UNW_PPC_F26 = 58,
254 UNW_PPC_F27 = 59,
255 UNW_PPC_F28 = 60,
256 UNW_PPC_F29 = 61,
257 UNW_PPC_F30 = 62,
258 UNW_PPC_F31 = 63,
259 UNW_PPC_MQ = 64,
260 UNW_PPC_LR = 65,
261 UNW_PPC_CTR = 66,
262 UNW_PPC_AP = 67,
263 UNW_PPC_CR0 = 68,
264 UNW_PPC_CR1 = 69,
265 UNW_PPC_CR2 = 70,
266 UNW_PPC_CR3 = 71,
267 UNW_PPC_CR4 = 72,
268 UNW_PPC_CR5 = 73,
269 UNW_PPC_CR6 = 74,
270 UNW_PPC_CR7 = 75,
271 UNW_PPC_XER = 76,
272 UNW_PPC_V0 = 77,
273 UNW_PPC_V1 = 78,
274 UNW_PPC_V2 = 79,
275 UNW_PPC_V3 = 80,
276 UNW_PPC_V4 = 81,
277 UNW_PPC_V5 = 82,
278 UNW_PPC_V6 = 83,
279 UNW_PPC_V7 = 84,
280 UNW_PPC_V8 = 85,
281 UNW_PPC_V9 = 86,
282 UNW_PPC_V10 = 87,
283 UNW_PPC_V11 = 88,
284 UNW_PPC_V12 = 89,
285 UNW_PPC_V13 = 90,
286 UNW_PPC_V14 = 91,
287 UNW_PPC_V15 = 92,
288 UNW_PPC_V16 = 93,
289 UNW_PPC_V17 = 94,
290 UNW_PPC_V18 = 95,
291 UNW_PPC_V19 = 96,
292 UNW_PPC_V20 = 97,
293 UNW_PPC_V21 = 98,
294 UNW_PPC_V22 = 99,
295 UNW_PPC_V23 = 100,
296 UNW_PPC_V24 = 101,
297 UNW_PPC_V25 = 102,
298 UNW_PPC_V26 = 103,
299 UNW_PPC_V27 = 104,
300 UNW_PPC_V28 = 105,
301 UNW_PPC_V29 = 106,
302 UNW_PPC_V30 = 107,
303 UNW_PPC_V31 = 108,
304 UNW_PPC_VRSAVE = 109,
305 UNW_PPC_VSCR = 110,
306 UNW_PPC_SPE_ACC = 111,
307 UNW_PPC_SPEFSCR = 112
308 };
309
310 // 64-bit ppc register numbers
311 enum {
312 UNW_PPC64_R0 = 0,
313 UNW_PPC64_R1 = 1,
314 UNW_PPC64_R2 = 2,
315 UNW_PPC64_R3 = 3,
316 UNW_PPC64_R4 = 4,
317 UNW_PPC64_R5 = 5,
318 UNW_PPC64_R6 = 6,
319 UNW_PPC64_R7 = 7,
320 UNW_PPC64_R8 = 8,
321 UNW_PPC64_R9 = 9,
322 UNW_PPC64_R10 = 10,
323 UNW_PPC64_R11 = 11,
324 UNW_PPC64_R12 = 12,
325 UNW_PPC64_R13 = 13,
326 UNW_PPC64_R14 = 14,
327 UNW_PPC64_R15 = 15,
328 UNW_PPC64_R16 = 16,
329 UNW_PPC64_R17 = 17,
330 UNW_PPC64_R18 = 18,
331 UNW_PPC64_R19 = 19,
332 UNW_PPC64_R20 = 20,
333 UNW_PPC64_R21 = 21,
334 UNW_PPC64_R22 = 22,
335 UNW_PPC64_R23 = 23,
336 UNW_PPC64_R24 = 24,
337 UNW_PPC64_R25 = 25,
338 UNW_PPC64_R26 = 26,
339 UNW_PPC64_R27 = 27,
340 UNW_PPC64_R28 = 28,
341 UNW_PPC64_R29 = 29,
342 UNW_PPC64_R30 = 30,
343 UNW_PPC64_R31 = 31,
344 UNW_PPC64_F0 = 32,
345 UNW_PPC64_F1 = 33,
346 UNW_PPC64_F2 = 34,
347 UNW_PPC64_F3 = 35,
348 UNW_PPC64_F4 = 36,
349 UNW_PPC64_F5 = 37,
350 UNW_PPC64_F6 = 38,
351 UNW_PPC64_F7 = 39,
352 UNW_PPC64_F8 = 40,
353 UNW_PPC64_F9 = 41,
354 UNW_PPC64_F10 = 42,
355 UNW_PPC64_F11 = 43,
356 UNW_PPC64_F12 = 44,
357 UNW_PPC64_F13 = 45,
358 UNW_PPC64_F14 = 46,
359 UNW_PPC64_F15 = 47,
360 UNW_PPC64_F16 = 48,
361 UNW_PPC64_F17 = 49,
362 UNW_PPC64_F18 = 50,
363 UNW_PPC64_F19 = 51,
364 UNW_PPC64_F20 = 52,
365 UNW_PPC64_F21 = 53,
366 UNW_PPC64_F22 = 54,
367 UNW_PPC64_F23 = 55,
368 UNW_PPC64_F24 = 56,
369 UNW_PPC64_F25 = 57,
370 UNW_PPC64_F26 = 58,
371 UNW_PPC64_F27 = 59,
372 UNW_PPC64_F28 = 60,
373 UNW_PPC64_F29 = 61,
374 UNW_PPC64_F30 = 62,
375 UNW_PPC64_F31 = 63,
376 // 64: reserved
377 UNW_PPC64_LR = 65,
378 UNW_PPC64_CTR = 66,
379 // 67: reserved
380 UNW_PPC64_CR0 = 68,
381 UNW_PPC64_CR1 = 69,
382 UNW_PPC64_CR2 = 70,
383 UNW_PPC64_CR3 = 71,
384 UNW_PPC64_CR4 = 72,
385 UNW_PPC64_CR5 = 73,
386 UNW_PPC64_CR6 = 74,
387 UNW_PPC64_CR7 = 75,
388 UNW_PPC64_XER = 76,
389 UNW_PPC64_V0 = 77,
390 UNW_PPC64_V1 = 78,
391 UNW_PPC64_V2 = 79,
392 UNW_PPC64_V3 = 80,
393 UNW_PPC64_V4 = 81,
394 UNW_PPC64_V5 = 82,
395 UNW_PPC64_V6 = 83,
396 UNW_PPC64_V7 = 84,
397 UNW_PPC64_V8 = 85,
398 UNW_PPC64_V9 = 86,
399 UNW_PPC64_V10 = 87,
400 UNW_PPC64_V11 = 88,
401 UNW_PPC64_V12 = 89,
402 UNW_PPC64_V13 = 90,
403 UNW_PPC64_V14 = 91,
404 UNW_PPC64_V15 = 92,
405 UNW_PPC64_V16 = 93,
406 UNW_PPC64_V17 = 94,
407 UNW_PPC64_V18 = 95,
408 UNW_PPC64_V19 = 96,
409 UNW_PPC64_V20 = 97,
410 UNW_PPC64_V21 = 98,
411 UNW_PPC64_V22 = 99,
412 UNW_PPC64_V23 = 100,
413 UNW_PPC64_V24 = 101,
414 UNW_PPC64_V25 = 102,
415 UNW_PPC64_V26 = 103,
416 UNW_PPC64_V27 = 104,
417 UNW_PPC64_V28 = 105,
418 UNW_PPC64_V29 = 106,
419 UNW_PPC64_V30 = 107,
420 UNW_PPC64_V31 = 108,
421 // 109, 111-113: OpenPOWER ELF V2 ABI: reserved
422 // Borrowing VRSAVE number from PPC32.
423 UNW_PPC64_VRSAVE = 109,
424 UNW_PPC64_VSCR = 110,
425 UNW_PPC64_TFHAR = 114,
426 UNW_PPC64_TFIAR = 115,
427 UNW_PPC64_TEXASR = 116,
428 UNW_PPC64_VS0 = UNW_PPC64_F0,
429 UNW_PPC64_VS1 = UNW_PPC64_F1,
430 UNW_PPC64_VS2 = UNW_PPC64_F2,
431 UNW_PPC64_VS3 = UNW_PPC64_F3,
432 UNW_PPC64_VS4 = UNW_PPC64_F4,
433 UNW_PPC64_VS5 = UNW_PPC64_F5,
434 UNW_PPC64_VS6 = UNW_PPC64_F6,
435 UNW_PPC64_VS7 = UNW_PPC64_F7,
436 UNW_PPC64_VS8 = UNW_PPC64_F8,
437 UNW_PPC64_VS9 = UNW_PPC64_F9,
438 UNW_PPC64_VS10 = UNW_PPC64_F10,
439 UNW_PPC64_VS11 = UNW_PPC64_F11,
440 UNW_PPC64_VS12 = UNW_PPC64_F12,
441 UNW_PPC64_VS13 = UNW_PPC64_F13,
442 UNW_PPC64_VS14 = UNW_PPC64_F14,
443 UNW_PPC64_VS15 = UNW_PPC64_F15,
444 UNW_PPC64_VS16 = UNW_PPC64_F16,
445 UNW_PPC64_VS17 = UNW_PPC64_F17,
446 UNW_PPC64_VS18 = UNW_PPC64_F18,
447 UNW_PPC64_VS19 = UNW_PPC64_F19,
448 UNW_PPC64_VS20 = UNW_PPC64_F20,
449 UNW_PPC64_VS21 = UNW_PPC64_F21,
450 UNW_PPC64_VS22 = UNW_PPC64_F22,
451 UNW_PPC64_VS23 = UNW_PPC64_F23,
452 UNW_PPC64_VS24 = UNW_PPC64_F24,
453 UNW_PPC64_VS25 = UNW_PPC64_F25,
454 UNW_PPC64_VS26 = UNW_PPC64_F26,
455 UNW_PPC64_VS27 = UNW_PPC64_F27,
456 UNW_PPC64_VS28 = UNW_PPC64_F28,
457 UNW_PPC64_VS29 = UNW_PPC64_F29,
458 UNW_PPC64_VS30 = UNW_PPC64_F30,
459 UNW_PPC64_VS31 = UNW_PPC64_F31,
460 UNW_PPC64_VS32 = UNW_PPC64_V0,
461 UNW_PPC64_VS33 = UNW_PPC64_V1,
462 UNW_PPC64_VS34 = UNW_PPC64_V2,
463 UNW_PPC64_VS35 = UNW_PPC64_V3,
464 UNW_PPC64_VS36 = UNW_PPC64_V4,
465 UNW_PPC64_VS37 = UNW_PPC64_V5,
466 UNW_PPC64_VS38 = UNW_PPC64_V6,
467 UNW_PPC64_VS39 = UNW_PPC64_V7,
468 UNW_PPC64_VS40 = UNW_PPC64_V8,
469 UNW_PPC64_VS41 = UNW_PPC64_V9,
470 UNW_PPC64_VS42 = UNW_PPC64_V10,
471 UNW_PPC64_VS43 = UNW_PPC64_V11,
472 UNW_PPC64_VS44 = UNW_PPC64_V12,
473 UNW_PPC64_VS45 = UNW_PPC64_V13,
474 UNW_PPC64_VS46 = UNW_PPC64_V14,
475 UNW_PPC64_VS47 = UNW_PPC64_V15,
476 UNW_PPC64_VS48 = UNW_PPC64_V16,
477 UNW_PPC64_VS49 = UNW_PPC64_V17,
478 UNW_PPC64_VS50 = UNW_PPC64_V18,
479 UNW_PPC64_VS51 = UNW_PPC64_V19,
480 UNW_PPC64_VS52 = UNW_PPC64_V20,
481 UNW_PPC64_VS53 = UNW_PPC64_V21,
482 UNW_PPC64_VS54 = UNW_PPC64_V22,
483 UNW_PPC64_VS55 = UNW_PPC64_V23,
484 UNW_PPC64_VS56 = UNW_PPC64_V24,
485 UNW_PPC64_VS57 = UNW_PPC64_V25,
486 UNW_PPC64_VS58 = UNW_PPC64_V26,
487 UNW_PPC64_VS59 = UNW_PPC64_V27,
488 UNW_PPC64_VS60 = UNW_PPC64_V28,
489 UNW_PPC64_VS61 = UNW_PPC64_V29,
490 UNW_PPC64_VS62 = UNW_PPC64_V30,
491 UNW_PPC64_VS63 = UNW_PPC64_V31
492 };
493
494 // 64-bit ARM64 registers
495 enum {
496 UNW_AARCH64_X0 = 0,
497 UNW_AARCH64_X1 = 1,
498 UNW_AARCH64_X2 = 2,
499 UNW_AARCH64_X3 = 3,
500 UNW_AARCH64_X4 = 4,
501 UNW_AARCH64_X5 = 5,
502 UNW_AARCH64_X6 = 6,
503 UNW_AARCH64_X7 = 7,
504 UNW_AARCH64_X8 = 8,
505 UNW_AARCH64_X9 = 9,
506 UNW_AARCH64_X10 = 10,
507 UNW_AARCH64_X11 = 11,
508 UNW_AARCH64_X12 = 12,
509 UNW_AARCH64_X13 = 13,
510 UNW_AARCH64_X14 = 14,
511 UNW_AARCH64_X15 = 15,
512 UNW_AARCH64_X16 = 16,
513 UNW_AARCH64_X17 = 17,
514 UNW_AARCH64_X18 = 18,
515 UNW_AARCH64_X19 = 19,
516 UNW_AARCH64_X20 = 20,
517 UNW_AARCH64_X21 = 21,
518 UNW_AARCH64_X22 = 22,
519 UNW_AARCH64_X23 = 23,
520 UNW_AARCH64_X24 = 24,
521 UNW_AARCH64_X25 = 25,
522 UNW_AARCH64_X26 = 26,
523 UNW_AARCH64_X27 = 27,
524 UNW_AARCH64_X28 = 28,
525 UNW_AARCH64_X29 = 29,
526 UNW_AARCH64_FP = 29,
527 UNW_AARCH64_X30 = 30,
528 UNW_AARCH64_LR = 30,
529 UNW_AARCH64_X31 = 31,
530 UNW_AARCH64_SP = 31,
531 UNW_AARCH64_PC = 32,
532
533 // reserved block
534 UNW_AARCH64_RA_SIGN_STATE = 34,
535
536 // FP/vector registers
537 UNW_AARCH64_V0 = 64,
538 UNW_AARCH64_V1 = 65,
539 UNW_AARCH64_V2 = 66,
540 UNW_AARCH64_V3 = 67,
541 UNW_AARCH64_V4 = 68,
542 UNW_AARCH64_V5 = 69,
543 UNW_AARCH64_V6 = 70,
544 UNW_AARCH64_V7 = 71,
545 UNW_AARCH64_V8 = 72,
546 UNW_AARCH64_V9 = 73,
547 UNW_AARCH64_V10 = 74,
548 UNW_AARCH64_V11 = 75,
549 UNW_AARCH64_V12 = 76,
550 UNW_AARCH64_V13 = 77,
551 UNW_AARCH64_V14 = 78,
552 UNW_AARCH64_V15 = 79,
553 UNW_AARCH64_V16 = 80,
554 UNW_AARCH64_V17 = 81,
555 UNW_AARCH64_V18 = 82,
556 UNW_AARCH64_V19 = 83,
557 UNW_AARCH64_V20 = 84,
558 UNW_AARCH64_V21 = 85,
559 UNW_AARCH64_V22 = 86,
560 UNW_AARCH64_V23 = 87,
561 UNW_AARCH64_V24 = 88,
562 UNW_AARCH64_V25 = 89,
563 UNW_AARCH64_V26 = 90,
564 UNW_AARCH64_V27 = 91,
565 UNW_AARCH64_V28 = 92,
566 UNW_AARCH64_V29 = 93,
567 UNW_AARCH64_V30 = 94,
568 UNW_AARCH64_V31 = 95,
569
570 // Compatibility aliases
571 UNW_ARM64_X0 = UNW_AARCH64_X0,
572 UNW_ARM64_X1 = UNW_AARCH64_X1,
573 UNW_ARM64_X2 = UNW_AARCH64_X2,
574 UNW_ARM64_X3 = UNW_AARCH64_X3,
575 UNW_ARM64_X4 = UNW_AARCH64_X4,
576 UNW_ARM64_X5 = UNW_AARCH64_X5,
577 UNW_ARM64_X6 = UNW_AARCH64_X6,
578 UNW_ARM64_X7 = UNW_AARCH64_X7,
579 UNW_ARM64_X8 = UNW_AARCH64_X8,
580 UNW_ARM64_X9 = UNW_AARCH64_X9,
581 UNW_ARM64_X10 = UNW_AARCH64_X10,
582 UNW_ARM64_X11 = UNW_AARCH64_X11,
583 UNW_ARM64_X12 = UNW_AARCH64_X12,
584 UNW_ARM64_X13 = UNW_AARCH64_X13,
585 UNW_ARM64_X14 = UNW_AARCH64_X14,
586 UNW_ARM64_X15 = UNW_AARCH64_X15,
587 UNW_ARM64_X16 = UNW_AARCH64_X16,
588 UNW_ARM64_X17 = UNW_AARCH64_X17,
589 UNW_ARM64_X18 = UNW_AARCH64_X18,
590 UNW_ARM64_X19 = UNW_AARCH64_X19,
591 UNW_ARM64_X20 = UNW_AARCH64_X20,
592 UNW_ARM64_X21 = UNW_AARCH64_X21,
593 UNW_ARM64_X22 = UNW_AARCH64_X22,
594 UNW_ARM64_X23 = UNW_AARCH64_X23,
595 UNW_ARM64_X24 = UNW_AARCH64_X24,
596 UNW_ARM64_X25 = UNW_AARCH64_X25,
597 UNW_ARM64_X26 = UNW_AARCH64_X26,
598 UNW_ARM64_X27 = UNW_AARCH64_X27,
599 UNW_ARM64_X28 = UNW_AARCH64_X28,
600 UNW_ARM64_X29 = UNW_AARCH64_X29,
601 UNW_ARM64_FP = UNW_AARCH64_FP,
602 UNW_ARM64_X30 = UNW_AARCH64_X30,
603 UNW_ARM64_LR = UNW_AARCH64_LR,
604 UNW_ARM64_X31 = UNW_AARCH64_X31,
605 UNW_ARM64_SP = UNW_AARCH64_SP,
606 UNW_ARM64_PC = UNW_AARCH64_PC,
607 UNW_ARM64_RA_SIGN_STATE = UNW_AARCH64_RA_SIGN_STATE,
608 UNW_ARM64_D0 = UNW_AARCH64_V0,
609 UNW_ARM64_D1 = UNW_AARCH64_V1,
610 UNW_ARM64_D2 = UNW_AARCH64_V2,
611 UNW_ARM64_D3 = UNW_AARCH64_V3,
612 UNW_ARM64_D4 = UNW_AARCH64_V4,
613 UNW_ARM64_D5 = UNW_AARCH64_V5,
614 UNW_ARM64_D6 = UNW_AARCH64_V6,
615 UNW_ARM64_D7 = UNW_AARCH64_V7,
616 UNW_ARM64_D8 = UNW_AARCH64_V8,
617 UNW_ARM64_D9 = UNW_AARCH64_V9,
618 UNW_ARM64_D10 = UNW_AARCH64_V10,
619 UNW_ARM64_D11 = UNW_AARCH64_V11,
620 UNW_ARM64_D12 = UNW_AARCH64_V12,
621 UNW_ARM64_D13 = UNW_AARCH64_V13,
622 UNW_ARM64_D14 = UNW_AARCH64_V14,
623 UNW_ARM64_D15 = UNW_AARCH64_V15,
624 UNW_ARM64_D16 = UNW_AARCH64_V16,
625 UNW_ARM64_D17 = UNW_AARCH64_V17,
626 UNW_ARM64_D18 = UNW_AARCH64_V18,
627 UNW_ARM64_D19 = UNW_AARCH64_V19,
628 UNW_ARM64_D20 = UNW_AARCH64_V20,
629 UNW_ARM64_D21 = UNW_AARCH64_V21,
630 UNW_ARM64_D22 = UNW_AARCH64_V22,
631 UNW_ARM64_D23 = UNW_AARCH64_V23,
632 UNW_ARM64_D24 = UNW_AARCH64_V24,
633 UNW_ARM64_D25 = UNW_AARCH64_V25,
634 UNW_ARM64_D26 = UNW_AARCH64_V26,
635 UNW_ARM64_D27 = UNW_AARCH64_V27,
636 UNW_ARM64_D28 = UNW_AARCH64_V28,
637 UNW_ARM64_D29 = UNW_AARCH64_V29,
638 UNW_ARM64_D30 = UNW_AARCH64_V30,
639 UNW_ARM64_D31 = UNW_AARCH64_V31,
640 };
641
642 // 32-bit ARM registers. Numbers match DWARF for ARM spec #3.1 Table 1.
643 // Naming scheme uses recommendations given in Note 4 for VFP-v2 and VFP-v3.
644 // In this scheme, even though the 64-bit floating point registers D0-D31
645 // overlap physically with the 32-bit floating pointer registers S0-S31,
646 // they are given a non-overlapping range of register numbers.
647 //
648 // Commented out ranges are not preserved during unwinding.
649 enum {
650 UNW_ARM_R0 = 0,
651 UNW_ARM_R1 = 1,
652 UNW_ARM_R2 = 2,
653 UNW_ARM_R3 = 3,
654 UNW_ARM_R4 = 4,
655 UNW_ARM_R5 = 5,
656 UNW_ARM_R6 = 6,
657 UNW_ARM_R7 = 7,
658 UNW_ARM_R8 = 8,
659 UNW_ARM_R9 = 9,
660 UNW_ARM_R10 = 10,
661 UNW_ARM_R11 = 11,
662 UNW_ARM_R12 = 12,
663 UNW_ARM_SP = 13, // Logical alias for UNW_REG_SP
664 UNW_ARM_R13 = 13,
665 UNW_ARM_LR = 14,
666 UNW_ARM_R14 = 14,
667 UNW_ARM_IP = 15, // Logical alias for UNW_REG_IP
668 UNW_ARM_R15 = 15,
669 // 16-63 -- OBSOLETE. Used in VFP1 to represent both S0-S31 and D0-D31.
670 UNW_ARM_S0 = 64,
671 UNW_ARM_S1 = 65,
672 UNW_ARM_S2 = 66,
673 UNW_ARM_S3 = 67,
674 UNW_ARM_S4 = 68,
675 UNW_ARM_S5 = 69,
676 UNW_ARM_S6 = 70,
677 UNW_ARM_S7 = 71,
678 UNW_ARM_S8 = 72,
679 UNW_ARM_S9 = 73,
680 UNW_ARM_S10 = 74,
681 UNW_ARM_S11 = 75,
682 UNW_ARM_S12 = 76,
683 UNW_ARM_S13 = 77,
684 UNW_ARM_S14 = 78,
685 UNW_ARM_S15 = 79,
686 UNW_ARM_S16 = 80,
687 UNW_ARM_S17 = 81,
688 UNW_ARM_S18 = 82,
689 UNW_ARM_S19 = 83,
690 UNW_ARM_S20 = 84,
691 UNW_ARM_S21 = 85,
692 UNW_ARM_S22 = 86,
693 UNW_ARM_S23 = 87,
694 UNW_ARM_S24 = 88,
695 UNW_ARM_S25 = 89,
696 UNW_ARM_S26 = 90,
697 UNW_ARM_S27 = 91,
698 UNW_ARM_S28 = 92,
699 UNW_ARM_S29 = 93,
700 UNW_ARM_S30 = 94,
701 UNW_ARM_S31 = 95,
702 // 96-103 -- OBSOLETE. F0-F7. Used by the FPA system. Superseded by VFP.
703 // 104-111 -- wCGR0-wCGR7, ACC0-ACC7 (Intel wireless MMX)
704 UNW_ARM_WR0 = 112,
705 UNW_ARM_WR1 = 113,
706 UNW_ARM_WR2 = 114,
707 UNW_ARM_WR3 = 115,
708 UNW_ARM_WR4 = 116,
709 UNW_ARM_WR5 = 117,
710 UNW_ARM_WR6 = 118,
711 UNW_ARM_WR7 = 119,
712 UNW_ARM_WR8 = 120,
713 UNW_ARM_WR9 = 121,
714 UNW_ARM_WR10 = 122,
715 UNW_ARM_WR11 = 123,
716 UNW_ARM_WR12 = 124,
717 UNW_ARM_WR13 = 125,
718 UNW_ARM_WR14 = 126,
719 UNW_ARM_WR15 = 127,
720 // 128-133 -- SPSR, SPSR_{FIQ|IRQ|ABT|UND|SVC}
721 // 134-142 -- Reserved
722 UNW_ARM_RA_AUTH_CODE = 143,
723 // 144-150 -- R8_USR-R14_USR
724 // 151-157 -- R8_FIQ-R14_FIQ
725 // 158-159 -- R13_IRQ-R14_IRQ
726 // 160-161 -- R13_ABT-R14_ABT
727 // 162-163 -- R13_UND-R14_UND
728 // 164-165 -- R13_SVC-R14_SVC
729 // 166-191 -- Reserved
730 UNW_ARM_WC0 = 192,
731 UNW_ARM_WC1 = 193,
732 UNW_ARM_WC2 = 194,
733 UNW_ARM_WC3 = 195,
734 // 196-199 -- wC4-wC7 (Intel wireless MMX control)
735 // 200-255 -- Reserved
736 UNW_ARM_D0 = 256,
737 UNW_ARM_D1 = 257,
738 UNW_ARM_D2 = 258,
739 UNW_ARM_D3 = 259,
740 UNW_ARM_D4 = 260,
741 UNW_ARM_D5 = 261,
742 UNW_ARM_D6 = 262,
743 UNW_ARM_D7 = 263,
744 UNW_ARM_D8 = 264,
745 UNW_ARM_D9 = 265,
746 UNW_ARM_D10 = 266,
747 UNW_ARM_D11 = 267,
748 UNW_ARM_D12 = 268,
749 UNW_ARM_D13 = 269,
750 UNW_ARM_D14 = 270,
751 UNW_ARM_D15 = 271,
752 UNW_ARM_D16 = 272,
753 UNW_ARM_D17 = 273,
754 UNW_ARM_D18 = 274,
755 UNW_ARM_D19 = 275,
756 UNW_ARM_D20 = 276,
757 UNW_ARM_D21 = 277,
758 UNW_ARM_D22 = 278,
759 UNW_ARM_D23 = 279,
760 UNW_ARM_D24 = 280,
761 UNW_ARM_D25 = 281,
762 UNW_ARM_D26 = 282,
763 UNW_ARM_D27 = 283,
764 UNW_ARM_D28 = 284,
765 UNW_ARM_D29 = 285,
766 UNW_ARM_D30 = 286,
767 UNW_ARM_D31 = 287,
768 // 288-319 -- Reserved for VFP/Neon
769 // 320-8191 -- Reserved
770 // 8192-16383 -- Unspecified vendor co-processor register.
771 };
772
773 // OpenRISC1000 register numbers
774 enum {
775 UNW_OR1K_R0 = 0,
776 UNW_OR1K_R1 = 1,
777 UNW_OR1K_R2 = 2,
778 UNW_OR1K_R3 = 3,
779 UNW_OR1K_R4 = 4,
780 UNW_OR1K_R5 = 5,
781 UNW_OR1K_R6 = 6,
782 UNW_OR1K_R7 = 7,
783 UNW_OR1K_R8 = 8,
784 UNW_OR1K_R9 = 9,
785 UNW_OR1K_R10 = 10,
786 UNW_OR1K_R11 = 11,
787 UNW_OR1K_R12 = 12,
788 UNW_OR1K_R13 = 13,
789 UNW_OR1K_R14 = 14,
790 UNW_OR1K_R15 = 15,
791 UNW_OR1K_R16 = 16,
792 UNW_OR1K_R17 = 17,
793 UNW_OR1K_R18 = 18,
794 UNW_OR1K_R19 = 19,
795 UNW_OR1K_R20 = 20,
796 UNW_OR1K_R21 = 21,
797 UNW_OR1K_R22 = 22,
798 UNW_OR1K_R23 = 23,
799 UNW_OR1K_R24 = 24,
800 UNW_OR1K_R25 = 25,
801 UNW_OR1K_R26 = 26,
802 UNW_OR1K_R27 = 27,
803 UNW_OR1K_R28 = 28,
804 UNW_OR1K_R29 = 29,
805 UNW_OR1K_R30 = 30,
806 UNW_OR1K_R31 = 31,
807 UNW_OR1K_EPCR = 32,
808 };
809
810 // MIPS registers
811 enum {
812 UNW_MIPS_R0 = 0,
813 UNW_MIPS_R1 = 1,
814 UNW_MIPS_R2 = 2,
815 UNW_MIPS_R3 = 3,
816 UNW_MIPS_R4 = 4,
817 UNW_MIPS_R5 = 5,
818 UNW_MIPS_R6 = 6,
819 UNW_MIPS_R7 = 7,
820 UNW_MIPS_R8 = 8,
821 UNW_MIPS_R9 = 9,
822 UNW_MIPS_R10 = 10,
823 UNW_MIPS_R11 = 11,
824 UNW_MIPS_R12 = 12,
825 UNW_MIPS_R13 = 13,
826 UNW_MIPS_R14 = 14,
827 UNW_MIPS_R15 = 15,
828 UNW_MIPS_R16 = 16,
829 UNW_MIPS_R17 = 17,
830 UNW_MIPS_R18 = 18,
831 UNW_MIPS_R19 = 19,
832 UNW_MIPS_R20 = 20,
833 UNW_MIPS_R21 = 21,
834 UNW_MIPS_R22 = 22,
835 UNW_MIPS_R23 = 23,
836 UNW_MIPS_R24 = 24,
837 UNW_MIPS_R25 = 25,
838 UNW_MIPS_R26 = 26,
839 UNW_MIPS_R27 = 27,
840 UNW_MIPS_R28 = 28,
841 UNW_MIPS_R29 = 29,
842 UNW_MIPS_R30 = 30,
843 UNW_MIPS_R31 = 31,
844 UNW_MIPS_F0 = 32,
845 UNW_MIPS_F1 = 33,
846 UNW_MIPS_F2 = 34,
847 UNW_MIPS_F3 = 35,
848 UNW_MIPS_F4 = 36,
849 UNW_MIPS_F5 = 37,
850 UNW_MIPS_F6 = 38,
851 UNW_MIPS_F7 = 39,
852 UNW_MIPS_F8 = 40,
853 UNW_MIPS_F9 = 41,
854 UNW_MIPS_F10 = 42,
855 UNW_MIPS_F11 = 43,
856 UNW_MIPS_F12 = 44,
857 UNW_MIPS_F13 = 45,
858 UNW_MIPS_F14 = 46,
859 UNW_MIPS_F15 = 47,
860 UNW_MIPS_F16 = 48,
861 UNW_MIPS_F17 = 49,
862 UNW_MIPS_F18 = 50,
863 UNW_MIPS_F19 = 51,
864 UNW_MIPS_F20 = 52,
865 UNW_MIPS_F21 = 53,
866 UNW_MIPS_F22 = 54,
867 UNW_MIPS_F23 = 55,
868 UNW_MIPS_F24 = 56,
869 UNW_MIPS_F25 = 57,
870 UNW_MIPS_F26 = 58,
871 UNW_MIPS_F27 = 59,
872 UNW_MIPS_F28 = 60,
873 UNW_MIPS_F29 = 61,
874 UNW_MIPS_F30 = 62,
875 UNW_MIPS_F31 = 63,
876 UNW_MIPS_HI = 64,
877 UNW_MIPS_LO = 65,
878 };
879
880 // SPARC registers
881 enum {
882 UNW_SPARC_G0 = 0,
883 UNW_SPARC_G1 = 1,
884 UNW_SPARC_G2 = 2,
885 UNW_SPARC_G3 = 3,
886 UNW_SPARC_G4 = 4,
887 UNW_SPARC_G5 = 5,
888 UNW_SPARC_G6 = 6,
889 UNW_SPARC_G7 = 7,
890 UNW_SPARC_O0 = 8,
891 UNW_SPARC_O1 = 9,
892 UNW_SPARC_O2 = 10,
893 UNW_SPARC_O3 = 11,
894 UNW_SPARC_O4 = 12,
895 UNW_SPARC_O5 = 13,
896 UNW_SPARC_O6 = 14,
897 UNW_SPARC_O7 = 15,
898 UNW_SPARC_L0 = 16,
899 UNW_SPARC_L1 = 17,
900 UNW_SPARC_L2 = 18,
901 UNW_SPARC_L3 = 19,
902 UNW_SPARC_L4 = 20,
903 UNW_SPARC_L5 = 21,
904 UNW_SPARC_L6 = 22,
905 UNW_SPARC_L7 = 23,
906 UNW_SPARC_I0 = 24,
907 UNW_SPARC_I1 = 25,
908 UNW_SPARC_I2 = 26,
909 UNW_SPARC_I3 = 27,
910 UNW_SPARC_I4 = 28,
911 UNW_SPARC_I5 = 29,
912 UNW_SPARC_I6 = 30,
913 UNW_SPARC_I7 = 31,
914 };
915
916 // Hexagon register numbers
917 enum {
918 UNW_HEXAGON_R0,
919 UNW_HEXAGON_R1,
920 UNW_HEXAGON_R2,
921 UNW_HEXAGON_R3,
922 UNW_HEXAGON_R4,
923 UNW_HEXAGON_R5,
924 UNW_HEXAGON_R6,
925 UNW_HEXAGON_R7,
926 UNW_HEXAGON_R8,
927 UNW_HEXAGON_R9,
928 UNW_HEXAGON_R10,
929 UNW_HEXAGON_R11,
930 UNW_HEXAGON_R12,
931 UNW_HEXAGON_R13,
932 UNW_HEXAGON_R14,
933 UNW_HEXAGON_R15,
934 UNW_HEXAGON_R16,
935 UNW_HEXAGON_R17,
936 UNW_HEXAGON_R18,
937 UNW_HEXAGON_R19,
938 UNW_HEXAGON_R20,
939 UNW_HEXAGON_R21,
940 UNW_HEXAGON_R22,
941 UNW_HEXAGON_R23,
942 UNW_HEXAGON_R24,
943 UNW_HEXAGON_R25,
944 UNW_HEXAGON_R26,
945 UNW_HEXAGON_R27,
946 UNW_HEXAGON_R28,
947 UNW_HEXAGON_R29,
948 UNW_HEXAGON_R30,
949 UNW_HEXAGON_R31,
950 UNW_HEXAGON_P3_0,
951 UNW_HEXAGON_PC,
952 };
953
954 // RISC-V registers. These match the DWARF register numbers defined by section
955 // 4 of the RISC-V ELF psABI specification, which can be found at:
956 //
957 // https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
958 enum {
959 UNW_RISCV_X0 = 0,
960 UNW_RISCV_X1 = 1,
961 UNW_RISCV_X2 = 2,
962 UNW_RISCV_X3 = 3,
963 UNW_RISCV_X4 = 4,
964 UNW_RISCV_X5 = 5,
965 UNW_RISCV_X6 = 6,
966 UNW_RISCV_X7 = 7,
967 UNW_RISCV_X8 = 8,
968 UNW_RISCV_X9 = 9,
969 UNW_RISCV_X10 = 10,
970 UNW_RISCV_X11 = 11,
971 UNW_RISCV_X12 = 12,
972 UNW_RISCV_X13 = 13,
973 UNW_RISCV_X14 = 14,
974 UNW_RISCV_X15 = 15,
975 UNW_RISCV_X16 = 16,
976 UNW_RISCV_X17 = 17,
977 UNW_RISCV_X18 = 18,
978 UNW_RISCV_X19 = 19,
979 UNW_RISCV_X20 = 20,
980 UNW_RISCV_X21 = 21,
981 UNW_RISCV_X22 = 22,
982 UNW_RISCV_X23 = 23,
983 UNW_RISCV_X24 = 24,
984 UNW_RISCV_X25 = 25,
985 UNW_RISCV_X26 = 26,
986 UNW_RISCV_X27 = 27,
987 UNW_RISCV_X28 = 28,
988 UNW_RISCV_X29 = 29,
989 UNW_RISCV_X30 = 30,
990 UNW_RISCV_X31 = 31,
991 UNW_RISCV_F0 = 32,
992 UNW_RISCV_F1 = 33,
993 UNW_RISCV_F2 = 34,
994 UNW_RISCV_F3 = 35,
995 UNW_RISCV_F4 = 36,
996 UNW_RISCV_F5 = 37,
997 UNW_RISCV_F6 = 38,
998 UNW_RISCV_F7 = 39,
999 UNW_RISCV_F8 = 40,
1000 UNW_RISCV_F9 = 41,
1001 UNW_RISCV_F10 = 42,
1002 UNW_RISCV_F11 = 43,
1003 UNW_RISCV_F12 = 44,
1004 UNW_RISCV_F13 = 45,
1005 UNW_RISCV_F14 = 46,
1006 UNW_RISCV_F15 = 47,
1007 UNW_RISCV_F16 = 48,
1008 UNW_RISCV_F17 = 49,
1009 UNW_RISCV_F18 = 50,
1010 UNW_RISCV_F19 = 51,
1011 UNW_RISCV_F20 = 52,
1012 UNW_RISCV_F21 = 53,
1013 UNW_RISCV_F22 = 54,
1014 UNW_RISCV_F23 = 55,
1015 UNW_RISCV_F24 = 56,
1016 UNW_RISCV_F25 = 57,
1017 UNW_RISCV_F26 = 58,
1018 UNW_RISCV_F27 = 59,
1019 UNW_RISCV_F28 = 60,
1020 UNW_RISCV_F29 = 61,
1021 UNW_RISCV_F30 = 62,
1022 UNW_RISCV_F31 = 63,
1023 };
1024
1025 // VE register numbers
1026 enum {
1027 UNW_VE_S0 = 0,
1028 UNW_VE_S1 = 1,
1029 UNW_VE_S2 = 2,
1030 UNW_VE_S3 = 3,
1031 UNW_VE_S4 = 4,
1032 UNW_VE_S5 = 5,
1033 UNW_VE_S6 = 6,
1034 UNW_VE_S7 = 7,
1035 UNW_VE_S8 = 8,
1036 UNW_VE_S9 = 9,
1037 UNW_VE_S10 = 10,
1038 UNW_VE_S11 = 11,
1039 UNW_VE_S12 = 12,
1040 UNW_VE_S13 = 13,
1041 UNW_VE_S14 = 14,
1042 UNW_VE_S15 = 15,
1043 UNW_VE_S16 = 16,
1044 UNW_VE_S17 = 17,
1045 UNW_VE_S18 = 18,
1046 UNW_VE_S19 = 19,
1047 UNW_VE_S20 = 20,
1048 UNW_VE_S21 = 21,
1049 UNW_VE_S22 = 22,
1050 UNW_VE_S23 = 23,
1051 UNW_VE_S24 = 24,
1052 UNW_VE_S25 = 25,
1053 UNW_VE_S26 = 26,
1054 UNW_VE_S27 = 27,
1055 UNW_VE_S28 = 28,
1056 UNW_VE_S29 = 29,
1057 UNW_VE_S30 = 30,
1058 UNW_VE_S31 = 31,
1059 UNW_VE_S32 = 32,
1060 UNW_VE_S33 = 33,
1061 UNW_VE_S34 = 34,
1062 UNW_VE_S35 = 35,
1063 UNW_VE_S36 = 36,
1064 UNW_VE_S37 = 37,
1065 UNW_VE_S38 = 38,
1066 UNW_VE_S39 = 39,
1067 UNW_VE_S40 = 40,
1068 UNW_VE_S41 = 41,
1069 UNW_VE_S42 = 42,
1070 UNW_VE_S43 = 43,
1071 UNW_VE_S44 = 44,
1072 UNW_VE_S45 = 45,
1073 UNW_VE_S46 = 46,
1074 UNW_VE_S47 = 47,
1075 UNW_VE_S48 = 48,
1076 UNW_VE_S49 = 49,
1077 UNW_VE_S50 = 50,
1078 UNW_VE_S51 = 51,
1079 UNW_VE_S52 = 52,
1080 UNW_VE_S53 = 53,
1081 UNW_VE_S54 = 54,
1082 UNW_VE_S55 = 55,
1083 UNW_VE_S56 = 56,
1084 UNW_VE_S57 = 57,
1085 UNW_VE_S58 = 58,
1086 UNW_VE_S59 = 59,
1087 UNW_VE_S60 = 60,
1088 UNW_VE_S61 = 61,
1089 UNW_VE_S62 = 62,
1090 UNW_VE_S63 = 63,
1091 UNW_VE_V0 = 64 + 0,
1092 UNW_VE_V1 = 64 + 1,
1093 UNW_VE_V2 = 64 + 2,
1094 UNW_VE_V3 = 64 + 3,
1095 UNW_VE_V4 = 64 + 4,
1096 UNW_VE_V5 = 64 + 5,
1097 UNW_VE_V6 = 64 + 6,
1098 UNW_VE_V7 = 64 + 7,
1099 UNW_VE_V8 = 64 + 8,
1100 UNW_VE_V9 = 64 + 9,
1101 UNW_VE_V10 = 64 + 10,
1102 UNW_VE_V11 = 64 + 11,
1103 UNW_VE_V12 = 64 + 12,
1104 UNW_VE_V13 = 64 + 13,
1105 UNW_VE_V14 = 64 + 14,
1106 UNW_VE_V15 = 64 + 15,
1107 UNW_VE_V16 = 64 + 16,
1108 UNW_VE_V17 = 64 + 17,
1109 UNW_VE_V18 = 64 + 18,
1110 UNW_VE_V19 = 64 + 19,
1111 UNW_VE_V20 = 64 + 20,
1112 UNW_VE_V21 = 64 + 21,
1113 UNW_VE_V22 = 64 + 22,
1114 UNW_VE_V23 = 64 + 23,
1115 UNW_VE_V24 = 64 + 24,
1116 UNW_VE_V25 = 64 + 25,
1117 UNW_VE_V26 = 64 + 26,
1118 UNW_VE_V27 = 64 + 27,
1119 UNW_VE_V28 = 64 + 28,
1120 UNW_VE_V29 = 64 + 29,
1121 UNW_VE_V30 = 64 + 30,
1122 UNW_VE_V31 = 64 + 31,
1123 UNW_VE_V32 = 64 + 32,
1124 UNW_VE_V33 = 64 + 33,
1125 UNW_VE_V34 = 64 + 34,
1126 UNW_VE_V35 = 64 + 35,
1127 UNW_VE_V36 = 64 + 36,
1128 UNW_VE_V37 = 64 + 37,
1129 UNW_VE_V38 = 64 + 38,
1130 UNW_VE_V39 = 64 + 39,
1131 UNW_VE_V40 = 64 + 40,
1132 UNW_VE_V41 = 64 + 41,
1133 UNW_VE_V42 = 64 + 42,
1134 UNW_VE_V43 = 64 + 43,
1135 UNW_VE_V44 = 64 + 44,
1136 UNW_VE_V45 = 64 + 45,
1137 UNW_VE_V46 = 64 + 46,
1138 UNW_VE_V47 = 64 + 47,
1139 UNW_VE_V48 = 64 + 48,
1140 UNW_VE_V49 = 64 + 49,
1141 UNW_VE_V50 = 64 + 50,
1142 UNW_VE_V51 = 64 + 51,
1143 UNW_VE_V52 = 64 + 52,
1144 UNW_VE_V53 = 64 + 53,
1145 UNW_VE_V54 = 64 + 54,
1146 UNW_VE_V55 = 64 + 55,
1147 UNW_VE_V56 = 64 + 56,
1148 UNW_VE_V57 = 64 + 57,
1149 UNW_VE_V58 = 64 + 58,
1150 UNW_VE_V59 = 64 + 59,
1151 UNW_VE_V60 = 64 + 60,
1152 UNW_VE_V61 = 64 + 61,
1153 UNW_VE_V62 = 64 + 62,
1154 UNW_VE_V63 = 64 + 63,
1155 UNW_VE_VM0 = 128 + 0,
1156 UNW_VE_VM1 = 128 + 1,
1157 UNW_VE_VM2 = 128 + 2,
1158 UNW_VE_VM3 = 128 + 3,
1159 UNW_VE_VM4 = 128 + 4,
1160 UNW_VE_VM5 = 128 + 5,
1161 UNW_VE_VM6 = 128 + 6,
1162 UNW_VE_VM7 = 128 + 7,
1163 UNW_VE_VM8 = 128 + 8,
1164 UNW_VE_VM9 = 128 + 9,
1165 UNW_VE_VM10 = 128 + 10,
1166 UNW_VE_VM11 = 128 + 11,
1167 UNW_VE_VM12 = 128 + 12,
1168 UNW_VE_VM13 = 128 + 13,
1169 UNW_VE_VM14 = 128 + 14,
1170 UNW_VE_VM15 = 128 + 15, // = 143
1171
1172 // Following registers don't have DWARF register numbers.
1173 UNW_VE_VIXR = 144,
1174 UNW_VE_VL = 145,
1175 };
1176
1177 #endif
LLVM monorepo