llvm/lib/CodeGen/MIRPrinter.cpp

   1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements the class that prints out the LLVM IR and machine
  10 // functions using the MIR serialization format.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "llvm/CodeGen/MIRPrinter.h"
  15 #include "llvm/ADT/DenseMap.h"
  16 #include "llvm/ADT/None.h"
  17 #include "llvm/ADT/STLExtras.h"
  18 #include "llvm/ADT/SmallBitVector.h"
  19 #include "llvm/ADT/SmallPtrSet.h"
  20 #include "llvm/ADT/SmallVector.h"
  21 #include "llvm/ADT/StringRef.h"
  22 #include "llvm/ADT/Twine.h"
  23 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
  24 #include "llvm/CodeGen/MIRYamlMapping.h"
  25 #include "llvm/CodeGen/MachineBasicBlock.h"
  26 #include "llvm/CodeGen/MachineConstantPool.h"
  27 #include "llvm/CodeGen/MachineFrameInfo.h"
  28 #include "llvm/CodeGen/MachineFunction.h"
  29 #include "llvm/CodeGen/MachineInstr.h"
  30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
  31 #include "llvm/CodeGen/MachineMemOperand.h"
  32 #include "llvm/CodeGen/MachineModuleSlotTracker.h"
  33 #include "llvm/CodeGen/MachineOperand.h"
  34 #include "llvm/CodeGen/MachineRegisterInfo.h"
  35 #include "llvm/CodeGen/PseudoSourceValue.h"
  36 #include "llvm/CodeGen/TargetFrameLowering.h"
  37 #include "llvm/CodeGen/TargetInstrInfo.h"
  38 #include "llvm/CodeGen/TargetRegisterInfo.h"
  39 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  40 #include "llvm/IR/BasicBlock.h"
  41 #include "llvm/IR/Constants.h"
  42 #include "llvm/IR/DebugInfo.h"
  43 #include "llvm/IR/DebugLoc.h"
  44 #include "llvm/IR/Function.h"
  45 #include "llvm/IR/GlobalValue.h"
  46 #include "llvm/IR/IRPrintingPasses.h"
  47 #include "llvm/IR/InstrTypes.h"
  48 #include "llvm/IR/Instructions.h"
  49 #include "llvm/IR/Intrinsics.h"
  50 #include "llvm/IR/Module.h"
  51 #include "llvm/IR/ModuleSlotTracker.h"
  52 #include "llvm/IR/Value.h"
  53 #include "llvm/MC/LaneBitmask.h"
  54 #include "llvm/MC/MCContext.h"
  55 #include "llvm/MC/MCDwarf.h"
  56 #include "llvm/MC/MCSymbol.h"
  57 #include "llvm/Support/AtomicOrdering.h"
  58 #include "llvm/Support/BranchProbability.h"
  59 #include "llvm/Support/Casting.h"
  60 #include "llvm/Support/CommandLine.h"
  61 #include "llvm/Support/ErrorHandling.h"
  62 #include "llvm/Support/Format.h"
  63 #include "llvm/Support/LowLevelTypeImpl.h"
  64 #include "llvm/Support/YAMLTraits.h"
  65 #include "llvm/Support/raw_ostream.h"
  66 #include "llvm/Target/TargetIntrinsicInfo.h"
  67 #include "llvm/Target/TargetMachine.h"
  68 #include <algorithm>
  69 #include <cassert>
  70 #include <cinttypes>
  71 #include <cstdint>
  72 #include <iterator>
  73 #include <string>
  74 #include <utility>
  75 #include <vector>
  76
  77 using namespace llvm;
  78
  79 static cl::opt<bool> SimplifyMIR(
  80     "simplify-mir", cl::Hidden,
  81     cl::desc("Leave out unnecessary information when printing MIR"));
  82
  83 static cl::opt<bool> PrintLocations("mir-debug-loc", cl::Hidden, cl::init(true),
  84                                     cl::desc("Print MIR debug-locations"));
  85
  86 namespace {
  87
  88 /// This structure describes how to print out stack object references.
  89 struct FrameIndexOperand {
  90   std::string Name;
  91   unsigned ID;
  92   bool IsFixed;
  93
  94   FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
  95       : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
  96
  97   /// Return an ordinary stack object reference.
  98   static FrameIndexOperand create(StringRef Name, unsigned ID) {
  99     return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
 100   }
 101
 102   /// Return a fixed stack object reference.
 103   static FrameIndexOperand createFixed(unsigned ID) {
 104     return FrameIndexOperand("", ID, /*IsFixed=*/true);
 105   }
 106 };
 107
 108 } // end anonymous namespace
 109
 110 namespace llvm {
 111
 112 /// This class prints out the machine functions using the MIR serialization
 113 /// format.
 114 class MIRPrinter {
 115   raw_ostream &OS;
 116   DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
 117   /// Maps from stack object indices to operand indices which will be used when
 118   /// printing frame index machine operands.
 119   DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
 120
 121 public:
 122   MIRPrinter(raw_ostream &OS) : OS(OS) {}
 123
 124   void print(const MachineFunction &MF);
 125
 126   void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
 127                const TargetRegisterInfo *TRI);
 128   void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
 129                const MachineFrameInfo &MFI);
 130   void convert(yaml::MachineFunction &MF,
 131                const MachineConstantPool &ConstantPool);
 132   void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
 133                const MachineJumpTableInfo &JTI);
 134   void convertStackObjects(yaml::MachineFunction &YMF,
 135                            const MachineFunction &MF, ModuleSlotTracker &MST);
 136   void convertCallSiteObjects(yaml::MachineFunction &YMF,
 137                               const MachineFunction &MF,
 138                               ModuleSlotTracker &MST);
 139   void convertMachineMetadataNodes(yaml::MachineFunction &YMF,
 140                                    const MachineFunction &MF,
 141                                    MachineModuleSlotTracker &MST);
 142
 143 private:
 144   void initRegisterMaskIds(const MachineFunction &MF);
 145 };
 146
 147 /// This class prints out the machine instructions using the MIR serialization
 148 /// format.
 149 class MIPrinter {
 150   raw_ostream &OS;
 151   ModuleSlotTracker &MST;
 152   const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
 153   const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
 154   /// Synchronization scope names registered with LLVMContext.
 155   SmallVector<StringRef, 8> SSNs;
 156
 157   bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const;
 158   bool canPredictSuccessors(const MachineBasicBlock &MBB) const;
 159
 160 public:
 161   MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
 162             const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
 163             const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
 164       : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
 165         StackObjectOperandMapping(StackObjectOperandMapping) {}
 166
 167   void print(const MachineBasicBlock &MBB);
 168
 169   void print(const MachineInstr &MI);
 170   void printStackObjectReference(int FrameIndex);
 171   void print(const MachineInstr &MI, unsigned OpIdx,
 172              const TargetRegisterInfo *TRI, const TargetInstrInfo *TII,
 173              bool ShouldPrintRegisterTies, LLT TypeToPrint,
 174              bool PrintDef = true);
 175 };
 176
 177 } // end namespace llvm
 178
 179 namespace llvm {
 180 namespace yaml {
 181
 182 /// This struct serializes the LLVM IR module.
 183 template <> struct BlockScalarTraits<Module> {
 184   static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
 185     Mod.print(OS, nullptr);
 186   }
 187
 188   static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
 189     llvm_unreachable("LLVM Module is supposed to be parsed separately");
 190     return "";
 191   }
 192 };
 193
 194 } // end namespace yaml
 195 } // end namespace llvm
 196
 197 static void printRegMIR(unsigned Reg, yaml::StringValue &Dest,
 198                         const TargetRegisterInfo *TRI) {
 199   raw_string_ostream OS(Dest.Value);
 200   OS << printReg(Reg, TRI);
 201 }
 202
 203 void MIRPrinter::print(const MachineFunction &MF) {
 204   initRegisterMaskIds(MF);
 205
 206   yaml::MachineFunction YamlMF;
 207   YamlMF.Name = MF.getName();
 208   YamlMF.Alignment = MF.getAlignment();
 209   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
 210   YamlMF.HasWinCFI = MF.hasWinCFI();
 211
 212   YamlMF.Legalized = MF.getProperties().hasProperty(
 213       MachineFunctionProperties::Property::Legalized);
 214   YamlMF.RegBankSelected = MF.getProperties().hasProperty(
 215       MachineFunctionProperties::Property::RegBankSelected);
 216   YamlMF.Selected = MF.getProperties().hasProperty(
 217       MachineFunctionProperties::Property::Selected);
 218   YamlMF.FailedISel = MF.getProperties().hasProperty(
 219       MachineFunctionProperties::Property::FailedISel);
 220   YamlMF.FailsVerification = MF.getProperties().hasProperty(
 221       MachineFunctionProperties::Property::FailsVerification);
 222   YamlMF.TracksDebugUserValues = MF.getProperties().hasProperty(
 223       MachineFunctionProperties::Property::TracksDebugUserValues);
 224
 225   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
 226   MachineModuleSlotTracker MST(&MF);
 227   MST.incorporateFunction(MF.getFunction());
 228   convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
 229   convertStackObjects(YamlMF, MF, MST);
 230   convertCallSiteObjects(YamlMF, MF, MST);
 231   for (const auto &Sub : MF.DebugValueSubstitutions) {
 232     const auto &SubSrc = Sub.Src;
 233     const auto &SubDest = Sub.Dest;
 234     YamlMF.DebugValueSubstitutions.push_back({SubSrc.first, SubSrc.second,
 235                                               SubDest.first,
 236                                               SubDest.second,
 237                                               Sub.Subreg});
 238   }
 239   if (const auto *ConstantPool = MF.getConstantPool())
 240     convert(YamlMF, *ConstantPool);
 241   if (const auto *JumpTableInfo = MF.getJumpTableInfo())
 242     convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
 243
 244   const TargetMachine &TM = MF.getTarget();
 245   YamlMF.MachineFuncInfo =
 246       std::unique_ptr<yaml::MachineFunctionInfo>(TM.convertFuncInfoToYAML(MF));
 247
 248   raw_string_ostream StrOS(YamlMF.Body.Value.Value);
 249   bool IsNewlineNeeded = false;
 250   for (const auto &MBB : MF) {
 251     if (IsNewlineNeeded)
 252       StrOS << "\n";
 253     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
 254         .print(MBB);
 255     IsNewlineNeeded = true;
 256   }
 257   StrOS.flush();
 258   // Convert machine metadata collected during the print of the machine
 259   // function.
 260   convertMachineMetadataNodes(YamlMF, MF, MST);
 261
 262   yaml::Output Out(OS);
 263   if (!SimplifyMIR)
 264       Out.setWriteDefaultValues(true);
 265   Out << YamlMF;
 266 }
 267
 268 static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
 269                                const TargetRegisterInfo *TRI) {
 270   assert(RegMask && "Can't print an empty register mask");
 271   OS << StringRef("CustomRegMask(");
 272
 273   bool IsRegInRegMaskFound = false;
 274   for (int I = 0, E = TRI->getNumRegs(); I < E; I++) {
 275     // Check whether the register is asserted in regmask.
 276     if (RegMask[I / 32] & (1u << (I % 32))) {
 277       if (IsRegInRegMaskFound)
 278         OS << ',';
 279       OS << printReg(I, TRI);
 280       IsRegInRegMaskFound = true;
 281     }
 282   }
 283
 284   OS << ')';
 285 }
 286
 287 static void printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest,
 288                                 const MachineRegisterInfo &RegInfo,
 289                                 const TargetRegisterInfo *TRI) {
 290   raw_string_ostream OS(Dest.Value);
 291   OS << printRegClassOrBank(Reg, RegInfo, TRI);
 292 }
 293
 294 template <typename T>
 295 static void
 296 printStackObjectDbgInfo(const MachineFunction::VariableDbgInfo &DebugVar,
 297                         T &Object, ModuleSlotTracker &MST) {
 298   std::array<std::string *, 3> Outputs{{&Object.DebugVar.Value,
 299                                         &Object.DebugExpr.Value,
 300                                         &Object.DebugLoc.Value}};
 301   std::array<const Metadata *, 3> Metas{{DebugVar.Var,
 302                                         DebugVar.Expr,
 303                                         DebugVar.Loc}};
 304   for (unsigned i = 0; i < 3; ++i) {
 305     raw_string_ostream StrOS(*Outputs[i]);
 306     Metas[i]->printAsOperand(StrOS, MST);
 307   }
 308 }
 309
 310 void MIRPrinter::convert(yaml::MachineFunction &MF,
 311                          const MachineRegisterInfo &RegInfo,
 312                          const TargetRegisterInfo *TRI) {
 313   MF.TracksRegLiveness = RegInfo.tracksLiveness();
 314
 315   // Print the virtual register definitions.
 316   for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
 317     unsigned Reg = Register::index2VirtReg(I);
 318     yaml::VirtualRegisterDefinition VReg;
 319     VReg.ID = I;
 320     if (RegInfo.getVRegName(Reg) != "")
 321       continue;
 322     ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI);
 323     unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
 324     if (PreferredReg)
 325       printRegMIR(PreferredReg, VReg.PreferredRegister, TRI);
 326     MF.VirtualRegisters.push_back(VReg);
 327   }
 328
 329   // Print the live ins.
 330   for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) {
 331     yaml::MachineFunctionLiveIn LiveIn;
 332     printRegMIR(LI.first, LiveIn.Register, TRI);
 333     if (LI.second)
 334       printRegMIR(LI.second, LiveIn.VirtualRegister, TRI);
 335     MF.LiveIns.push_back(LiveIn);
 336   }
 337
 338   // Prints the callee saved registers.
 339   if (RegInfo.isUpdatedCSRsInitialized()) {
 340     const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs();
 341     std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
 342     for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) {
 343       yaml::FlowStringValue Reg;
 344       printRegMIR(*I, Reg, TRI);
 345       CalleeSavedRegisters.push_back(Reg);
 346     }
 347     MF.CalleeSavedRegisters = CalleeSavedRegisters;
 348   }
 349 }
 350
 351 void MIRPrinter::convert(ModuleSlotTracker &MST,
 352                          yaml::MachineFrameInfo &YamlMFI,
 353                          const MachineFrameInfo &MFI) {
 354   YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
 355   YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
 356   YamlMFI.HasStackMap = MFI.hasStackMap();
 357   YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
 358   YamlMFI.StackSize = MFI.getStackSize();
 359   YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
 360   YamlMFI.MaxAlignment = MFI.getMaxAlign().value();
 361   YamlMFI.AdjustsStack = MFI.adjustsStack();
 362   YamlMFI.HasCalls = MFI.hasCalls();
 363   YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed()
 364     ? MFI.getMaxCallFrameSize() : ~0u;
 365   YamlMFI.CVBytesOfCalleeSavedRegisters =
 366       MFI.getCVBytesOfCalleeSavedRegisters();
 367   YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
 368   YamlMFI.HasVAStart = MFI.hasVAStart();
 369   YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
 370   YamlMFI.HasTailCall = MFI.hasTailCall();
 371   YamlMFI.LocalFrameSize = MFI.getLocalFrameSize();
 372   if (MFI.getSavePoint()) {
 373     raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
 374     StrOS << printMBBReference(*MFI.getSavePoint());
 375   }
 376   if (MFI.getRestorePoint()) {
 377     raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
 378     StrOS << printMBBReference(*MFI.getRestorePoint());
 379   }
 380 }
 381
 382 void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF,
 383                                      const MachineFunction &MF,
 384                                      ModuleSlotTracker &MST) {
 385   const MachineFrameInfo &MFI = MF.getFrameInfo();
 386   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
 387
 388   // Process fixed stack objects.
 389   assert(YMF.FixedStackObjects.empty());
 390   SmallVector<int, 32> FixedStackObjectsIdx;
 391   const int BeginIdx = MFI.getObjectIndexBegin();
 392   if (BeginIdx < 0)
 393     FixedStackObjectsIdx.reserve(-BeginIdx);
 394
 395   unsigned ID = 0;
 396   for (int I = BeginIdx; I < 0; ++I, ++ID) {
 397     FixedStackObjectsIdx.push_back(-1); // Fill index for possible dead.
 398     if (MFI.isDeadObjectIndex(I))
 399       continue;
 400
 401     yaml::FixedMachineStackObject YamlObject;
 402     YamlObject.ID = ID;
 403     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
 404                           ? yaml::FixedMachineStackObject::SpillSlot
 405                           : yaml::FixedMachineStackObject::DefaultType;
 406     YamlObject.Offset = MFI.getObjectOffset(I);
 407     YamlObject.Size = MFI.getObjectSize(I);
 408     YamlObject.Alignment = MFI.getObjectAlign(I);
 409     YamlObject.StackID = (TargetStackID::Value)MFI.getStackID(I);
 410     YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
 411     YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
 412     // Save the ID' position in FixedStackObjects storage vector.
 413     FixedStackObjectsIdx[ID] = YMF.FixedStackObjects.size();
 414     YMF.FixedStackObjects.push_back(YamlObject);
 415     StackObjectOperandMapping.insert(
 416         std::make_pair(I, FrameIndexOperand::createFixed(ID)));
 417   }
 418
 419   // Process ordinary stack objects.
 420   assert(YMF.StackObjects.empty());
 421   SmallVector<unsigned, 32> StackObjectsIdx;
 422   const int EndIdx = MFI.getObjectIndexEnd();
 423   if (EndIdx > 0)
 424     StackObjectsIdx.reserve(EndIdx);
 425   ID = 0;
 426   for (int I = 0; I < EndIdx; ++I, ++ID) {
 427     StackObjectsIdx.push_back(-1); // Fill index for possible dead.
 428     if (MFI.isDeadObjectIndex(I))
 429       continue;
 430
 431     yaml::MachineStackObject YamlObject;
 432     YamlObject.ID = ID;
 433     if (const auto *Alloca = MFI.getObjectAllocation(I))
 434       YamlObject.Name.Value = std::string(
 435           Alloca->hasName() ? Alloca->getName() : "");
 436     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
 437                           ? yaml::MachineStackObject::SpillSlot
 438                           : MFI.isVariableSizedObjectIndex(I)
 439                                 ? yaml::MachineStackObject::VariableSized
 440                                 : yaml::MachineStackObject::DefaultType;
 441     YamlObject.Offset = MFI.getObjectOffset(I);
 442     YamlObject.Size = MFI.getObjectSize(I);
 443     YamlObject.Alignment = MFI.getObjectAlign(I);
 444     YamlObject.StackID = (TargetStackID::Value)MFI.getStackID(I);
 445
 446     // Save the ID' position in StackObjects storage vector.
 447     StackObjectsIdx[ID] = YMF.StackObjects.size();
 448     YMF.StackObjects.push_back(YamlObject);
 449     StackObjectOperandMapping.insert(std::make_pair(
 450         I, FrameIndexOperand::create(YamlObject.Name.Value, ID)));
 451   }
 452
 453   for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
 454     const int FrameIdx = CSInfo.getFrameIdx();
 455     if (!CSInfo.isSpilledToReg() && MFI.isDeadObjectIndex(FrameIdx))
 456       continue;
 457
 458     yaml::StringValue Reg;
 459     printRegMIR(CSInfo.getReg(), Reg, TRI);
 460     if (!CSInfo.isSpilledToReg()) {
 461       assert(FrameIdx >= MFI.getObjectIndexBegin() &&
 462              FrameIdx < MFI.getObjectIndexEnd() &&
 463              "Invalid stack object index");
 464       if (FrameIdx < 0) { // Negative index means fixed objects.
 465         auto &Object =
 466             YMF.FixedStackObjects
 467                 [FixedStackObjectsIdx[FrameIdx + MFI.getNumFixedObjects()]];
 468         Object.CalleeSavedRegister = Reg;
 469         Object.CalleeSavedRestored = CSInfo.isRestored();
 470       } else {
 471         auto &Object = YMF.StackObjects[StackObjectsIdx[FrameIdx]];
 472         Object.CalleeSavedRegister = Reg;
 473         Object.CalleeSavedRestored = CSInfo.isRestored();
 474       }
 475     }
 476   }
 477   for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
 478     auto LocalObject = MFI.getLocalFrameObjectMap(I);
 479     assert(LocalObject.first >= 0 && "Expected a locally mapped stack object");
 480     YMF.StackObjects[StackObjectsIdx[LocalObject.first]].LocalOffset =
 481         LocalObject.second;
 482   }
 483
 484   // Print the stack object references in the frame information class after
 485   // converting the stack objects.
 486   if (MFI.hasStackProtectorIndex()) {
 487     raw_string_ostream StrOS(YMF.FrameInfo.StackProtector.Value);
 488     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
 489         .printStackObjectReference(MFI.getStackProtectorIndex());
 490   }
 491
 492   // Print the debug variable information.
 493   for (const MachineFunction::VariableDbgInfo &DebugVar :
 494        MF.getVariableDbgInfo()) {
 495     assert(DebugVar.Slot >= MFI.getObjectIndexBegin() &&
 496            DebugVar.Slot < MFI.getObjectIndexEnd() &&
 497            "Invalid stack object index");
 498     if (DebugVar.Slot < 0) { // Negative index means fixed objects.
 499       auto &Object =
 500           YMF.FixedStackObjects[FixedStackObjectsIdx[DebugVar.Slot +
 501                                                      MFI.getNumFixedObjects()]];
 502       printStackObjectDbgInfo(DebugVar, Object, MST);
 503     } else {
 504       auto &Object = YMF.StackObjects[StackObjectsIdx[DebugVar.Slot]];
 505       printStackObjectDbgInfo(DebugVar, Object, MST);
 506     }
 507   }
 508 }
 509
 510 void MIRPrinter::convertCallSiteObjects(yaml::MachineFunction &YMF,
 511                                         const MachineFunction &MF,
 512                                         ModuleSlotTracker &MST) {
 513   const auto *TRI = MF.getSubtarget().getRegisterInfo();
 514   for (auto CSInfo : MF.getCallSitesInfo()) {
 515     yaml::CallSiteInfo YmlCS;
 516     yaml::CallSiteInfo::MachineInstrLoc CallLocation;
 517
 518     // Prepare instruction position.
 519     MachineBasicBlock::const_instr_iterator CallI = CSInfo.first->getIterator();
 520     CallLocation.BlockNum = CallI->getParent()->getNumber();
 521     // Get call instruction offset from the beginning of block.
 522     CallLocation.Offset =
 523         std::distance(CallI->getParent()->instr_begin(), CallI);
 524     YmlCS.CallLocation = CallLocation;
 525     // Construct call arguments and theirs forwarding register info.
 526     for (auto ArgReg : CSInfo.second) {
 527       yaml::CallSiteInfo::ArgRegPair YmlArgReg;
 528       YmlArgReg.ArgNo = ArgReg.ArgNo;
 529       printRegMIR(ArgReg.Reg, YmlArgReg.Reg, TRI);
 530       YmlCS.ArgForwardingRegs.emplace_back(YmlArgReg);
 531     }
 532     YMF.CallSitesInfo.push_back(YmlCS);
 533   }
 534
 535   // Sort call info by position of call instructions.
 536   llvm::sort(YMF.CallSitesInfo.begin(), YMF.CallSitesInfo.end(),
 537              [](yaml::CallSiteInfo A, yaml::CallSiteInfo B) {
 538                if (A.CallLocation.BlockNum == B.CallLocation.BlockNum)
 539                  return A.CallLocation.Offset < B.CallLocation.Offset;
 540                return A.CallLocation.BlockNum < B.CallLocation.BlockNum;
 541              });
 542 }
 543
 544 void MIRPrinter::convertMachineMetadataNodes(yaml::MachineFunction &YMF,
 545                                              const MachineFunction &MF,
 546                                              MachineModuleSlotTracker &MST) {
 547   MachineModuleSlotTracker::MachineMDNodeListType MDList;
 548   MST.collectMachineMDNodes(MDList);
 549   for (auto &MD : MDList) {
 550     std::string NS;
 551     raw_string_ostream StrOS(NS);
 552     MD.second->print(StrOS, MST, MF.getFunction().getParent());
 553     YMF.MachineMetadataNodes.push_back(StrOS.str());
 554   }
 555 }
 556
 557 void MIRPrinter::convert(yaml::MachineFunction &MF,
 558                          const MachineConstantPool &ConstantPool) {
 559   unsigned ID = 0;
 560   for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
 561     std::string Str;
 562     raw_string_ostream StrOS(Str);
 563     if (Constant.isMachineConstantPoolEntry()) {
 564       Constant.Val.MachineCPVal->print(StrOS);
 565     } else {
 566       Constant.Val.ConstVal->printAsOperand(StrOS);
 567     }
 568
 569     yaml::MachineConstantPoolValue YamlConstant;
 570     YamlConstant.ID = ID++;
 571     YamlConstant.Value = StrOS.str();
 572     YamlConstant.Alignment = Constant.getAlign();
 573     YamlConstant.IsTargetSpecific = Constant.isMachineConstantPoolEntry();
 574
 575     MF.Constants.push_back(YamlConstant);
 576   }
 577 }
 578
 579 void MIRPrinter::convert(ModuleSlotTracker &MST,
 580                          yaml::MachineJumpTable &YamlJTI,
 581                          const MachineJumpTableInfo &JTI) {
 582   YamlJTI.Kind = JTI.getEntryKind();
 583   unsigned ID = 0;
 584   for (const auto &Table : JTI.getJumpTables()) {
 585     std::string Str;
 586     yaml::MachineJumpTable::Entry Entry;
 587     Entry.ID = ID++;
 588     for (const auto *MBB : Table.MBBs) {
 589       raw_string_ostream StrOS(Str);
 590       StrOS << printMBBReference(*MBB);
 591       Entry.Blocks.push_back(StrOS.str());
 592       Str.clear();
 593     }
 594     YamlJTI.Entries.push_back(Entry);
 595   }
 596 }
 597
 598 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
 599   const auto *TRI = MF.getSubtarget().getRegisterInfo();
 600   unsigned I = 0;
 601   for (const uint32_t *Mask : TRI->getRegMasks())
 602     RegisterMaskIds.insert(std::make_pair(Mask, I++));
 603 }
 604
 605 void llvm::guessSuccessors(const MachineBasicBlock &MBB,
 606                            SmallVectorImpl<MachineBasicBlock*> &Result,
 607                            bool &IsFallthrough) {
 608   SmallPtrSet<MachineBasicBlock*,8> Seen;
 609
 610   for (const MachineInstr &MI : MBB) {
 611     if (MI.isPHI())
 612       continue;
 613     for (const MachineOperand &MO : MI.operands()) {
 614       if (!MO.isMBB())
 615         continue;
 616       MachineBasicBlock *Succ = MO.getMBB();
 617       auto RP = Seen.insert(Succ);
 618       if (RP.second)
 619         Result.push_back(Succ);
 620     }
 621   }
 622   MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
 623   IsFallthrough = I == MBB.end() || !I->isBarrier();
 624 }
 625
 626 bool
 627 MIPrinter::canPredictBranchProbabilities(const MachineBasicBlock &MBB) const {
 628   if (MBB.succ_size() <= 1)
 629     return true;
 630   if (!MBB.hasSuccessorProbabilities())
 631     return true;
 632
 633   SmallVector<BranchProbability,8> Normalized(MBB.Probs.begin(),
 634                                               MBB.Probs.end());
 635   BranchProbability::normalizeProbabilities(Normalized.begin(),
 636                                             Normalized.end());
 637   SmallVector<BranchProbability,8> Equal(Normalized.size());
 638   BranchProbability::normalizeProbabilities(Equal.begin(), Equal.end());
 639
 640   return std::equal(Normalized.begin(), Normalized.end(), Equal.begin());
 641 }
 642
 643 bool MIPrinter::canPredictSuccessors(const MachineBasicBlock &MBB) const {
 644   SmallVector<MachineBasicBlock*,8> GuessedSuccs;
 645   bool GuessedFallthrough;
 646   guessSuccessors(MBB, GuessedSuccs, GuessedFallthrough);
 647   if (GuessedFallthrough) {
 648     const MachineFunction &MF = *MBB.getParent();
 649     MachineFunction::const_iterator NextI = std::next(MBB.getIterator());
 650     if (NextI != MF.end()) {
 651       MachineBasicBlock *Next = const_cast<MachineBasicBlock*>(&*NextI);
 652       if (!is_contained(GuessedSuccs, Next))
 653         GuessedSuccs.push_back(Next);
 654     }
 655   }
 656   if (GuessedSuccs.size() != MBB.succ_size())
 657     return false;
 658   return std::equal(MBB.succ_begin(), MBB.succ_end(), GuessedSuccs.begin());
 659 }
 660
 661 void MIPrinter::print(const MachineBasicBlock &MBB) {
 662   assert(MBB.getNumber() >= 0 && "Invalid MBB number");
 663   MBB.printName(OS,
 664                 MachineBasicBlock::PrintNameIr |
 665                     MachineBasicBlock::PrintNameAttributes,
 666                 &MST);
 667   OS << ":\n";
 668
 669   bool HasLineAttributes = false;
 670   // Print the successors
 671   bool canPredictProbs = canPredictBranchProbabilities(MBB);
 672   // Even if the list of successors is empty, if we cannot guess it,
 673   // we need to print it to tell the parser that the list is empty.
 674   // This is needed, because MI model unreachable as empty blocks
 675   // with an empty successor list. If the parser would see that
 676   // without the successor list, it would guess the code would
 677   // fallthrough.
 678   if ((!MBB.succ_empty() && !SimplifyMIR) || !canPredictProbs ||
 679       !canPredictSuccessors(MBB)) {
 680     OS.indent(2) << "successors: ";
 681     for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
 682       if (I != MBB.succ_begin())
 683         OS << ", ";
 684       OS << printMBBReference(**I);
 685       if (!SimplifyMIR || !canPredictProbs)
 686         OS << '('
 687            << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
 688            << ')';
 689     }
 690     OS << "\n";
 691     HasLineAttributes = true;
 692   }
 693
 694   // Print the live in registers.
 695   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
 696   if (MRI.tracksLiveness() && !MBB.livein_empty()) {
 697     const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
 698     OS.indent(2) << "liveins: ";
 699     bool First = true;
 700     for (const auto &LI : MBB.liveins()) {
 701       if (!First)
 702         OS << ", ";
 703       First = false;
 704       OS << printReg(LI.PhysReg, &TRI);
 705       if (!LI.LaneMask.all())
 706         OS << ":0x" << PrintLaneMask(LI.LaneMask);
 707     }
 708     OS << "\n";
 709     HasLineAttributes = true;
 710   }
 711
 712   if (HasLineAttributes)
 713     OS << "\n";
 714   bool IsInBundle = false;
 715   for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
 716     const MachineInstr &MI = *I;
 717     if (IsInBundle && !MI.isInsideBundle()) {
 718       OS.indent(2) << "}\n";
 719       IsInBundle = false;
 720     }
 721     OS.indent(IsInBundle ? 4 : 2);
 722     print(MI);
 723     if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
 724       OS << " {";
 725       IsInBundle = true;
 726     }
 727     OS << "\n";
 728   }
 729   if (IsInBundle)
 730     OS.indent(2) << "}\n";
 731 }
 732
 733 void MIPrinter::print(const MachineInstr &MI) {
 734   const auto *MF = MI.getMF();
 735   const auto &MRI = MF->getRegInfo();
 736   const auto &SubTarget = MF->getSubtarget();
 737   const auto *TRI = SubTarget.getRegisterInfo();
 738   assert(TRI && "Expected target register info");
 739   const auto *TII = SubTarget.getInstrInfo();
 740   assert(TII && "Expected target instruction info");
 741   if (MI.isCFIInstruction())
 742     assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
 743
 744   SmallBitVector PrintedTypes(8);
 745   bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies();
 746   unsigned I = 0, E = MI.getNumOperands();
 747   for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
 748          !MI.getOperand(I).isImplicit();
 749        ++I) {
 750     if (I)
 751       OS << ", ";
 752     print(MI, I, TRI, TII, ShouldPrintRegisterTies,
 753           MI.getTypeToPrint(I, PrintedTypes, MRI),
 754           /*PrintDef=*/false);
 755   }
 756
 757   if (I)
 758     OS << " = ";
 759   if (MI.getFlag(MachineInstr::FrameSetup))
 760     OS << "frame-setup ";
 761   if (MI.getFlag(MachineInstr::FrameDestroy))
 762     OS << "frame-destroy ";
 763   if (MI.getFlag(MachineInstr::FmNoNans))
 764     OS << "nnan ";
 765   if (MI.getFlag(MachineInstr::FmNoInfs))
 766     OS << "ninf ";
 767   if (MI.getFlag(MachineInstr::FmNsz))
 768     OS << "nsz ";
 769   if (MI.getFlag(MachineInstr::FmArcp))
 770     OS << "arcp ";
 771   if (MI.getFlag(MachineInstr::FmContract))
 772     OS << "contract ";
 773   if (MI.getFlag(MachineInstr::FmAfn))
 774     OS << "afn ";
 775   if (MI.getFlag(MachineInstr::FmReassoc))
 776     OS << "reassoc ";
 777   if (MI.getFlag(MachineInstr::NoUWrap))
 778     OS << "nuw ";
 779   if (MI.getFlag(MachineInstr::NoSWrap))
 780     OS << "nsw ";
 781   if (MI.getFlag(MachineInstr::IsExact))
 782     OS << "exact ";
 783   if (MI.getFlag(MachineInstr::NoFPExcept))
 784     OS << "nofpexcept ";
 785   if (MI.getFlag(MachineInstr::NoMerge))
 786     OS << "nomerge ";
 787
 788   OS << TII->getName(MI.getOpcode());
 789   if (I < E)
 790     OS << ' ';
 791
 792   bool NeedComma = false;
 793   for (; I < E; ++I) {
 794     if (NeedComma)
 795       OS << ", ";
 796     print(MI, I, TRI, TII, ShouldPrintRegisterTies,
 797           MI.getTypeToPrint(I, PrintedTypes, MRI));
 798     NeedComma = true;
 799   }
 800
 801   // Print any optional symbols attached to this instruction as-if they were
 802   // operands.
 803   if (MCSymbol *PreInstrSymbol = MI.getPreInstrSymbol()) {
 804     if (NeedComma)
 805       OS << ',';
 806     OS << " pre-instr-symbol ";
 807     MachineOperand::printSymbol(OS, *PreInstrSymbol);
 808     NeedComma = true;
 809   }
 810   if (MCSymbol *PostInstrSymbol = MI.getPostInstrSymbol()) {
 811     if (NeedComma)
 812       OS << ',';
 813     OS << " post-instr-symbol ";
 814     MachineOperand::printSymbol(OS, *PostInstrSymbol);
 815     NeedComma = true;
 816   }
 817   if (MDNode *HeapAllocMarker = MI.getHeapAllocMarker()) {
 818     if (NeedComma)
 819       OS << ',';
 820     OS << " heap-alloc-marker ";
 821     HeapAllocMarker->printAsOperand(OS, MST);
 822     NeedComma = true;
 823   }
 824
 825   if (auto Num = MI.peekDebugInstrNum()) {
 826     if (NeedComma)
 827       OS << ',';
 828     OS << " debug-instr-number " << Num;
 829     NeedComma = true;
 830   }
 831
 832   if (PrintLocations) {
 833     if (const DebugLoc &DL = MI.getDebugLoc()) {
 834       if (NeedComma)
 835         OS << ',';
 836       OS << " debug-location ";
 837       DL->printAsOperand(OS, MST);
 838     }
 839   }
 840
 841   if (!MI.memoperands_empty()) {
 842     OS << " :: ";
 843     const LLVMContext &Context = MF->getFunction().getContext();
 844     const MachineFrameInfo &MFI = MF->getFrameInfo();
 845     bool NeedComma = false;
 846     for (const auto *Op : MI.memoperands()) {
 847       if (NeedComma)
 848         OS << ", ";
 849       Op->print(OS, MST, SSNs, Context, &MFI, TII);
 850       NeedComma = true;
 851     }
 852   }
 853 }
 854
 855 void MIPrinter::printStackObjectReference(int FrameIndex) {
 856   auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
 857   assert(ObjectInfo != StackObjectOperandMapping.end() &&
 858          "Invalid frame index");
 859   const FrameIndexOperand &Operand = ObjectInfo->second;
 860   MachineOperand::printStackObjectReference(OS, Operand.ID, Operand.IsFixed,
 861                                             Operand.Name);
 862 }
 863
 864 static std::string formatOperandComment(std::string Comment) {
 865   if (Comment.empty())
 866     return Comment;
 867   return std::string(" /* " + Comment + " */");
 868 }
 869
 870 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
 871                       const TargetRegisterInfo *TRI,
 872                       const TargetInstrInfo *TII,
 873                       bool ShouldPrintRegisterTies, LLT TypeToPrint,
 874                       bool PrintDef) {
 875   const MachineOperand &Op = MI.getOperand(OpIdx);
 876   std::string MOComment = TII->createMIROperandComment(MI, Op, OpIdx, TRI);
 877
 878   switch (Op.getType()) {
 879   case MachineOperand::MO_Immediate:
 880     if (MI.isOperandSubregIdx(OpIdx)) {
 881       MachineOperand::printTargetFlags(OS, Op);
 882       MachineOperand::printSubRegIdx(OS, Op.getImm(), TRI);
 883       break;
 884     }
 885     LLVM_FALLTHROUGH;
 886   case MachineOperand::MO_Register:
 887   case MachineOperand::MO_CImmediate:
 888   case MachineOperand::MO_FPImmediate:
 889   case MachineOperand::MO_MachineBasicBlock:
 890   case MachineOperand::MO_ConstantPoolIndex:
 891   case MachineOperand::MO_TargetIndex:
 892   case MachineOperand::MO_JumpTableIndex:
 893   case MachineOperand::MO_ExternalSymbol:
 894   case MachineOperand::MO_GlobalAddress:
 895   case MachineOperand::MO_RegisterLiveOut:
 896   case MachineOperand::MO_Metadata:
 897   case MachineOperand::MO_MCSymbol:
 898   case MachineOperand::MO_CFIIndex:
 899   case MachineOperand::MO_IntrinsicID:
 900   case MachineOperand::MO_Predicate:
 901   case MachineOperand::MO_BlockAddress:
 902   case MachineOperand::MO_ShuffleMask: {
 903     unsigned TiedOperandIdx = 0;
 904     if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
 905       TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
 906     const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo();
 907     Op.print(OS, MST, TypeToPrint, OpIdx, PrintDef, /*IsStandalone=*/false,
 908              ShouldPrintRegisterTies, TiedOperandIdx, TRI, TII);
 909       OS << formatOperandComment(MOComment);
 910     break;
 911   }
 912   case MachineOperand::MO_FrameIndex:
 913     printStackObjectReference(Op.getIndex());
 914     break;
 915   case MachineOperand::MO_RegisterMask: {
 916     auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
 917     if (RegMaskInfo != RegisterMaskIds.end())
 918       OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
 919     else
 920       printCustomRegMask(Op.getRegMask(), OS, TRI);
 921     break;
 922   }
 923   }
 924 }
 925
 926 void MIRFormatter::printIRValue(raw_ostream &OS, const Value &V,
 927                                 ModuleSlotTracker &MST) {
 928   if (isa<GlobalValue>(V)) {
 929     V.printAsOperand(OS, /*PrintType=*/false, MST);
 930     return;
 931   }
 932   if (isa<Constant>(V)) {
 933     // Machine memory operands can load/store to/from constant value pointers.
 934     OS << '`';
 935     V.printAsOperand(OS, /*PrintType=*/true, MST);
 936     OS << '`';
 937     return;
 938   }
 939   OS << "%ir.";
 940   if (V.hasName()) {
 941     printLLVMNameWithoutPrefix(OS, V.getName());
 942     return;
 943   }
 944   int Slot = MST.getCurrentFunction() ? MST.getLocalSlot(&V) : -1;
 945   MachineOperand::printIRSlotNumber(OS, Slot);
 946 }
 947
 948 void llvm::printMIR(raw_ostream &OS, const Module &M) {
 949   yaml::Output Out(OS);
 950   Out << const_cast<Module &>(M);
 951 }
 952
 953 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
 954   MIRPrinter Printer(OS);
 955   Printer.print(MF);
 956 }