llvm/lib/CodeGen/MachineOperand.cpp

   1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 /// \file Methods common to all machine operands.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "llvm/CodeGen/MachineOperand.h"
  14 #include "llvm/ADT/FoldingSet.h"
  15 #include "llvm/ADT/StringExtras.h"
  16 #include "llvm/Analysis/Loads.h"
  17 #include "llvm/Analysis/MemoryLocation.h"
  18 #include "llvm/CodeGen/MIRFormatter.h"
  19 #include "llvm/CodeGen/MIRPrinter.h"
  20 #include "llvm/CodeGen/MachineFrameInfo.h"
  21 #include "llvm/CodeGen/MachineJumpTableInfo.h"
  22 #include "llvm/CodeGen/MachineRegisterInfo.h"
  23 #include "llvm/CodeGen/TargetInstrInfo.h"
  24 #include "llvm/CodeGen/TargetRegisterInfo.h"
  25 #include "llvm/Config/llvm-config.h"
  26 #include "llvm/IR/Constants.h"
  27 #include "llvm/IR/IRPrintingPasses.h"
  28 #include "llvm/IR/Instructions.h"
  29 #include "llvm/IR/ModuleSlotTracker.h"
  30 #include "llvm/MC/MCDwarf.h"
  31 #include "llvm/Target/TargetIntrinsicInfo.h"
  32 #include "llvm/Target/TargetMachine.h"
  33
  34 using namespace llvm;
  35
  36 static cl::opt<int>
  37     PrintRegMaskNumRegs("print-regmask-num-regs",
  38                         cl::desc("Number of registers to limit to when "
  39                                  "printing regmask operands in IR dumps. "
  40                                  "unlimited = -1"),
  41                         cl::init(32), cl::Hidden);
  42
  43 static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {
  44   if (const MachineInstr *MI = MO.getParent())
  45     if (const MachineBasicBlock *MBB = MI->getParent())
  46       if (const MachineFunction *MF = MBB->getParent())
  47         return MF;
  48   return nullptr;
  49 }
  50 static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
  51   return const_cast<MachineFunction *>(
  52       getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
  53 }
  54
  55 void MachineOperand::setReg(Register Reg) {
  56   if (getReg() == Reg)
  57     return; // No change.
  58
  59   // Clear the IsRenamable bit to keep it conservatively correct.
  60   IsRenamable = false;
  61
  62   // Otherwise, we have to change the register.  If this operand is embedded
  63   // into a machine function, we need to update the old and new register's
  64   // use/def lists.
  65   if (MachineFunction *MF = getMFIfAvailable(*this)) {
  66     MachineRegisterInfo &MRI = MF->getRegInfo();
  67     MRI.removeRegOperandFromUseList(this);
  68     SmallContents.RegNo = Reg;
  69     MRI.addRegOperandToUseList(this);
  70     return;
  71   }
  72
  73   // Otherwise, just change the register, no problem.  :)
  74   SmallContents.RegNo = Reg;
  75 }
  76
  77 void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx,
  78                                   const TargetRegisterInfo &TRI) {
  79   assert(Reg.isVirtual());
  80   if (SubIdx && getSubReg())
  81     SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
  82   setReg(Reg);
  83   if (SubIdx)
  84     setSubReg(SubIdx);
  85 }
  86
  87 void MachineOperand::substPhysReg(MCRegister Reg, const TargetRegisterInfo &TRI) {
  88   assert(Register::isPhysicalRegister(Reg));
  89   if (getSubReg()) {
  90     Reg = TRI.getSubReg(Reg, getSubReg());
  91     // Note that getSubReg() may return 0 if the sub-register doesn't exist.
  92     // That won't happen in legal code.
  93     setSubReg(0);
  94     if (isDef())
  95       setIsUndef(false);
  96   }
  97   setReg(Reg);
  98 }
  99
 100 /// Change a def to a use, or a use to a def.
 101 void MachineOperand::setIsDef(bool Val) {
 102   assert(isReg() && "Wrong MachineOperand accessor");
 103   assert((!Val || !isDebug()) && "Marking a debug operation as def");
 104   if (IsDef == Val)
 105     return;
 106   assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
 107   // MRI may keep uses and defs in different list positions.
 108   if (MachineFunction *MF = getMFIfAvailable(*this)) {
 109     MachineRegisterInfo &MRI = MF->getRegInfo();
 110     MRI.removeRegOperandFromUseList(this);
 111     IsDef = Val;
 112     MRI.addRegOperandToUseList(this);
 113     return;
 114   }
 115   IsDef = Val;
 116 }
 117
 118 bool MachineOperand::isRenamable() const {
 119   assert(isReg() && "Wrong MachineOperand accessor");
 120   assert(Register::isPhysicalRegister(getReg()) &&
 121          "isRenamable should only be checked on physical registers");
 122   if (!IsRenamable)
 123     return false;
 124
 125   const MachineInstr *MI = getParent();
 126   if (!MI)
 127     return true;
 128
 129   if (isDef())
 130     return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
 131
 132   assert(isUse() && "Reg is not def or use");
 133   return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
 134 }
 135
 136 void MachineOperand::setIsRenamable(bool Val) {
 137   assert(isReg() && "Wrong MachineOperand accessor");
 138   assert(Register::isPhysicalRegister(getReg()) &&
 139          "setIsRenamable should only be called on physical registers");
 140   IsRenamable = Val;
 141 }
 142
 143 // If this operand is currently a register operand, and if this is in a
 144 // function, deregister the operand from the register's use/def list.
 145 void MachineOperand::removeRegFromUses() {
 146   if (!isReg() || !isOnRegUseList())
 147     return;
 148
 149   if (MachineFunction *MF = getMFIfAvailable(*this))
 150     MF->getRegInfo().removeRegOperandFromUseList(this);
 151 }
 152
 153 /// ChangeToImmediate - Replace this operand with a new immediate operand of
 154 /// the specified value.  If an operand is known to be an immediate already,
 155 /// the setImm method should be used.
 156 void MachineOperand::ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags) {
 157   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
 158
 159   removeRegFromUses();
 160
 161   OpKind = MO_Immediate;
 162   Contents.ImmVal = ImmVal;
 163   setTargetFlags(TargetFlags);
 164 }
 165
 166 void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm,
 167                                          unsigned TargetFlags) {
 168   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
 169
 170   removeRegFromUses();
 171
 172   OpKind = MO_FPImmediate;
 173   Contents.CFP = FPImm;
 174   setTargetFlags(TargetFlags);
 175 }
 176
 177 void MachineOperand::ChangeToES(const char *SymName,
 178                                 unsigned TargetFlags) {
 179   assert((!isReg() || !isTied()) &&
 180          "Cannot change a tied operand into an external symbol");
 181
 182   removeRegFromUses();
 183
 184   OpKind = MO_ExternalSymbol;
 185   Contents.OffsetedInfo.Val.SymbolName = SymName;
 186   setOffset(0); // Offset is always 0.
 187   setTargetFlags(TargetFlags);
 188 }
 189
 190 void MachineOperand::ChangeToGA(const GlobalValue *GV, int64_t Offset,
 191                                 unsigned TargetFlags) {
 192   assert((!isReg() || !isTied()) &&
 193          "Cannot change a tied operand into a global address");
 194
 195   removeRegFromUses();
 196
 197   OpKind = MO_GlobalAddress;
 198   Contents.OffsetedInfo.Val.GV = GV;
 199   setOffset(Offset);
 200   setTargetFlags(TargetFlags);
 201 }
 202
 203 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags) {
 204   assert((!isReg() || !isTied()) &&
 205          "Cannot change a tied operand into an MCSymbol");
 206
 207   removeRegFromUses();
 208
 209   OpKind = MO_MCSymbol;
 210   Contents.Sym = Sym;
 211   setTargetFlags(TargetFlags);
 212 }
 213
 214 void MachineOperand::ChangeToFrameIndex(int Idx, unsigned TargetFlags) {
 215   assert((!isReg() || !isTied()) &&
 216          "Cannot change a tied operand into a FrameIndex");
 217
 218   removeRegFromUses();
 219
 220   OpKind = MO_FrameIndex;
 221   setIndex(Idx);
 222   setTargetFlags(TargetFlags);
 223 }
 224
 225 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
 226                                          unsigned TargetFlags) {
 227   assert((!isReg() || !isTied()) &&
 228          "Cannot change a tied operand into a FrameIndex");
 229
 230   removeRegFromUses();
 231
 232   OpKind = MO_TargetIndex;
 233   setIndex(Idx);
 234   setOffset(Offset);
 235   setTargetFlags(TargetFlags);
 236 }
 237
 238 /// ChangeToRegister - Replace this operand with a new register operand of
 239 /// the specified value.  If an operand is known to be an register already,
 240 /// the setReg method should be used.
 241 void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp,
 242                                       bool isKill, bool isDead, bool isUndef,
 243                                       bool isDebug) {
 244   MachineRegisterInfo *RegInfo = nullptr;
 245   if (MachineFunction *MF = getMFIfAvailable(*this))
 246     RegInfo = &MF->getRegInfo();
 247   // If this operand is already a register operand, remove it from the
 248   // register's use/def lists.
 249   bool WasReg = isReg();
 250   if (RegInfo && WasReg)
 251     RegInfo->removeRegOperandFromUseList(this);
 252
 253   // Ensure debug instructions set debug flag on register uses.
 254   const MachineInstr *MI = getParent();
 255   if (!isDef && MI && MI->isDebugInstr())
 256     isDebug = true;
 257
 258   // Change this to a register and set the reg#.
 259   assert(!(isDead && !isDef) && "Dead flag on non-def");
 260   assert(!(isKill && isDef) && "Kill flag on def");
 261   OpKind = MO_Register;
 262   SmallContents.RegNo = Reg;
 263   SubReg_TargetFlags = 0;
 264   IsDef = isDef;
 265   IsImp = isImp;
 266   IsDeadOrKill = isKill | isDead;
 267   IsRenamable = false;
 268   IsUndef = isUndef;
 269   IsInternalRead = false;
 270   IsEarlyClobber = false;
 271   IsDebug = isDebug;
 272   // Ensure isOnRegUseList() returns false.
 273   Contents.Reg.Prev = nullptr;
 274   // Preserve the tie when the operand was already a register.
 275   if (!WasReg)
 276     TiedTo = 0;
 277
 278   // If this operand is embedded in a function, add the operand to the
 279   // register's use/def list.
 280   if (RegInfo)
 281     RegInfo->addRegOperandToUseList(this);
 282 }
 283
 284 /// isIdenticalTo - Return true if this operand is identical to the specified
 285 /// operand. Note that this should stay in sync with the hash_value overload
 286 /// below.
 287 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
 288   if (getType() != Other.getType() ||
 289       getTargetFlags() != Other.getTargetFlags())
 290     return false;
 291
 292   switch (getType()) {
 293   case MachineOperand::MO_Register:
 294     return getReg() == Other.getReg() && isDef() == Other.isDef() &&
 295            getSubReg() == Other.getSubReg();
 296   case MachineOperand::MO_Immediate:
 297     return getImm() == Other.getImm();
 298   case MachineOperand::MO_CImmediate:
 299     return getCImm() == Other.getCImm();
 300   case MachineOperand::MO_FPImmediate:
 301     return getFPImm() == Other.getFPImm();
 302   case MachineOperand::MO_MachineBasicBlock:
 303     return getMBB() == Other.getMBB();
 304   case MachineOperand::MO_FrameIndex:
 305     return getIndex() == Other.getIndex();
 306   case MachineOperand::MO_ConstantPoolIndex:
 307   case MachineOperand::MO_TargetIndex:
 308     return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
 309   case MachineOperand::MO_JumpTableIndex:
 310     return getIndex() == Other.getIndex();
 311   case MachineOperand::MO_GlobalAddress:
 312     return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
 313   case MachineOperand::MO_ExternalSymbol:
 314     return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
 315            getOffset() == Other.getOffset();
 316   case MachineOperand::MO_BlockAddress:
 317     return getBlockAddress() == Other.getBlockAddress() &&
 318            getOffset() == Other.getOffset();
 319   case MachineOperand::MO_RegisterMask:
 320   case MachineOperand::MO_RegisterLiveOut: {
 321     // Shallow compare of the two RegMasks
 322     const uint32_t *RegMask = getRegMask();
 323     const uint32_t *OtherRegMask = Other.getRegMask();
 324     if (RegMask == OtherRegMask)
 325       return true;
 326
 327     if (const MachineFunction *MF = getMFIfAvailable(*this)) {
 328       // Calculate the size of the RegMask
 329       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
 330       unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
 331
 332       // Deep compare of the two RegMasks
 333       return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
 334     }
 335     // We don't know the size of the RegMask, so we can't deep compare the two
 336     // reg masks.
 337     return false;
 338   }
 339   case MachineOperand::MO_MCSymbol:
 340     return getMCSymbol() == Other.getMCSymbol();
 341   case MachineOperand::MO_CFIIndex:
 342     return getCFIIndex() == Other.getCFIIndex();
 343   case MachineOperand::MO_Metadata:
 344     return getMetadata() == Other.getMetadata();
 345   case MachineOperand::MO_IntrinsicID:
 346     return getIntrinsicID() == Other.getIntrinsicID();
 347   case MachineOperand::MO_Predicate:
 348     return getPredicate() == Other.getPredicate();
 349   case MachineOperand::MO_ShuffleMask:
 350     return getShuffleMask() == Other.getShuffleMask();
 351   }
 352   llvm_unreachable("Invalid machine operand type");
 353 }
 354
 355 // Note: this must stay exactly in sync with isIdenticalTo above.
 356 hash_code llvm::hash_value(const MachineOperand &MO) {
 357   switch (MO.getType()) {
 358   case MachineOperand::MO_Register:
 359     // Register operands don't have target flags.
 360     return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
 361   case MachineOperand::MO_Immediate:
 362     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
 363   case MachineOperand::MO_CImmediate:
 364     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
 365   case MachineOperand::MO_FPImmediate:
 366     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
 367   case MachineOperand::MO_MachineBasicBlock:
 368     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
 369   case MachineOperand::MO_FrameIndex:
 370     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
 371   case MachineOperand::MO_ConstantPoolIndex:
 372   case MachineOperand::MO_TargetIndex:
 373     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
 374                         MO.getOffset());
 375   case MachineOperand::MO_JumpTableIndex:
 376     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
 377   case MachineOperand::MO_ExternalSymbol:
 378     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
 379                         StringRef(MO.getSymbolName()));
 380   case MachineOperand::MO_GlobalAddress:
 381     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
 382                         MO.getOffset());
 383   case MachineOperand::MO_BlockAddress:
 384     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
 385                         MO.getOffset());
 386   case MachineOperand::MO_RegisterMask:
 387   case MachineOperand::MO_RegisterLiveOut:
 388     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
 389   case MachineOperand::MO_Metadata:
 390     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
 391   case MachineOperand::MO_MCSymbol:
 392     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
 393   case MachineOperand::MO_CFIIndex:
 394     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
 395   case MachineOperand::MO_IntrinsicID:
 396     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
 397   case MachineOperand::MO_Predicate:
 398     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
 399   case MachineOperand::MO_ShuffleMask:
 400     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getShuffleMask());
 401   }
 402   llvm_unreachable("Invalid machine operand type");
 403 }
 404
 405 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
 406 // it.
 407 static void tryToGetTargetInfo(const MachineOperand &MO,
 408                                const TargetRegisterInfo *&TRI,
 409                                const TargetIntrinsicInfo *&IntrinsicInfo) {
 410   if (const MachineFunction *MF = getMFIfAvailable(MO)) {
 411     TRI = MF->getSubtarget().getRegisterInfo();
 412     IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
 413   }
 414 }
 415
 416 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
 417   const auto *TII = MF.getSubtarget().getInstrInfo();
 418   assert(TII && "expected instruction info");
 419   auto Indices = TII->getSerializableTargetIndices();
 420   auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
 421     return I.first == Index;
 422   });
 423   if (Found != Indices.end())
 424     return Found->second;
 425   return nullptr;
 426 }
 427
 428 const char *MachineOperand::getTargetIndexName() const {
 429   const MachineFunction *MF = getMFIfAvailable(*this);
 430   return MF ? ::getTargetIndexName(*MF, this->getIndex()) : nullptr;
 431 }
 432
 433 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
 434   auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
 435   for (const auto &I : Flags) {
 436     if (I.first == TF) {
 437       return I.second;
 438     }
 439   }
 440   return nullptr;
 441 }
 442
 443 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
 444                              const TargetRegisterInfo *TRI) {
 445   if (!TRI) {
 446     OS << "%dwarfreg." << DwarfReg;
 447     return;
 448   }
 449
 450   if (Optional<unsigned> Reg = TRI->getLLVMRegNum(DwarfReg, true))
 451     OS << printReg(*Reg, TRI);
 452   else
 453     OS << "<badreg>";
 454 }
 455
 456 static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
 457                                   ModuleSlotTracker &MST) {
 458   OS << "%ir-block.";
 459   if (BB.hasName()) {
 460     printLLVMNameWithoutPrefix(OS, BB.getName());
 461     return;
 462   }
 463   Optional<int> Slot;
 464   if (const Function *F = BB.getParent()) {
 465     if (F == MST.getCurrentFunction()) {
 466       Slot = MST.getLocalSlot(&BB);
 467     } else if (const Module *M = F->getParent()) {
 468       ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
 469       CustomMST.incorporateFunction(*F);
 470       Slot = CustomMST.getLocalSlot(&BB);
 471     }
 472   }
 473   if (Slot)
 474     MachineOperand::printIRSlotNumber(OS, *Slot);
 475   else
 476     OS << "<unknown>";
 477 }
 478
 479 static void printSyncScope(raw_ostream &OS, const LLVMContext &Context,
 480                            SyncScope::ID SSID,
 481                            SmallVectorImpl<StringRef> &SSNs) {
 482   switch (SSID) {
 483   case SyncScope::System:
 484     break;
 485   default:
 486     if (SSNs.empty())
 487       Context.getSyncScopeNames(SSNs);
 488
 489     OS << "syncscope(\"";
 490     printEscapedString(SSNs[SSID], OS);
 491     OS << "\") ";
 492     break;
 493   }
 494 }
 495
 496 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
 497                                         unsigned TMMOFlag) {
 498   auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
 499   for (const auto &I : Flags) {
 500     if (I.first == TMMOFlag) {
 501       return I.second;
 502     }
 503   }
 504   return nullptr;
 505 }
 506
 507 static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
 508                             const MachineFrameInfo *MFI) {
 509   StringRef Name;
 510   if (MFI) {
 511     IsFixed = MFI->isFixedObjectIndex(FrameIndex);
 512     if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
 513       if (Alloca->hasName())
 514         Name = Alloca->getName();
 515     if (IsFixed)
 516       FrameIndex -= MFI->getObjectIndexBegin();
 517   }
 518   MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
 519 }
 520
 521 void MachineOperand::printSubRegIdx(raw_ostream &OS, uint64_t Index,
 522                                     const TargetRegisterInfo *TRI) {
 523   OS << "%subreg.";
 524   if (TRI)
 525     OS << TRI->getSubRegIndexName(Index);
 526   else
 527     OS << Index;
 528 }
 529
 530 void MachineOperand::printTargetFlags(raw_ostream &OS,
 531                                       const MachineOperand &Op) {
 532   if (!Op.getTargetFlags())
 533     return;
 534   const MachineFunction *MF = getMFIfAvailable(Op);
 535   if (!MF)
 536     return;
 537
 538   const auto *TII = MF->getSubtarget().getInstrInfo();
 539   assert(TII && "expected instruction info");
 540   auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
 541   OS << "target-flags(";
 542   const bool HasDirectFlags = Flags.first;
 543   const bool HasBitmaskFlags = Flags.second;
 544   if (!HasDirectFlags && !HasBitmaskFlags) {
 545     OS << "<unknown>) ";
 546     return;
 547   }
 548   if (HasDirectFlags) {
 549     if (const auto *Name = getTargetFlagName(TII, Flags.first))
 550       OS << Name;
 551     else
 552       OS << "<unknown target flag>";
 553   }
 554   if (!HasBitmaskFlags) {
 555     OS << ") ";
 556     return;
 557   }
 558   bool IsCommaNeeded = HasDirectFlags;
 559   unsigned BitMask = Flags.second;
 560   auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
 561   for (const auto &Mask : BitMasks) {
 562     // Check if the flag's bitmask has the bits of the current mask set.
 563     if ((BitMask & Mask.first) == Mask.first) {
 564       if (IsCommaNeeded)
 565         OS << ", ";
 566       IsCommaNeeded = true;
 567       OS << Mask.second;
 568       // Clear the bits which were serialized from the flag's bitmask.
 569       BitMask &= ~(Mask.first);
 570     }
 571   }
 572   if (BitMask) {
 573     // When the resulting flag's bitmask isn't zero, we know that we didn't
 574     // serialize all of the bit flags.
 575     if (IsCommaNeeded)
 576       OS << ", ";
 577     OS << "<unknown bitmask target flag>";
 578   }
 579   OS << ") ";
 580 }
 581
 582 void MachineOperand::printSymbol(raw_ostream &OS, MCSymbol &Sym) {
 583   OS << "<mcsymbol " << Sym << ">";
 584 }
 585
 586 void MachineOperand::printStackObjectReference(raw_ostream &OS,
 587                                                unsigned FrameIndex,
 588                                                bool IsFixed, StringRef Name) {
 589   if (IsFixed) {
 590     OS << "%fixed-stack." << FrameIndex;
 591     return;
 592   }
 593
 594   OS << "%stack." << FrameIndex;
 595   if (!Name.empty())
 596     OS << '.' << Name;
 597 }
 598
 599 void MachineOperand::printOperandOffset(raw_ostream &OS, int64_t Offset) {
 600   if (Offset == 0)
 601     return;
 602   if (Offset < 0) {
 603     OS << " - " << -Offset;
 604     return;
 605   }
 606   OS << " + " << Offset;
 607 }
 608
 609 void MachineOperand::printIRSlotNumber(raw_ostream &OS, int Slot) {
 610   if (Slot == -1)
 611     OS << "<badref>";
 612   else
 613     OS << Slot;
 614 }
 615
 616 static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
 617                      const TargetRegisterInfo *TRI) {
 618   switch (CFI.getOperation()) {
 619   case MCCFIInstruction::OpSameValue:
 620     OS << "same_value ";
 621     if (MCSymbol *Label = CFI.getLabel())
 622       MachineOperand::printSymbol(OS, *Label);
 623     printCFIRegister(CFI.getRegister(), OS, TRI);
 624     break;
 625   case MCCFIInstruction::OpRememberState:
 626     OS << "remember_state ";
 627     if (MCSymbol *Label = CFI.getLabel())
 628       MachineOperand::printSymbol(OS, *Label);
 629     break;
 630   case MCCFIInstruction::OpRestoreState:
 631     OS << "restore_state ";
 632     if (MCSymbol *Label = CFI.getLabel())
 633       MachineOperand::printSymbol(OS, *Label);
 634     break;
 635   case MCCFIInstruction::OpOffset:
 636     OS << "offset ";
 637     if (MCSymbol *Label = CFI.getLabel())
 638       MachineOperand::printSymbol(OS, *Label);
 639     printCFIRegister(CFI.getRegister(), OS, TRI);
 640     OS << ", " << CFI.getOffset();
 641     break;
 642   case MCCFIInstruction::OpDefCfaRegister:
 643     OS << "def_cfa_register ";
 644     if (MCSymbol *Label = CFI.getLabel())
 645       MachineOperand::printSymbol(OS, *Label);
 646     printCFIRegister(CFI.getRegister(), OS, TRI);
 647     break;
 648   case MCCFIInstruction::OpDefCfaOffset:
 649     OS << "def_cfa_offset ";
 650     if (MCSymbol *Label = CFI.getLabel())
 651       MachineOperand::printSymbol(OS, *Label);
 652     OS << CFI.getOffset();
 653     break;
 654   case MCCFIInstruction::OpDefCfa:
 655     OS << "def_cfa ";
 656     if (MCSymbol *Label = CFI.getLabel())
 657       MachineOperand::printSymbol(OS, *Label);
 658     printCFIRegister(CFI.getRegister(), OS, TRI);
 659     OS << ", " << CFI.getOffset();
 660     break;
 661   case MCCFIInstruction::OpLLVMDefAspaceCfa:
 662     OS << "llvm_def_aspace_cfa ";
 663     if (MCSymbol *Label = CFI.getLabel())
 664       MachineOperand::printSymbol(OS, *Label);
 665     printCFIRegister(CFI.getRegister(), OS, TRI);
 666     OS << ", " << CFI.getOffset();
 667     OS << ", " << CFI.getAddressSpace();
 668     break;
 669   case MCCFIInstruction::OpRelOffset:
 670     OS << "rel_offset ";
 671     if (MCSymbol *Label = CFI.getLabel())
 672       MachineOperand::printSymbol(OS, *Label);
 673     printCFIRegister(CFI.getRegister(), OS, TRI);
 674     OS << ", " << CFI.getOffset();
 675     break;
 676   case MCCFIInstruction::OpAdjustCfaOffset:
 677     OS << "adjust_cfa_offset ";
 678     if (MCSymbol *Label = CFI.getLabel())
 679       MachineOperand::printSymbol(OS, *Label);
 680     OS << CFI.getOffset();
 681     break;
 682   case MCCFIInstruction::OpRestore:
 683     OS << "restore ";
 684     if (MCSymbol *Label = CFI.getLabel())
 685       MachineOperand::printSymbol(OS, *Label);
 686     printCFIRegister(CFI.getRegister(), OS, TRI);
 687     break;
 688   case MCCFIInstruction::OpEscape: {
 689     OS << "escape ";
 690     if (MCSymbol *Label = CFI.getLabel())
 691       MachineOperand::printSymbol(OS, *Label);
 692     if (!CFI.getValues().empty()) {
 693       size_t e = CFI.getValues().size() - 1;
 694       for (size_t i = 0; i < e; ++i)
 695         OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
 696       OS << format("0x%02x", uint8_t(CFI.getValues()[e]));
 697     }
 698     break;
 699   }
 700   case MCCFIInstruction::OpUndefined:
 701     OS << "undefined ";
 702     if (MCSymbol *Label = CFI.getLabel())
 703       MachineOperand::printSymbol(OS, *Label);
 704     printCFIRegister(CFI.getRegister(), OS, TRI);
 705     break;
 706   case MCCFIInstruction::OpRegister:
 707     OS << "register ";
 708     if (MCSymbol *Label = CFI.getLabel())
 709       MachineOperand::printSymbol(OS, *Label);
 710     printCFIRegister(CFI.getRegister(), OS, TRI);
 711     OS << ", ";
 712     printCFIRegister(CFI.getRegister2(), OS, TRI);
 713     break;
 714   case MCCFIInstruction::OpWindowSave:
 715     OS << "window_save ";
 716     if (MCSymbol *Label = CFI.getLabel())
 717       MachineOperand::printSymbol(OS, *Label);
 718     break;
 719   case MCCFIInstruction::OpNegateRAState:
 720     OS << "negate_ra_sign_state ";
 721     if (MCSymbol *Label = CFI.getLabel())
 722       MachineOperand::printSymbol(OS, *Label);
 723     break;
 724   default:
 725     // TODO: Print the other CFI Operations.
 726     OS << "<unserializable cfi directive>";
 727     break;
 728   }
 729 }
 730
 731 void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
 732                            const TargetIntrinsicInfo *IntrinsicInfo) const {
 733   print(OS, LLT{}, TRI, IntrinsicInfo);
 734 }
 735
 736 void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
 737                            const TargetRegisterInfo *TRI,
 738                            const TargetIntrinsicInfo *IntrinsicInfo) const {
 739   tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
 740   ModuleSlotTracker DummyMST(nullptr);
 741   print(OS, DummyMST, TypeToPrint, None, /*PrintDef=*/false,
 742         /*IsStandalone=*/true,
 743         /*ShouldPrintRegisterTies=*/true,
 744         /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
 745 }
 746
 747 void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
 748                            LLT TypeToPrint, Optional<unsigned> OpIdx, bool PrintDef,
 749                            bool IsStandalone, bool ShouldPrintRegisterTies,
 750                            unsigned TiedOperandIdx,
 751                            const TargetRegisterInfo *TRI,
 752                            const TargetIntrinsicInfo *IntrinsicInfo) const {
 753   printTargetFlags(OS, *this);
 754   switch (getType()) {
 755   case MachineOperand::MO_Register: {
 756     Register Reg = getReg();
 757     if (isImplicit())
 758       OS << (isDef() ? "implicit-def " : "implicit ");
 759     else if (PrintDef && isDef())
 760       // Print the 'def' flag only when the operand is defined after '='.
 761       OS << "def ";
 762     if (isInternalRead())
 763       OS << "internal ";
 764     if (isDead())
 765       OS << "dead ";
 766     if (isKill())
 767       OS << "killed ";
 768     if (isUndef())
 769       OS << "undef ";
 770     if (isEarlyClobber())
 771       OS << "early-clobber ";
 772     if (Register::isPhysicalRegister(getReg()) && isRenamable())
 773       OS << "renamable ";
 774     // isDebug() is exactly true for register operands of a DBG_VALUE. So we
 775     // simply infer it when parsing and do not need to print it.
 776
 777     const MachineRegisterInfo *MRI = nullptr;
 778     if (Register::isVirtualRegister(Reg)) {
 779       if (const MachineFunction *MF = getMFIfAvailable(*this)) {
 780         MRI = &MF->getRegInfo();
 781       }
 782     }
 783
 784     OS << printReg(Reg, TRI, 0, MRI);
 785     // Print the sub register.
 786     if (unsigned SubReg = getSubReg()) {
 787       if (TRI)
 788         OS << '.' << TRI->getSubRegIndexName(SubReg);
 789       else
 790         OS << ".subreg" << SubReg;
 791     }
 792     // Print the register class / bank.
 793     if (Register::isVirtualRegister(Reg)) {
 794       if (const MachineFunction *MF = getMFIfAvailable(*this)) {
 795         const MachineRegisterInfo &MRI = MF->getRegInfo();
 796         if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
 797           OS << ':';
 798           OS << printRegClassOrBank(Reg, MRI, TRI);
 799         }
 800       }
 801     }
 802     // Print ties.
 803     if (ShouldPrintRegisterTies && isTied() && !isDef())
 804       OS << "(tied-def " << TiedOperandIdx << ")";
 805     // Print types.
 806     if (TypeToPrint.isValid())
 807       OS << '(' << TypeToPrint << ')';
 808     break;
 809   }
 810   case MachineOperand::MO_Immediate: {
 811     const MIRFormatter *Formatter = nullptr;
 812     if (const MachineFunction *MF = getMFIfAvailable(*this)) {
 813       const auto *TII = MF->getSubtarget().getInstrInfo();
 814       assert(TII && "expected instruction info");
 815       Formatter = TII->getMIRFormatter();
 816     }
 817     if (Formatter)
 818       Formatter->printImm(OS, *getParent(), OpIdx, getImm());
 819     else
 820       OS << getImm();
 821     break;
 822   }
 823   case MachineOperand::MO_CImmediate:
 824     getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
 825     break;
 826   case MachineOperand::MO_FPImmediate:
 827     getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
 828     break;
 829   case MachineOperand::MO_MachineBasicBlock:
 830     OS << printMBBReference(*getMBB());
 831     break;
 832   case MachineOperand::MO_FrameIndex: {
 833     int FrameIndex = getIndex();
 834     bool IsFixed = false;
 835     const MachineFrameInfo *MFI = nullptr;
 836     if (const MachineFunction *MF = getMFIfAvailable(*this))
 837       MFI = &MF->getFrameInfo();
 838     printFrameIndex(OS, FrameIndex, IsFixed, MFI);
 839     break;
 840   }
 841   case MachineOperand::MO_ConstantPoolIndex:
 842     OS << "%const." << getIndex();
 843     printOperandOffset(OS, getOffset());
 844     break;
 845   case MachineOperand::MO_TargetIndex: {
 846     OS << "target-index(";
 847     const char *Name = "<unknown>";
 848     if (const MachineFunction *MF = getMFIfAvailable(*this))
 849       if (const auto *TargetIndexName = ::getTargetIndexName(*MF, getIndex()))
 850         Name = TargetIndexName;
 851     OS << Name << ')';
 852     printOperandOffset(OS, getOffset());
 853     break;
 854   }
 855   case MachineOperand::MO_JumpTableIndex:
 856     OS << printJumpTableEntryReference(getIndex());
 857     break;
 858   case MachineOperand::MO_GlobalAddress:
 859     getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
 860     printOperandOffset(OS, getOffset());
 861     break;
 862   case MachineOperand::MO_ExternalSymbol: {
 863     StringRef Name = getSymbolName();
 864     OS << '&';
 865     if (Name.empty()) {
 866       OS << "\"\"";
 867     } else {
 868       printLLVMNameWithoutPrefix(OS, Name);
 869     }
 870     printOperandOffset(OS, getOffset());
 871     break;
 872   }
 873   case MachineOperand::MO_BlockAddress: {
 874     OS << "blockaddress(";
 875     getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
 876                                                      MST);
 877     OS << ", ";
 878     printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
 879     OS << ')';
 880     MachineOperand::printOperandOffset(OS, getOffset());
 881     break;
 882   }
 883   case MachineOperand::MO_RegisterMask: {
 884     OS << "<regmask";
 885     if (TRI) {
 886       unsigned NumRegsInMask = 0;
 887       unsigned NumRegsEmitted = 0;
 888       for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
 889         unsigned MaskWord = i / 32;
 890         unsigned MaskBit = i % 32;
 891         if (getRegMask()[MaskWord] & (1 << MaskBit)) {
 892           if (PrintRegMaskNumRegs < 0 ||
 893               NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
 894             OS << " " << printReg(i, TRI);
 895             NumRegsEmitted++;
 896           }
 897           NumRegsInMask++;
 898         }
 899       }
 900       if (NumRegsEmitted != NumRegsInMask)
 901         OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
 902     } else {
 903       OS << " ...";
 904     }
 905     OS << ">";
 906     break;
 907   }
 908   case MachineOperand::MO_RegisterLiveOut: {
 909     const uint32_t *RegMask = getRegLiveOut();
 910     OS << "liveout(";
 911     if (!TRI) {
 912       OS << "<unknown>";
 913     } else {
 914       bool IsCommaNeeded = false;
 915       for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
 916         if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
 917           if (IsCommaNeeded)
 918             OS << ", ";
 919           OS << printReg(Reg, TRI);
 920           IsCommaNeeded = true;
 921         }
 922       }
 923     }
 924     OS << ")";
 925     break;
 926   }
 927   case MachineOperand::MO_Metadata:
 928     getMetadata()->printAsOperand(OS, MST);
 929     break;
 930   case MachineOperand::MO_MCSymbol:
 931     printSymbol(OS, *getMCSymbol());
 932     break;
 933   case MachineOperand::MO_CFIIndex: {
 934     if (const MachineFunction *MF = getMFIfAvailable(*this))
 935       printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
 936     else
 937       OS << "<cfi directive>";
 938     break;
 939   }
 940   case MachineOperand::MO_IntrinsicID: {
 941     Intrinsic::ID ID = getIntrinsicID();
 942     if (ID < Intrinsic::num_intrinsics)
 943       OS << "intrinsic(@" << Intrinsic::getBaseName(ID) << ')';
 944     else if (IntrinsicInfo)
 945       OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
 946     else
 947       OS << "intrinsic(" << ID << ')';
 948     break;
 949   }
 950   case MachineOperand::MO_Predicate: {
 951     auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
 952     OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
 953        << CmpInst::getPredicateName(Pred) << ')';
 954     break;
 955   }
 956   case MachineOperand::MO_ShuffleMask:
 957     OS << "shufflemask(";
 958     ArrayRef<int> Mask = getShuffleMask();
 959     StringRef Separator;
 960     for (int Elt : Mask) {
 961       if (Elt == -1)
 962         OS << Separator << "undef";
 963       else
 964         OS << Separator << Elt;
 965       Separator = ", ";
 966     }
 967
 968     OS << ')';
 969     break;
 970   }
 971 }
 972
 973 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 974 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
 975 #endif
 976
 977 //===----------------------------------------------------------------------===//
 978 // MachineMemOperand Implementation
 979 //===----------------------------------------------------------------------===//
 980
 981 /// getAddrSpace - Return the LLVM IR address space number that this pointer
 982 /// points into.
 983 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
 984
 985 /// isDereferenceable - Return true if V is always dereferenceable for
 986 /// Offset + Size byte.
 987 bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
 988                                            const DataLayout &DL) const {
 989   if (!V.is<const Value *>())
 990     return false;
 991
 992   const Value *BasePtr = V.get<const Value *>();
 993   if (BasePtr == nullptr)
 994     return false;
 995
 996   return isDereferenceableAndAlignedPointer(
 997       BasePtr, Align(1), APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
 998 }
 999
1000 /// getConstantPool - Return a MachinePointerInfo record that refers to the
1001 /// constant pool.
1002 MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
1003   return MachinePointerInfo(MF.getPSVManager().getConstantPool());
1004 }
1005
1006 /// getFixedStack - Return a MachinePointerInfo record that refers to the
1007 /// the specified FrameIndex.
1008 MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
1009                                                      int FI, int64_t Offset) {
1010   return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
1011 }
1012
1013 MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
1014   return MachinePointerInfo(MF.getPSVManager().getJumpTable());
1015 }
1016
1017 MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
1018   return MachinePointerInfo(MF.getPSVManager().getGOT());
1019 }
1020
1021 MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
1022                                                 int64_t Offset, uint8_t ID) {
1023   return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID);
1024 }
1025
1026 MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) {
1027   return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace());
1028 }
1029
1030 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
1031                                      LLT type, Align a, const AAMDNodes &AAInfo,
1032                                      const MDNode *Ranges, SyncScope::ID SSID,
1033                                      AtomicOrdering Ordering,
1034                                      AtomicOrdering FailureOrdering)
1035     : PtrInfo(ptrinfo), MemoryType(type), FlagVals(f), BaseAlign(a),
1036       AAInfo(AAInfo), Ranges(Ranges) {
1037   assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
1038           isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
1039          "invalid pointer value");
1040   assert((isLoad() || isStore()) && "Not a load/store!");
1041
1042   AtomicInfo.SSID = static_cast<unsigned>(SSID);
1043   assert(getSyncScopeID() == SSID && "Value truncated");
1044   AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1045   assert(getSuccessOrdering() == Ordering && "Value truncated");
1046   AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1047   assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1048 }
1049
1050 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
1051                                      uint64_t s, Align a,
1052                                      const AAMDNodes &AAInfo,
1053                                      const MDNode *Ranges, SyncScope::ID SSID,
1054                                      AtomicOrdering Ordering,
1055                                      AtomicOrdering FailureOrdering)
1056     : MachineMemOperand(ptrinfo, f,
1057                         s == ~UINT64_C(0) ? LLT() : LLT::scalar(8 * s), a,
1058                         AAInfo, Ranges, SSID, Ordering, FailureOrdering) {}
1059
1060 /// Profile - Gather unique data for the object.
1061 ///
1062 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
1063   ID.AddInteger(getOffset());
1064   ID.AddInteger(getMemoryType().getUniqueRAWLLTData());
1065   ID.AddPointer(getOpaqueValue());
1066   ID.AddInteger(getFlags());
1067   ID.AddInteger(getBaseAlign().value());
1068 }
1069
1070 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
1071   // The Value and Offset may differ due to CSE. But the flags and size
1072   // should be the same.
1073   assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1074   assert((MMO->getSize() == ~UINT64_C(0) || getSize() == ~UINT64_C(0) ||
1075           MMO->getSize() == getSize()) &&
1076          "Size mismatch!");
1077
1078   if (MMO->getBaseAlign() >= getBaseAlign()) {
1079     // Update the alignment value.
1080     BaseAlign = MMO->getBaseAlign();
1081     // Also update the base and offset, because the new alignment may
1082     // not be applicable with the old ones.
1083     PtrInfo = MMO->PtrInfo;
1084   }
1085 }
1086
1087 /// getAlign - Return the minimum known alignment in bytes of the
1088 /// actual memory reference.
1089 Align MachineMemOperand::getAlign() const {
1090   return commonAlignment(getBaseAlign(), getOffset());
1091 }
1092
1093 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
1094                               SmallVectorImpl<StringRef> &SSNs,
1095                               const LLVMContext &Context,
1096                               const MachineFrameInfo *MFI,
1097                               const TargetInstrInfo *TII) const {
1098   OS << '(';
1099   if (isVolatile())
1100     OS << "volatile ";
1101   if (isNonTemporal())
1102     OS << "non-temporal ";
1103   if (isDereferenceable())
1104     OS << "dereferenceable ";
1105   if (isInvariant())
1106     OS << "invariant ";
1107   if (getFlags() & MachineMemOperand::MOTargetFlag1)
1108     OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag1)
1109        << "\" ";
1110   if (getFlags() & MachineMemOperand::MOTargetFlag2)
1111     OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag2)
1112        << "\" ";
1113   if (getFlags() & MachineMemOperand::MOTargetFlag3)
1114     OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag3)
1115        << "\" ";
1116
1117   assert((isLoad() || isStore()) &&
1118          "machine memory operand must be a load or store (or both)");
1119   if (isLoad())
1120     OS << "load ";
1121   if (isStore())
1122     OS << "store ";
1123
1124   printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1125
1126   if (getSuccessOrdering() != AtomicOrdering::NotAtomic)
1127     OS << toIRString(getSuccessOrdering()) << ' ';
1128   if (getFailureOrdering() != AtomicOrdering::NotAtomic)
1129     OS << toIRString(getFailureOrdering()) << ' ';
1130
1131   if (getMemoryType().isValid())
1132     OS << '(' << getMemoryType() << ')';
1133   else
1134     OS << "unknown-size";
1135
1136   if (const Value *Val = getValue()) {
1137     OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1138     MIRFormatter::printIRValue(OS, *Val, MST);
1139   } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1140     OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1141     assert(PVal && "Expected a pseudo source value");
1142     switch (PVal->kind()) {
1143     case PseudoSourceValue::Stack:
1144       OS << "stack";
1145       break;
1146     case PseudoSourceValue::GOT:
1147       OS << "got";
1148       break;
1149     case PseudoSourceValue::JumpTable:
1150       OS << "jump-table";
1151       break;
1152     case PseudoSourceValue::ConstantPool:
1153       OS << "constant-pool";
1154       break;
1155     case PseudoSourceValue::FixedStack: {
1156       int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1157       bool IsFixed = true;
1158       printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1159       break;
1160     }
1161     case PseudoSourceValue::GlobalValueCallEntry:
1162       OS << "call-entry ";
1163       cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1164           OS, /*PrintType=*/false, MST);
1165       break;
1166     case PseudoSourceValue::ExternalSymbolCallEntry:
1167       OS << "call-entry &";
1168       printLLVMNameWithoutPrefix(
1169           OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1170       break;
1171     default: {
1172       const MIRFormatter *Formatter = TII->getMIRFormatter();
1173       // FIXME: This is not necessarily the correct MIR serialization format for
1174       // a custom pseudo source value, but at least it allows
1175       // MIR printing to work on a target with custom pseudo source
1176       // values.
1177       OS << "custom \"";
1178       Formatter->printCustomPseudoSourceValue(OS, MST, *PVal);
1179       OS << '\"';
1180       break;
1181     }
1182     }
1183   } else if (getOpaqueValue() == nullptr && getOffset() != 0) {
1184     OS << ((isLoad() && isStore()) ? " on "
1185            : isLoad()              ? " from "
1186                                    : " into ")
1187        << "unknown-address";
1188   }
1189   MachineOperand::printOperandOffset(OS, getOffset());
1190   if (getSize() > 0 && getAlign() != getSize())
1191     OS << ", align " << getAlign().value();
1192   if (getAlign() != getBaseAlign())
1193     OS << ", basealign " << getBaseAlign().value();
1194   auto AAInfo = getAAInfo();
1195   if (AAInfo.TBAA) {
1196     OS << ", !tbaa ";
1197     AAInfo.TBAA->printAsOperand(OS, MST);
1198   }
1199   if (AAInfo.Scope) {
1200     OS << ", !alias.scope ";
1201     AAInfo.Scope->printAsOperand(OS, MST);
1202   }
1203   if (AAInfo.NoAlias) {
1204     OS << ", !noalias ";
1205     AAInfo.NoAlias->printAsOperand(OS, MST);
1206   }
1207   if (getRanges()) {
1208     OS << ", !range ";
1209     getRanges()->printAsOperand(OS, MST);
1210   }
1211   // FIXME: Implement addrspace printing/parsing in MIR.
1212   // For now, print this even though parsing it is not available in MIR.
1213   if (unsigned AS = getAddrSpace())
1214     OS << ", addrspace " << AS;
1215
1216   OS << ')';
1217 }