llvm/test/tools/llvm-mca/AArch64/Exynos/asimd-ld4.s

   1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
   2 # RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M3
   3 # RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M4
   4 # RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m5 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M5
   5
   6 ld4     {v0.s, v1.s, v2.s, v3.s}[0], [sp]
   7 ld4r    {v0.2s, v1.2s, v2.2s, v3.2s}, [sp]
   8 ld4     {v0.2s, v1.2s, v2.2s, v3.2s}, [sp]
   9
  10 ld4     {v0.d, v1.d, v2.d, v3.d}[0], [sp]
  11 ld4r    {v0.2d, v1.2d, v2.2d, v3.2d}, [sp]
  12 ld4     {v0.2d, v1.2d, v2.2d, v3.2d}, [sp]
  13
  14 ld4     {v0.s, v1.s, v2.s, v3.s}[0], [sp], #16
  15 ld4r    {v0.2s, v1.2s, v2.2s, v3.2s}, [sp], #16
  16 ld4     {v0.2s, v1.2s, v2.2s, v3.2s}, [sp], #32
  17
  18 ld4     {v0.d, v1.d, v2.d, v3.d}[0], [sp], #32
  19 ld4r    {v0.2d, v1.2d, v2.2d, v3.2d}, [sp], #32
  20 ld4     {v0.2d, v1.2d, v2.2d, v3.2d}, [sp], #64
  21
  22 ld4     {v0.s, v1.s, v2.s, v3.s}[0], [sp], x0
  23 ld4r    {v0.2s, v1.2s, v2.2s, v3.2s}, [sp], x0
  24 ld4     {v0.2s, v1.2s, v2.2s, v3.2s}, [sp], x0
  25
  26 ld4     {v0.d, v1.d, v2.d, v3.d}[0], [sp], x0
  27 ld4r    {v0.2d, v1.2d, v2.2d, v3.2d}, [sp], x0
  28 ld4     {v0.2d, v1.2d, v2.2d, v3.2d}, [sp], x0
  29
  30 # ALL:      Iterations:        100
  31 # ALL-NEXT: Instructions:      1800
  32
  33 # M3-NEXT:  Total Cycles:      15598
  34 # M4-NEXT:  Total Cycles:      13004
  35 # M5-NEXT:  Total Cycles:      14304
  36
  37 # ALL-NEXT: Total uOps:        9300
  38
  39 # ALL:      Dispatch Width:    6
  40
  41 # M3-NEXT:  uOps Per Cycle:    0.60
  42 # M3-NEXT:  IPC:               0.12
  43 # M3-NEXT:  Block RThroughput: 108.0
  44
  45 # M4-NEXT:  uOps Per Cycle:    0.72
  46 # M4-NEXT:  IPC:               0.14
  47 # M4-NEXT:  Block RThroughput: 61.5
  48
  49 # M5-NEXT:  uOps Per Cycle:    0.65
  50 # M5-NEXT:  IPC:               0.13
  51 # M5-NEXT:  Block RThroughput: 40.5
  52
  53 # ALL:      Instruction Info:
  54 # ALL-NEXT: [1]: #uOps
  55 # ALL-NEXT: [2]: Latency
  56 # ALL-NEXT: [3]: RThroughput
  57 # ALL-NEXT: [4]: MayLoad
  58 # ALL-NEXT: [5]: MayStore
  59 # ALL-NEXT: [6]: HasSideEffects (U)
  60
  61 # ALL:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
  62
  63 # M3-NEXT:   5      9     2.00    *                   ld4       { v0.s, v1.s, v2.s, v3.s }[0], [sp]
  64 # M3-NEXT:   4      6     2.00    *                   ld4r      { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
  65 # M3-NEXT:   4      14    12.00   *                   ld4       { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
  66 # M3-NEXT:   6      7     6.00    *                   ld4       { v0.d, v1.d, v2.d, v3.d }[0], [sp]
  67 # M3-NEXT:   4      6     2.00    *                   ld4r      { v0.2d, v1.2d, v2.2d, v3.2d }, [sp]
  68 # M3-NEXT:   4      14    12.00   *                   ld4       { v0.2d, v1.2d, v2.2d, v3.2d }, [sp]
  69 # M3-NEXT:   6      9     2.00    *                   ld4       { v0.s, v1.s, v2.s, v3.s }[0], [sp], #16
  70 # M3-NEXT:   5      6     2.00    *                   ld4r      { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], #16
  71 # M3-NEXT:   5      14    12.00   *                   ld4       { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], #32
  72 # M3-NEXT:   7      7     6.00    *                   ld4       { v0.d, v1.d, v2.d, v3.d }[0], [sp], #32
  73 # M3-NEXT:   5      6     2.00    *                   ld4r      { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], #32
  74 # M3-NEXT:   5      14    12.00   *                   ld4       { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], #64
  75 # M3-NEXT:   6      9     2.00    *                   ld4       { v0.s, v1.s, v2.s, v3.s }[0], [sp], x0
  76 # M3-NEXT:   5      6     2.00    *                   ld4r      { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x0
  77 # M3-NEXT:   5      14    12.00   *                   ld4       { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x0
  78 # M3-NEXT:   7      7     6.00    *                   ld4       { v0.d, v1.d, v2.d, v3.d }[0], [sp], x0
  79 # M3-NEXT:   5      6     2.00    *                   ld4r      { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], x0
  80 # M3-NEXT:   5      14    12.00   *                   ld4       { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], x0
  81
  82 # M4-NEXT:   5      7     2.00    *                   ld4       { v0.s, v1.s, v2.s, v3.s }[0], [sp]
  83 # M4-NEXT:   4      6     2.00    *                   ld4r      { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
  84 # M4-NEXT:   4      14    6.00    *                   ld4       { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
  85 # M4-NEXT:   6      7     3.00    *                   ld4       { v0.d, v1.d, v2.d, v3.d }[0], [sp]
  86 # M4-NEXT:   4      6     2.00    *                   ld4r      { v0.2d, v1.2d, v2.2d, v3.2d }, [sp]
  87 # M4-NEXT:   4      14    6.00    *                   ld4       { v0.2d, v1.2d, v2.2d, v3.2d }, [sp]
  88 # M4-NEXT:   6      7     2.00    *                   ld4       { v0.s, v1.s, v2.s, v3.s }[0], [sp], #16
  89 # M4-NEXT:   5      6     2.00    *                   ld4r      { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], #16
  90 # M4-NEXT:   5      14    6.00    *                   ld4       { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], #32
  91 # M4-NEXT:   7      7     3.00    *                   ld4       { v0.d, v1.d, v2.d, v3.d }[0], [sp], #32
  92 # M4-NEXT:   5      6     2.00    *                   ld4r      { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], #32
  93 # M4-NEXT:   5      14    6.00    *                   ld4       { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], #64
  94 # M4-NEXT:   6      7     2.00    *                   ld4       { v0.s, v1.s, v2.s, v3.s }[0], [sp], x0
  95 # M4-NEXT:   5      6     2.00    *                   ld4r      { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x0
  96 # M4-NEXT:   5      14    6.00    *                   ld4       { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x0
  97 # M4-NEXT:   7      7     3.00    *                   ld4       { v0.d, v1.d, v2.d, v3.d }[0], [sp], x0
  98 # M4-NEXT:   5      6     2.00    *                   ld4r      { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], x0
  99 # M4-NEXT:   5      14    6.00    *                   ld4       { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], x0
 100
 101 # M5-NEXT:   5      8     2.00    *                   ld4       { v0.s, v1.s, v2.s, v3.s }[0], [sp]
 102 # M5-NEXT:   4      7     2.00    *                   ld4r      { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
 103 # M5-NEXT:   4      15    4.00    *                   ld4       { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
 104 # M5-NEXT:   6      8     2.00    *                   ld4       { v0.d, v1.d, v2.d, v3.d }[0], [sp]
 105 # M5-NEXT:   4      7     2.00    *                   ld4r      { v0.2d, v1.2d, v2.2d, v3.2d }, [sp]
 106 # M5-NEXT:   4      15    4.00    *                   ld4       { v0.2d, v1.2d, v2.2d, v3.2d }, [sp]
 107 # M5-NEXT:   6      8     2.00    *                   ld4       { v0.s, v1.s, v2.s, v3.s }[0], [sp], #16
 108 # M5-NEXT:   5      7     2.00    *                   ld4r      { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], #16
 109 # M5-NEXT:   5      15    4.00    *                   ld4       { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], #32
 110 # M5-NEXT:   7      8     2.00    *                   ld4       { v0.d, v1.d, v2.d, v3.d }[0], [sp], #32
 111 # M5-NEXT:   5      7     2.00    *                   ld4r      { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], #32
 112 # M5-NEXT:   5      15    4.00    *                   ld4       { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], #64
 113 # M5-NEXT:   6      8     2.00    *                   ld4       { v0.s, v1.s, v2.s, v3.s }[0], [sp], x0
 114 # M5-NEXT:   5      7     2.00    *                   ld4r      { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x0
 115 # M5-NEXT:   5      15    4.00    *                   ld4       { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x0
 116 # M5-NEXT:   7      8     2.00    *                   ld4       { v0.d, v1.d, v2.d, v3.d }[0], [sp], x0
 117 # M5-NEXT:   5      7     2.00    *                   ld4r      { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], x0
 118 # M5-NEXT:   5      15    4.00    *                   ld4       { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], x0