llvm/test/tools/llvm-mca/AArch64/Exynos/shifted-register.s

   1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
   2 # RUN: llvm-mca -march=aarch64 -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM3
   3 # RUN: llvm-mca -march=aarch64 -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM4
   4 # RUN: llvm-mca -march=aarch64 -mcpu=exynos-m5 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM5
   5
   6   adds  w0, w1, w2, lsl #0
   7   sub   x3, x4, x5, lsr #1
   8   ands  x6, x7, x8, lsl #2
   9   orr   w9, w10, w11, asr #3
  10   adds  w12, w13, w14, lsl #4
  11   sub   x15, x16, x17, lsr #6
  12   ands  x18, x19, x20, lsl #8
  13   eor   w21, w22, w23, asr #10
  14
  15 # ALL:      Iterations:        100
  16 # ALL-NEXT: Instructions:      800
  17
  18 # EM3-NEXT: Total Cycles:      354
  19 # EM4-NEXT: Total Cycles:      329
  20 # EM5-NEXT: Total Cycles:      220
  21
  22 # ALL-NEXT: Total uOps:        800
  23
  24 # EM3:      Dispatch Width:    6
  25 # EM3-NEXT: uOps Per Cycle:    2.26
  26 # EM3-NEXT: IPC:               2.26
  27 # EM3-NEXT: Block RThroughput: 3.5
  28
  29 # EM4:      Dispatch Width:    6
  30 # EM4-NEXT: uOps Per Cycle:    2.43
  31 # EM4-NEXT: IPC:               2.43
  32 # EM4-NEXT: Block RThroughput: 3.3
  33
  34 # EM5:      Dispatch Width:    6
  35 # EM5-NEXT: uOps Per Cycle:    3.64
  36 # EM5-NEXT: IPC:               3.64
  37 # EM5-NEXT: Block RThroughput: 1.5
  38
  39 # ALL:      Instruction Info:
  40 # ALL-NEXT: [1]: #uOps
  41 # ALL-NEXT: [2]: Latency
  42 # ALL-NEXT: [3]: RThroughput
  43 # ALL-NEXT: [4]: MayLoad
  44 # ALL-NEXT: [5]: MayStore
  45 # ALL-NEXT: [6]: HasSideEffects (U)
  46
  47 # ALL:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
  48
  49 # EM3-NEXT:  1      1     0.25                        adds      w0, w1, w2
  50 # EM3-NEXT:  1      2     0.50                        sub       x3, x4, x5, lsr #1
  51 # EM3-NEXT:  1      1     0.25                        ands      x6, x7, x8, lsl #2
  52 # EM3-NEXT:  1      2     0.50                        orr       w9, w10, w11, asr #3
  53 # EM3-NEXT:  1      2     0.50                        adds      w12, w13, w14, lsl #4
  54 # EM3-NEXT:  1      2     0.50                        sub       x15, x16, x17, lsr #6
  55 # EM3-NEXT:  1      2     0.50                        ands      x18, x19, x20, lsl #8
  56 # EM3-NEXT:  1      2     0.50                        eor       w21, w22, w23, asr #10
  57
  58 # EM4-NEXT:  1      1     0.25                        adds      w0, w1, w2
  59 # EM4-NEXT:  1      2     0.50                        sub       x3, x4, x5, lsr #1
  60 # EM4-NEXT:  1      1     0.25                        ands      x6, x7, x8, lsl #2
  61 # EM4-NEXT:  1      2     0.50                        orr       w9, w10, w11, asr #3
  62 # EM4-NEXT:  1      2     0.50                        adds      w12, w13, w14, lsl #4
  63 # EM4-NEXT:  1      2     0.50                        sub       x15, x16, x17, lsr #6
  64 # EM4-NEXT:  1      1     0.25                        ands      x18, x19, x20, lsl #8
  65 # EM4-NEXT:  1      2     0.50                        eor       w21, w22, w23, asr #10
  66
  67 # EM5-NEXT:  1      1     0.17                        adds      w0, w1, w2
  68 # EM5-NEXT:  1      2     0.50                        sub       x3, x4, x5, lsr #1
  69 # EM5-NEXT:  1      1     0.25                        ands      x6, x7, x8, lsl #2
  70 # EM5-NEXT:  1      2     0.33                        orr       w9, w10, w11, asr #3
  71 # EM5-NEXT:  1      2     0.33                        adds      w12, w13, w14, lsl #4
  72 # EM5-NEXT:  1      2     0.50                        sub       x15, x16, x17, lsr #6
  73 # EM5-NEXT:  1      1     0.25                        ands      x18, x19, x20, lsl #8
  74 # EM5-NEXT:  1      2     0.33                        eor       w21, w22, w23, asr #10