[sanitizer] Improve FreeBSD ASLR detection
[llvm-project.git] / llvm / test / tools / llvm-mca / X86 / read-after-ld-1.s
blob118983e59ca25d5ebd8b752c19ca08820a00b720
1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=sandybridge -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefixes=ALL,SANDY
3 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefixes=ALL,HASWELL
4 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=broadwell -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefixes=ALL,BDWELL
5 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=skylake -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefixes=ALL,SKYLAKE
6 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=icelake-server -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefixes=ALL,SKYLAKE
7 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefixes=ALL,BARCELONA
8 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefixes=ALL,BDVER2
9 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefixes=ALL,BTVER2
10 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefixes=ALL,ZNVER1
11 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver2 -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefixes=ALL,ZNVER2
12 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefixes=ALL,ZNVER3
14 vdivps %xmm0, %xmm1, %xmm1
15 vaddps (%rax), %xmm1, %xmm1
17 # ALL: Iterations: 1
18 # ALL-NEXT: Instructions: 2
20 # BARCELONA-NEXT: Total Cycles: 20
21 # BARCELONA-NEXT: Total uOps: 3
23 # BDVER2-NEXT: Total Cycles: 17
24 # BDVER2-NEXT: Total uOps: 2
26 # BDWELL-NEXT: Total Cycles: 17
27 # BDWELL-NEXT: Total uOps: 3
29 # BTVER2-NEXT: Total Cycles: 25
30 # BTVER2-NEXT: Total uOps: 2
32 # HASWELL-NEXT: Total Cycles: 19
33 # HASWELL-NEXT: Total uOps: 3
35 # SANDY-NEXT: Total Cycles: 20
36 # SANDY-NEXT: Total uOps: 3
38 # SKYLAKE-NEXT: Total Cycles: 18
39 # SKYLAKE-NEXT: Total uOps: 3
41 # ZNVER1-NEXT: Total Cycles: 20
42 # ZNVER1-NEXT: Total uOps: 2
44 # ZNVER2-NEXT: Total Cycles: 21
45 # ZNVER2-NEXT: Total uOps: 2
47 # ZNVER3-NEXT: Total Cycles: 17
48 # ZNVER3-NEXT: Total uOps: 2
50 # BARCELONA: Dispatch Width: 4
51 # BARCELONA-NEXT: uOps Per Cycle: 0.15
52 # BARCELONA-NEXT: IPC: 0.10
53 # BARCELONA-NEXT: Block RThroughput: 14.0
55 # BDVER2: Dispatch Width: 4
56 # BDVER2-NEXT: uOps Per Cycle: 0.12
57 # BDVER2-NEXT: IPC: 0.12
58 # BDVER2-NEXT: Block RThroughput: 5.0
60 # BDWELL: Dispatch Width: 4
61 # BDWELL-NEXT: uOps Per Cycle: 0.18
62 # BDWELL-NEXT: IPC: 0.12
63 # BDWELL-NEXT: Block RThroughput: 5.0
65 # BTVER2: Dispatch Width: 2
66 # BTVER2-NEXT: uOps Per Cycle: 0.08
67 # BTVER2-NEXT: IPC: 0.08
68 # BTVER2-NEXT: Block RThroughput: 19.0
70 # HASWELL: Dispatch Width: 4
71 # HASWELL-NEXT: uOps Per Cycle: 0.16
72 # HASWELL-NEXT: IPC: 0.11
73 # HASWELL-NEXT: Block RThroughput: 7.0
75 # SANDY: Dispatch Width: 4
76 # SANDY-NEXT: uOps Per Cycle: 0.15
77 # SANDY-NEXT: IPC: 0.10
78 # SANDY-NEXT: Block RThroughput: 14.0
80 # SKYLAKE: Dispatch Width: 6
81 # SKYLAKE-NEXT: uOps Per Cycle: 0.17
82 # SKYLAKE-NEXT: IPC: 0.11
83 # SKYLAKE-NEXT: Block RThroughput: 3.0
85 # ZNVER1: Dispatch Width: 4
86 # ZNVER1-NEXT: uOps Per Cycle: 0.10
87 # ZNVER1-NEXT: IPC: 0.10
88 # ZNVER1-NEXT: Block RThroughput: 1.0
90 # ZNVER2: Dispatch Width: 4
91 # ZNVER2-NEXT: uOps Per Cycle: 0.10
92 # ZNVER2-NEXT: IPC: 0.10
93 # ZNVER2-NEXT: Block RThroughput: 1.0
95 # ZNVER3: Dispatch Width: 6
96 # ZNVER3-NEXT: uOps Per Cycle: 0.12
97 # ZNVER3-NEXT: IPC: 0.12
98 # ZNVER3-NEXT: Block RThroughput: 3.0
100 # ALL: Timeline view:
102 # BARCELONA-NEXT: 0123456789
103 # BARCELONA-NEXT: Index 0123456789
105 # BDVER2-NEXT: 0123456
106 # BDVER2-NEXT: Index 0123456789
108 # BDWELL-NEXT: 0123456
109 # BDWELL-NEXT: Index 0123456789
111 # BTVER2-NEXT: 0123456789
112 # BTVER2-NEXT: Index 0123456789 01234
114 # HASWELL-NEXT: 012345678
115 # HASWELL-NEXT: Index 0123456789
117 # SANDY-NEXT: 0123456789
118 # SANDY-NEXT: Index 0123456789
120 # SKYLAKE-NEXT: 01234567
121 # SKYLAKE-NEXT: Index 0123456789
123 # ZNVER1-NEXT: 0123456789
124 # ZNVER1-NEXT: Index 0123456789
126 # ZNVER2-NEXT: 0123456789
127 # ZNVER2-NEXT: Index 0123456789 0
129 # ZNVER3-NEXT: 0123456
130 # ZNVER3-NEXT: Index 0123456789
132 # BARCELONA: [0,0] DeeeeeeeeeeeeeeER . vdivps %xmm0, %xmm1, %xmm1
133 # BARCELONA-NEXT: [0,1] D========eeeeeeeeeER vaddps (%rax), %xmm1, %xmm1
135 # BDVER2: [0,0] DeeeeeeeeeER .. vdivps %xmm0, %xmm1, %xmm1
136 # BDVER2-NEXT: [0,1] D====eeeeeeeeeeER vaddps (%rax), %xmm1, %xmm1
138 # BDWELL: [0,0] DeeeeeeeeeeeER .. vdivps %xmm0, %xmm1, %xmm1
139 # BDWELL-NEXT: [0,1] D======eeeeeeeeER vaddps (%rax), %xmm1, %xmm1
141 # BTVER2: [0,0] DeeeeeeeeeeeeeeeeeeeER . vdivps %xmm0, %xmm1, %xmm1
142 # BTVER2-NEXT: [0,1] D==============eeeeeeeeER vaddps (%rax), %xmm1, %xmm1
144 # HASWELL: [0,0] DeeeeeeeeeeeeeER . vdivps %xmm0, %xmm1, %xmm1
145 # HASWELL-NEXT: [0,1] D=======eeeeeeeeeER vaddps (%rax), %xmm1, %xmm1
147 # SANDY: [0,0] DeeeeeeeeeeeeeeER . vdivps %xmm0, %xmm1, %xmm1
148 # SANDY-NEXT: [0,1] D========eeeeeeeeeER vaddps (%rax), %xmm1, %xmm1
150 # SKYLAKE: [0,0] DeeeeeeeeeeeER . . vdivps %xmm0, %xmm1, %xmm1
151 # SKYLAKE-NEXT: [0,1] D=====eeeeeeeeeeER vaddps (%rax), %xmm1, %xmm1
153 # ZNVER1: [0,0] DeeeeeeeeeeeeeeeER . vdivps %xmm0, %xmm1, %xmm1
154 # ZNVER1-NEXT: [0,1] D=======eeeeeeeeeeER vaddps (%rax), %xmm1, %xmm1
156 # ZNVER2: [0,0] DeeeeeeeeeeeeeeeER . vdivps %xmm0, %xmm1, %xmm1
157 # ZNVER2-NEXT: [0,1] D========eeeeeeeeeeER vaddps (%rax), %xmm1, %xmm1
159 # ZNVER3: [0,0] DeeeeeeeeeeeER .. vdivps %xmm0, %xmm1, %xmm1
160 # ZNVER3-NEXT: [0,1] D====eeeeeeeeeeER vaddps (%rax), %xmm1, %xmm1
162 # ALL: Average Wait times (based on the timeline view):
163 # ALL-NEXT: [0]: Executions
164 # ALL-NEXT: [1]: Average time spent waiting in a scheduler's queue
165 # ALL-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
166 # ALL-NEXT: [3]: Average time elapsed from WB until retire stage
168 # ALL: [0] [1] [2] [3]
169 # ALL-NEXT: 0. 1 1.0 1.0 0.0 vdivps %xmm0, %xmm1, %xmm1
171 # BARCELONA-NEXT: 1. 1 9.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1
172 # BARCELONA-NEXT: 1 5.0 0.5 0.0 <total>
174 # BDVER2-NEXT: 1. 1 5.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1
175 # BDVER2-NEXT: 1 3.0 0.5 0.0 <total>
177 # BDWELL-NEXT: 1. 1 7.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1
178 # BDWELL-NEXT: 1 4.0 0.5 0.0 <total>
180 # BTVER2-NEXT: 1. 1 15.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1
181 # BTVER2-NEXT: 1 8.0 0.5 0.0 <total>
183 # HASWELL-NEXT: 1. 1 8.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1
184 # HASWELL-NEXT: 1 4.5 0.5 0.0 <total>
186 # SANDY-NEXT: 1. 1 9.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1
187 # SANDY-NEXT: 1 5.0 0.5 0.0 <total>
189 # SKYLAKE-NEXT: 1. 1 6.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1
190 # SKYLAKE-NEXT: 1 3.5 0.5 0.0 <total>
192 # ZNVER1-NEXT: 1. 1 8.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1
193 # ZNVER1-NEXT: 1 4.5 0.5 0.0 <total>
195 # ZNVER2-NEXT: 1. 1 9.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1
196 # ZNVER2-NEXT: 1 5.0 0.5 0.0 <total>
198 # ZNVER3-NEXT: 1. 1 5.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1
199 # ZNVER3-NEXT: 1 3.0 0.5 0.0 <total>