| blob | 479664c6f5f62121869e7868fb0b44a1f10191dc |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-ZVE64X,RV32,RV32I
3 ; RUN: llc -mtriple=riscv64 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-ZVE64X,RV64,RV64I
4 ; RUN: llc -mtriple=riscv32 -mattr=+zve64f,+f -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-F,RV32,RV32F
5 ; RUN: llc -mtriple=riscv64 -mattr=+zve64f,+f -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-F,RV64,RV64F
6 ; RUN: llc -mtriple=riscv32 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-D,RV32,RV32D
7 ; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-D,RV64,RV64D
8 ; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
9 ; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
11 define <vscale x 1 x i8> @cttz_nxv1i8(<vscale x 1 x i8> %va) {
12 ; CHECK-ZVE64X-LABEL: cttz_nxv1i8:
13 ; CHECK-ZVE64X: # %bb.0:
14 ; CHECK-ZVE64X-NEXT: li a0, 1
15 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
16 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
17 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
18 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
19 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
20 ; CHECK-ZVE64X-NEXT: li a0, 85
21 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
22 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
23 ; CHECK-ZVE64X-NEXT: li a0, 51
24 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
25 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
26 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
27 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
28 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
29 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
30 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
31 ; CHECK-ZVE64X-NEXT: ret
32 ;
33 ; CHECK-F-LABEL: cttz_nxv1i8:
34 ; CHECK-F: # %bb.0:
35 ; CHECK-F-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
36 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
37 ; CHECK-F-NEXT: vand.vv v9, v8, v9
38 ; CHECK-F-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
39 ; CHECK-F-NEXT: vzext.vf2 v10, v9
40 ; CHECK-F-NEXT: vfwcvt.f.xu.v v9, v10
41 ; CHECK-F-NEXT: vnsrl.wi v9, v9, 23
42 ; CHECK-F-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
43 ; CHECK-F-NEXT: vnsrl.wi v9, v9, 0
44 ; CHECK-F-NEXT: li a0, 127
45 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
46 ; CHECK-F-NEXT: vsub.vx v8, v9, a0
47 ; CHECK-F-NEXT: vmerge.vim v8, v8, 8, v0
48 ; CHECK-F-NEXT: ret
49 ;
50 ; CHECK-D-LABEL: cttz_nxv1i8:
51 ; CHECK-D: # %bb.0:
52 ; CHECK-D-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
53 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
54 ; CHECK-D-NEXT: vand.vv v9, v8, v9
55 ; CHECK-D-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
56 ; CHECK-D-NEXT: vzext.vf2 v10, v9
57 ; CHECK-D-NEXT: vfwcvt.f.xu.v v9, v10
58 ; CHECK-D-NEXT: vnsrl.wi v9, v9, 23
59 ; CHECK-D-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
60 ; CHECK-D-NEXT: vnsrl.wi v9, v9, 0
61 ; CHECK-D-NEXT: li a0, 127
62 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
63 ; CHECK-D-NEXT: vsub.vx v8, v9, a0
64 ; CHECK-D-NEXT: vmerge.vim v8, v8, 8, v0
65 ; CHECK-D-NEXT: ret
66 ;
67 ; CHECK-ZVBB-LABEL: cttz_nxv1i8:
68 ; CHECK-ZVBB: # %bb.0:
69 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
70 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
71 ; CHECK-ZVBB-NEXT: ret
72 %a = call <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 false)
73 ret <vscale x 1 x i8> %a
74 }
75 declare <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8>, i1)
77 define <vscale x 2 x i8> @cttz_nxv2i8(<vscale x 2 x i8> %va) {
78 ; CHECK-ZVE64X-LABEL: cttz_nxv2i8:
79 ; CHECK-ZVE64X: # %bb.0:
80 ; CHECK-ZVE64X-NEXT: li a0, 1
81 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
82 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
83 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
84 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
85 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
86 ; CHECK-ZVE64X-NEXT: li a0, 85
87 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
88 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
89 ; CHECK-ZVE64X-NEXT: li a0, 51
90 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
91 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
92 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
93 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
94 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
95 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
96 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
97 ; CHECK-ZVE64X-NEXT: ret
98 ;
99 ; CHECK-F-LABEL: cttz_nxv2i8:
100 ; CHECK-F: # %bb.0:
101 ; CHECK-F-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
102 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
103 ; CHECK-F-NEXT: vand.vv v9, v8, v9
104 ; CHECK-F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
105 ; CHECK-F-NEXT: vzext.vf2 v10, v9
106 ; CHECK-F-NEXT: vfwcvt.f.xu.v v9, v10
107 ; CHECK-F-NEXT: vnsrl.wi v9, v9, 23
108 ; CHECK-F-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
109 ; CHECK-F-NEXT: vnsrl.wi v9, v9, 0
110 ; CHECK-F-NEXT: li a0, 127
111 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
112 ; CHECK-F-NEXT: vsub.vx v8, v9, a0
113 ; CHECK-F-NEXT: vmerge.vim v8, v8, 8, v0
114 ; CHECK-F-NEXT: ret
115 ;
116 ; CHECK-D-LABEL: cttz_nxv2i8:
117 ; CHECK-D: # %bb.0:
118 ; CHECK-D-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
119 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
120 ; CHECK-D-NEXT: vand.vv v9, v8, v9
121 ; CHECK-D-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
122 ; CHECK-D-NEXT: vzext.vf2 v10, v9
123 ; CHECK-D-NEXT: vfwcvt.f.xu.v v9, v10
124 ; CHECK-D-NEXT: vnsrl.wi v9, v9, 23
125 ; CHECK-D-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
126 ; CHECK-D-NEXT: vnsrl.wi v9, v9, 0
127 ; CHECK-D-NEXT: li a0, 127
128 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
129 ; CHECK-D-NEXT: vsub.vx v8, v9, a0
130 ; CHECK-D-NEXT: vmerge.vim v8, v8, 8, v0
131 ; CHECK-D-NEXT: ret
132 ;
133 ; CHECK-ZVBB-LABEL: cttz_nxv2i8:
134 ; CHECK-ZVBB: # %bb.0:
135 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
136 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
137 ; CHECK-ZVBB-NEXT: ret
138 %a = call <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 false)
139 ret <vscale x 2 x i8> %a
140 }
141 declare <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8>, i1)
143 define <vscale x 4 x i8> @cttz_nxv4i8(<vscale x 4 x i8> %va) {
144 ; CHECK-ZVE64X-LABEL: cttz_nxv4i8:
145 ; CHECK-ZVE64X: # %bb.0:
146 ; CHECK-ZVE64X-NEXT: li a0, 1
147 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
148 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
149 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
150 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
151 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
152 ; CHECK-ZVE64X-NEXT: li a0, 85
153 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
154 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
155 ; CHECK-ZVE64X-NEXT: li a0, 51
156 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
157 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
158 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
159 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
160 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
161 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
162 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
163 ; CHECK-ZVE64X-NEXT: ret
164 ;
165 ; CHECK-F-LABEL: cttz_nxv4i8:
166 ; CHECK-F: # %bb.0:
167 ; CHECK-F-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
168 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
169 ; CHECK-F-NEXT: vand.vv v9, v8, v9
170 ; CHECK-F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
171 ; CHECK-F-NEXT: vzext.vf2 v10, v9
172 ; CHECK-F-NEXT: vfwcvt.f.xu.v v12, v10
173 ; CHECK-F-NEXT: vnsrl.wi v9, v12, 23
174 ; CHECK-F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
175 ; CHECK-F-NEXT: vnsrl.wi v9, v9, 0
176 ; CHECK-F-NEXT: li a0, 127
177 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
178 ; CHECK-F-NEXT: vsub.vx v8, v9, a0
179 ; CHECK-F-NEXT: vmerge.vim v8, v8, 8, v0
180 ; CHECK-F-NEXT: ret
181 ;
182 ; CHECK-D-LABEL: cttz_nxv4i8:
183 ; CHECK-D: # %bb.0:
184 ; CHECK-D-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
185 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
186 ; CHECK-D-NEXT: vand.vv v9, v8, v9
187 ; CHECK-D-NEXT: vsetvli zero, zero, e16, m1, ta, ma
188 ; CHECK-D-NEXT: vzext.vf2 v10, v9
189 ; CHECK-D-NEXT: vfwcvt.f.xu.v v12, v10
190 ; CHECK-D-NEXT: vnsrl.wi v9, v12, 23
191 ; CHECK-D-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
192 ; CHECK-D-NEXT: vnsrl.wi v9, v9, 0
193 ; CHECK-D-NEXT: li a0, 127
194 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
195 ; CHECK-D-NEXT: vsub.vx v8, v9, a0
196 ; CHECK-D-NEXT: vmerge.vim v8, v8, 8, v0
197 ; CHECK-D-NEXT: ret
198 ;
199 ; CHECK-ZVBB-LABEL: cttz_nxv4i8:
200 ; CHECK-ZVBB: # %bb.0:
201 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
202 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
203 ; CHECK-ZVBB-NEXT: ret
204 %a = call <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 false)
205 ret <vscale x 4 x i8> %a
206 }
207 declare <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8>, i1)
209 define <vscale x 8 x i8> @cttz_nxv8i8(<vscale x 8 x i8> %va) {
210 ; CHECK-ZVE64X-LABEL: cttz_nxv8i8:
211 ; CHECK-ZVE64X: # %bb.0:
212 ; CHECK-ZVE64X-NEXT: li a0, 1
213 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, m1, ta, ma
214 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
215 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
216 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
217 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
218 ; CHECK-ZVE64X-NEXT: li a0, 85
219 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
220 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
221 ; CHECK-ZVE64X-NEXT: li a0, 51
222 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
223 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
224 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
225 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
226 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
227 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
228 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
229 ; CHECK-ZVE64X-NEXT: ret
230 ;
231 ; CHECK-F-LABEL: cttz_nxv8i8:
232 ; CHECK-F: # %bb.0:
233 ; CHECK-F-NEXT: vsetvli a0, zero, e8, m1, ta, ma
234 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
235 ; CHECK-F-NEXT: vand.vv v9, v8, v9
236 ; CHECK-F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
237 ; CHECK-F-NEXT: vzext.vf2 v10, v9
238 ; CHECK-F-NEXT: vfwcvt.f.xu.v v12, v10
239 ; CHECK-F-NEXT: vnsrl.wi v10, v12, 23
240 ; CHECK-F-NEXT: vsetvli zero, zero, e8, m1, ta, ma
241 ; CHECK-F-NEXT: vnsrl.wi v9, v10, 0
242 ; CHECK-F-NEXT: li a0, 127
243 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
244 ; CHECK-F-NEXT: vsub.vx v8, v9, a0
245 ; CHECK-F-NEXT: vmerge.vim v8, v8, 8, v0
246 ; CHECK-F-NEXT: ret
247 ;
248 ; CHECK-D-LABEL: cttz_nxv8i8:
249 ; CHECK-D: # %bb.0:
250 ; CHECK-D-NEXT: vsetvli a0, zero, e8, m1, ta, ma
251 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
252 ; CHECK-D-NEXT: vand.vv v9, v8, v9
253 ; CHECK-D-NEXT: vsetvli zero, zero, e16, m2, ta, ma
254 ; CHECK-D-NEXT: vzext.vf2 v10, v9
255 ; CHECK-D-NEXT: vfwcvt.f.xu.v v12, v10
256 ; CHECK-D-NEXT: vnsrl.wi v10, v12, 23
257 ; CHECK-D-NEXT: vsetvli zero, zero, e8, m1, ta, ma
258 ; CHECK-D-NEXT: vnsrl.wi v9, v10, 0
259 ; CHECK-D-NEXT: li a0, 127
260 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
261 ; CHECK-D-NEXT: vsub.vx v8, v9, a0
262 ; CHECK-D-NEXT: vmerge.vim v8, v8, 8, v0
263 ; CHECK-D-NEXT: ret
264 ;
265 ; CHECK-ZVBB-LABEL: cttz_nxv8i8:
266 ; CHECK-ZVBB: # %bb.0:
267 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
268 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
269 ; CHECK-ZVBB-NEXT: ret
270 %a = call <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 false)
271 ret <vscale x 8 x i8> %a
272 }
273 declare <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8>, i1)
275 define <vscale x 16 x i8> @cttz_nxv16i8(<vscale x 16 x i8> %va) {
276 ; CHECK-ZVE64X-LABEL: cttz_nxv16i8:
277 ; CHECK-ZVE64X: # %bb.0:
278 ; CHECK-ZVE64X-NEXT: li a0, 1
279 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, m2, ta, ma
280 ; CHECK-ZVE64X-NEXT: vsub.vx v10, v8, a0
281 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
282 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v10
283 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
284 ; CHECK-ZVE64X-NEXT: li a0, 85
285 ; CHECK-ZVE64X-NEXT: vand.vx v10, v10, a0
286 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v10
287 ; CHECK-ZVE64X-NEXT: li a0, 51
288 ; CHECK-ZVE64X-NEXT: vand.vx v10, v8, a0
289 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
290 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
291 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v10, v8
292 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 4
293 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v10
294 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
295 ; CHECK-ZVE64X-NEXT: ret
296 ;
297 ; CHECK-F-LABEL: cttz_nxv16i8:
298 ; CHECK-F: # %bb.0:
299 ; CHECK-F-NEXT: vsetvli a0, zero, e8, m2, ta, ma
300 ; CHECK-F-NEXT: vrsub.vi v10, v8, 0
301 ; CHECK-F-NEXT: vand.vv v10, v8, v10
302 ; CHECK-F-NEXT: vsetvli zero, zero, e16, m4, ta, ma
303 ; CHECK-F-NEXT: vzext.vf2 v12, v10
304 ; CHECK-F-NEXT: vfwcvt.f.xu.v v16, v12
305 ; CHECK-F-NEXT: vnsrl.wi v12, v16, 23
306 ; CHECK-F-NEXT: vsetvli zero, zero, e8, m2, ta, ma
307 ; CHECK-F-NEXT: vnsrl.wi v10, v12, 0
308 ; CHECK-F-NEXT: li a0, 127
309 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
310 ; CHECK-F-NEXT: vsub.vx v8, v10, a0
311 ; CHECK-F-NEXT: vmerge.vim v8, v8, 8, v0
312 ; CHECK-F-NEXT: ret
313 ;
314 ; CHECK-D-LABEL: cttz_nxv16i8:
315 ; CHECK-D: # %bb.0:
316 ; CHECK-D-NEXT: vsetvli a0, zero, e8, m2, ta, ma
317 ; CHECK-D-NEXT: vrsub.vi v10, v8, 0
318 ; CHECK-D-NEXT: vand.vv v10, v8, v10
319 ; CHECK-D-NEXT: vsetvli zero, zero, e16, m4, ta, ma
320 ; CHECK-D-NEXT: vzext.vf2 v12, v10
321 ; CHECK-D-NEXT: vfwcvt.f.xu.v v16, v12
322 ; CHECK-D-NEXT: vnsrl.wi v12, v16, 23
323 ; CHECK-D-NEXT: vsetvli zero, zero, e8, m2, ta, ma
324 ; CHECK-D-NEXT: vnsrl.wi v10, v12, 0
325 ; CHECK-D-NEXT: li a0, 127
326 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
327 ; CHECK-D-NEXT: vsub.vx v8, v10, a0
328 ; CHECK-D-NEXT: vmerge.vim v8, v8, 8, v0
329 ; CHECK-D-NEXT: ret
330 ;
331 ; CHECK-ZVBB-LABEL: cttz_nxv16i8:
332 ; CHECK-ZVBB: # %bb.0:
333 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
334 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
335 ; CHECK-ZVBB-NEXT: ret
336 %a = call <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 false)
337 ret <vscale x 16 x i8> %a
338 }
339 declare <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8>, i1)
341 define <vscale x 32 x i8> @cttz_nxv32i8(<vscale x 32 x i8> %va) {
342 ; CHECK-LABEL: cttz_nxv32i8:
343 ; CHECK: # %bb.0:
344 ; CHECK-NEXT: li a0, 1
345 ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
346 ; CHECK-NEXT: vsub.vx v12, v8, a0
347 ; CHECK-NEXT: vnot.v v8, v8
348 ; CHECK-NEXT: vand.vv v8, v8, v12
349 ; CHECK-NEXT: vsrl.vi v12, v8, 1
350 ; CHECK-NEXT: li a0, 85
351 ; CHECK-NEXT: vand.vx v12, v12, a0
352 ; CHECK-NEXT: vsub.vv v8, v8, v12
353 ; CHECK-NEXT: li a0, 51
354 ; CHECK-NEXT: vand.vx v12, v8, a0
355 ; CHECK-NEXT: vsrl.vi v8, v8, 2
356 ; CHECK-NEXT: vand.vx v8, v8, a0
357 ; CHECK-NEXT: vadd.vv v8, v12, v8
358 ; CHECK-NEXT: vsrl.vi v12, v8, 4
359 ; CHECK-NEXT: vadd.vv v8, v8, v12
360 ; CHECK-NEXT: vand.vi v8, v8, 15
361 ; CHECK-NEXT: ret
362 ;
363 ; CHECK-ZVBB-LABEL: cttz_nxv32i8:
364 ; CHECK-ZVBB: # %bb.0:
365 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m4, ta, ma
366 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
367 ; CHECK-ZVBB-NEXT: ret
368 %a = call <vscale x 32 x i8> @llvm.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 false)
369 ret <vscale x 32 x i8> %a
370 }
371 declare <vscale x 32 x i8> @llvm.cttz.nxv32i8(<vscale x 32 x i8>, i1)
373 define <vscale x 64 x i8> @cttz_nxv64i8(<vscale x 64 x i8> %va) {
374 ; CHECK-LABEL: cttz_nxv64i8:
375 ; CHECK: # %bb.0:
376 ; CHECK-NEXT: li a0, 1
377 ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
378 ; CHECK-NEXT: vsub.vx v16, v8, a0
379 ; CHECK-NEXT: vnot.v v8, v8
380 ; CHECK-NEXT: vand.vv v8, v8, v16
381 ; CHECK-NEXT: vsrl.vi v16, v8, 1
382 ; CHECK-NEXT: li a0, 85
383 ; CHECK-NEXT: vand.vx v16, v16, a0
384 ; CHECK-NEXT: vsub.vv v8, v8, v16
385 ; CHECK-NEXT: li a0, 51
386 ; CHECK-NEXT: vand.vx v16, v8, a0
387 ; CHECK-NEXT: vsrl.vi v8, v8, 2
388 ; CHECK-NEXT: vand.vx v8, v8, a0
389 ; CHECK-NEXT: vadd.vv v8, v16, v8
390 ; CHECK-NEXT: vsrl.vi v16, v8, 4
391 ; CHECK-NEXT: vadd.vv v8, v8, v16
392 ; CHECK-NEXT: vand.vi v8, v8, 15
393 ; CHECK-NEXT: ret
394 ;
395 ; CHECK-ZVBB-LABEL: cttz_nxv64i8:
396 ; CHECK-ZVBB: # %bb.0:
397 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m8, ta, ma
398 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
399 ; CHECK-ZVBB-NEXT: ret
400 %a = call <vscale x 64 x i8> @llvm.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 false)
401 ret <vscale x 64 x i8> %a
402 }
403 declare <vscale x 64 x i8> @llvm.cttz.nxv64i8(<vscale x 64 x i8>, i1)
405 define <vscale x 1 x i16> @cttz_nxv1i16(<vscale x 1 x i16> %va) {
406 ; CHECK-ZVE64X-LABEL: cttz_nxv1i16:
407 ; CHECK-ZVE64X: # %bb.0:
408 ; CHECK-ZVE64X-NEXT: li a0, 1
409 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
410 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
411 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
412 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
413 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
414 ; CHECK-ZVE64X-NEXT: lui a0, 5
415 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
416 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
417 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
418 ; CHECK-ZVE64X-NEXT: lui a0, 3
419 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
420 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
421 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
422 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
423 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
424 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
425 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
426 ; CHECK-ZVE64X-NEXT: lui a0, 1
427 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
428 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
429 ; CHECK-ZVE64X-NEXT: li a0, 257
430 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
431 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
432 ; CHECK-ZVE64X-NEXT: ret
433 ;
434 ; CHECK-F-LABEL: cttz_nxv1i16:
435 ; CHECK-F: # %bb.0:
436 ; CHECK-F-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
437 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
438 ; CHECK-F-NEXT: vand.vv v9, v8, v9
439 ; CHECK-F-NEXT: vfwcvt.f.xu.v v10, v9
440 ; CHECK-F-NEXT: vnsrl.wi v9, v10, 23
441 ; CHECK-F-NEXT: li a0, 127
442 ; CHECK-F-NEXT: vsub.vx v9, v9, a0
443 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
444 ; CHECK-F-NEXT: li a0, 16
445 ; CHECK-F-NEXT: vmerge.vxm v8, v9, a0, v0
446 ; CHECK-F-NEXT: ret
447 ;
448 ; CHECK-D-LABEL: cttz_nxv1i16:
449 ; CHECK-D: # %bb.0:
450 ; CHECK-D-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
451 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
452 ; CHECK-D-NEXT: vand.vv v9, v8, v9
453 ; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v9
454 ; CHECK-D-NEXT: vnsrl.wi v9, v10, 23
455 ; CHECK-D-NEXT: li a0, 127
456 ; CHECK-D-NEXT: vsub.vx v9, v9, a0
457 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
458 ; CHECK-D-NEXT: li a0, 16
459 ; CHECK-D-NEXT: vmerge.vxm v8, v9, a0, v0
460 ; CHECK-D-NEXT: ret
461 ;
462 ; CHECK-ZVBB-LABEL: cttz_nxv1i16:
463 ; CHECK-ZVBB: # %bb.0:
464 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
465 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
466 ; CHECK-ZVBB-NEXT: ret
467 %a = call <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 false)
468 ret <vscale x 1 x i16> %a
469 }
470 declare <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16>, i1)
472 define <vscale x 2 x i16> @cttz_nxv2i16(<vscale x 2 x i16> %va) {
473 ; CHECK-ZVE64X-LABEL: cttz_nxv2i16:
474 ; CHECK-ZVE64X: # %bb.0:
475 ; CHECK-ZVE64X-NEXT: li a0, 1
476 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
477 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
478 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
479 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
480 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
481 ; CHECK-ZVE64X-NEXT: lui a0, 5
482 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
483 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
484 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
485 ; CHECK-ZVE64X-NEXT: lui a0, 3
486 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
487 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
488 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
489 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
490 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
491 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
492 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
493 ; CHECK-ZVE64X-NEXT: lui a0, 1
494 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
495 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
496 ; CHECK-ZVE64X-NEXT: li a0, 257
497 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
498 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
499 ; CHECK-ZVE64X-NEXT: ret
500 ;
501 ; CHECK-F-LABEL: cttz_nxv2i16:
502 ; CHECK-F: # %bb.0:
503 ; CHECK-F-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
504 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
505 ; CHECK-F-NEXT: vand.vv v9, v8, v9
506 ; CHECK-F-NEXT: vfwcvt.f.xu.v v10, v9
507 ; CHECK-F-NEXT: vnsrl.wi v9, v10, 23
508 ; CHECK-F-NEXT: li a0, 127
509 ; CHECK-F-NEXT: vsub.vx v9, v9, a0
510 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
511 ; CHECK-F-NEXT: li a0, 16
512 ; CHECK-F-NEXT: vmerge.vxm v8, v9, a0, v0
513 ; CHECK-F-NEXT: ret
514 ;
515 ; CHECK-D-LABEL: cttz_nxv2i16:
516 ; CHECK-D: # %bb.0:
517 ; CHECK-D-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
518 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
519 ; CHECK-D-NEXT: vand.vv v9, v8, v9
520 ; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v9
521 ; CHECK-D-NEXT: vnsrl.wi v9, v10, 23
522 ; CHECK-D-NEXT: li a0, 127
523 ; CHECK-D-NEXT: vsub.vx v9, v9, a0
524 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
525 ; CHECK-D-NEXT: li a0, 16
526 ; CHECK-D-NEXT: vmerge.vxm v8, v9, a0, v0
527 ; CHECK-D-NEXT: ret
528 ;
529 ; CHECK-ZVBB-LABEL: cttz_nxv2i16:
530 ; CHECK-ZVBB: # %bb.0:
531 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
532 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
533 ; CHECK-ZVBB-NEXT: ret
534 %a = call <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 false)
535 ret <vscale x 2 x i16> %a
536 }
537 declare <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16>, i1)
539 define <vscale x 4 x i16> @cttz_nxv4i16(<vscale x 4 x i16> %va) {
540 ; CHECK-ZVE64X-LABEL: cttz_nxv4i16:
541 ; CHECK-ZVE64X: # %bb.0:
542 ; CHECK-ZVE64X-NEXT: li a0, 1
543 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, m1, ta, ma
544 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
545 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
546 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
547 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
548 ; CHECK-ZVE64X-NEXT: lui a0, 5
549 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
550 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
551 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
552 ; CHECK-ZVE64X-NEXT: lui a0, 3
553 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
554 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
555 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
556 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
557 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
558 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
559 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
560 ; CHECK-ZVE64X-NEXT: lui a0, 1
561 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
562 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
563 ; CHECK-ZVE64X-NEXT: li a0, 257
564 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
565 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
566 ; CHECK-ZVE64X-NEXT: ret
567 ;
568 ; CHECK-F-LABEL: cttz_nxv4i16:
569 ; CHECK-F: # %bb.0:
570 ; CHECK-F-NEXT: vsetvli a0, zero, e16, m1, ta, ma
571 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
572 ; CHECK-F-NEXT: vand.vv v9, v8, v9
573 ; CHECK-F-NEXT: vfwcvt.f.xu.v v10, v9
574 ; CHECK-F-NEXT: vnsrl.wi v9, v10, 23
575 ; CHECK-F-NEXT: li a0, 127
576 ; CHECK-F-NEXT: vsub.vx v9, v9, a0
577 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
578 ; CHECK-F-NEXT: li a0, 16
579 ; CHECK-F-NEXT: vmerge.vxm v8, v9, a0, v0
580 ; CHECK-F-NEXT: ret
581 ;
582 ; CHECK-D-LABEL: cttz_nxv4i16:
583 ; CHECK-D: # %bb.0:
584 ; CHECK-D-NEXT: vsetvli a0, zero, e16, m1, ta, ma
585 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
586 ; CHECK-D-NEXT: vand.vv v9, v8, v9
587 ; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v9
588 ; CHECK-D-NEXT: vnsrl.wi v9, v10, 23
589 ; CHECK-D-NEXT: li a0, 127
590 ; CHECK-D-NEXT: vsub.vx v9, v9, a0
591 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
592 ; CHECK-D-NEXT: li a0, 16
593 ; CHECK-D-NEXT: vmerge.vxm v8, v9, a0, v0
594 ; CHECK-D-NEXT: ret
595 ;
596 ; CHECK-ZVBB-LABEL: cttz_nxv4i16:
597 ; CHECK-ZVBB: # %bb.0:
598 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
599 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
600 ; CHECK-ZVBB-NEXT: ret
601 %a = call <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 false)
602 ret <vscale x 4 x i16> %a
603 }
604 declare <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16>, i1)
606 define <vscale x 8 x i16> @cttz_nxv8i16(<vscale x 8 x i16> %va) {
607 ; CHECK-ZVE64X-LABEL: cttz_nxv8i16:
608 ; CHECK-ZVE64X: # %bb.0:
609 ; CHECK-ZVE64X-NEXT: li a0, 1
610 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, m2, ta, ma
611 ; CHECK-ZVE64X-NEXT: vsub.vx v10, v8, a0
612 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
613 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v10
614 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
615 ; CHECK-ZVE64X-NEXT: lui a0, 5
616 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
617 ; CHECK-ZVE64X-NEXT: vand.vx v10, v10, a0
618 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v10
619 ; CHECK-ZVE64X-NEXT: lui a0, 3
620 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
621 ; CHECK-ZVE64X-NEXT: vand.vx v10, v8, a0
622 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
623 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
624 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v10, v8
625 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 4
626 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v10
627 ; CHECK-ZVE64X-NEXT: lui a0, 1
628 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
629 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
630 ; CHECK-ZVE64X-NEXT: li a0, 257
631 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
632 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
633 ; CHECK-ZVE64X-NEXT: ret
634 ;
635 ; CHECK-F-LABEL: cttz_nxv8i16:
636 ; CHECK-F: # %bb.0:
637 ; CHECK-F-NEXT: vsetvli a0, zero, e16, m2, ta, ma
638 ; CHECK-F-NEXT: vrsub.vi v10, v8, 0
639 ; CHECK-F-NEXT: vand.vv v10, v8, v10
640 ; CHECK-F-NEXT: vfwcvt.f.xu.v v12, v10
641 ; CHECK-F-NEXT: vnsrl.wi v10, v12, 23
642 ; CHECK-F-NEXT: li a0, 127
643 ; CHECK-F-NEXT: vsub.vx v10, v10, a0
644 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
645 ; CHECK-F-NEXT: li a0, 16
646 ; CHECK-F-NEXT: vmerge.vxm v8, v10, a0, v0
647 ; CHECK-F-NEXT: ret
648 ;
649 ; CHECK-D-LABEL: cttz_nxv8i16:
650 ; CHECK-D: # %bb.0:
651 ; CHECK-D-NEXT: vsetvli a0, zero, e16, m2, ta, ma
652 ; CHECK-D-NEXT: vrsub.vi v10, v8, 0
653 ; CHECK-D-NEXT: vand.vv v10, v8, v10
654 ; CHECK-D-NEXT: vfwcvt.f.xu.v v12, v10
655 ; CHECK-D-NEXT: vnsrl.wi v10, v12, 23
656 ; CHECK-D-NEXT: li a0, 127
657 ; CHECK-D-NEXT: vsub.vx v10, v10, a0
658 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
659 ; CHECK-D-NEXT: li a0, 16
660 ; CHECK-D-NEXT: vmerge.vxm v8, v10, a0, v0
661 ; CHECK-D-NEXT: ret
662 ;
663 ; CHECK-ZVBB-LABEL: cttz_nxv8i16:
664 ; CHECK-ZVBB: # %bb.0:
665 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma
666 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
667 ; CHECK-ZVBB-NEXT: ret
668 %a = call <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 false)
669 ret <vscale x 8 x i16> %a
670 }
671 declare <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16>, i1)
673 define <vscale x 16 x i16> @cttz_nxv16i16(<vscale x 16 x i16> %va) {
674 ; CHECK-ZVE64X-LABEL: cttz_nxv16i16:
675 ; CHECK-ZVE64X: # %bb.0:
676 ; CHECK-ZVE64X-NEXT: li a0, 1
677 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, m4, ta, ma
678 ; CHECK-ZVE64X-NEXT: vsub.vx v12, v8, a0
679 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
680 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v12
681 ; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 1
682 ; CHECK-ZVE64X-NEXT: lui a0, 5
683 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
684 ; CHECK-ZVE64X-NEXT: vand.vx v12, v12, a0
685 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v12
686 ; CHECK-ZVE64X-NEXT: lui a0, 3
687 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
688 ; CHECK-ZVE64X-NEXT: vand.vx v12, v8, a0
689 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
690 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
691 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v12, v8
692 ; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 4
693 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v12
694 ; CHECK-ZVE64X-NEXT: lui a0, 1
695 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
696 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
697 ; CHECK-ZVE64X-NEXT: li a0, 257
698 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
699 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
700 ; CHECK-ZVE64X-NEXT: ret
701 ;
702 ; CHECK-F-LABEL: cttz_nxv16i16:
703 ; CHECK-F: # %bb.0:
704 ; CHECK-F-NEXT: vsetvli a0, zero, e16, m4, ta, ma
705 ; CHECK-F-NEXT: vrsub.vi v12, v8, 0
706 ; CHECK-F-NEXT: vand.vv v12, v8, v12
707 ; CHECK-F-NEXT: vfwcvt.f.xu.v v16, v12
708 ; CHECK-F-NEXT: vnsrl.wi v12, v16, 23
709 ; CHECK-F-NEXT: li a0, 127
710 ; CHECK-F-NEXT: vsub.vx v12, v12, a0
711 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
712 ; CHECK-F-NEXT: li a0, 16
713 ; CHECK-F-NEXT: vmerge.vxm v8, v12, a0, v0
714 ; CHECK-F-NEXT: ret
715 ;
716 ; CHECK-D-LABEL: cttz_nxv16i16:
717 ; CHECK-D: # %bb.0:
718 ; CHECK-D-NEXT: vsetvli a0, zero, e16, m4, ta, ma
719 ; CHECK-D-NEXT: vrsub.vi v12, v8, 0
720 ; CHECK-D-NEXT: vand.vv v12, v8, v12
721 ; CHECK-D-NEXT: vfwcvt.f.xu.v v16, v12
722 ; CHECK-D-NEXT: vnsrl.wi v12, v16, 23
723 ; CHECK-D-NEXT: li a0, 127
724 ; CHECK-D-NEXT: vsub.vx v12, v12, a0
725 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
726 ; CHECK-D-NEXT: li a0, 16
727 ; CHECK-D-NEXT: vmerge.vxm v8, v12, a0, v0
728 ; CHECK-D-NEXT: ret
729 ;
730 ; CHECK-ZVBB-LABEL: cttz_nxv16i16:
731 ; CHECK-ZVBB: # %bb.0:
732 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma
733 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
734 ; CHECK-ZVBB-NEXT: ret
735 %a = call <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 false)
736 ret <vscale x 16 x i16> %a
737 }
738 declare <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16>, i1)
740 define <vscale x 32 x i16> @cttz_nxv32i16(<vscale x 32 x i16> %va) {
741 ; CHECK-LABEL: cttz_nxv32i16:
742 ; CHECK: # %bb.0:
743 ; CHECK-NEXT: li a0, 1
744 ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
745 ; CHECK-NEXT: vsub.vx v16, v8, a0
746 ; CHECK-NEXT: vnot.v v8, v8
747 ; CHECK-NEXT: vand.vv v8, v8, v16
748 ; CHECK-NEXT: vsrl.vi v16, v8, 1
749 ; CHECK-NEXT: lui a0, 5
750 ; CHECK-NEXT: addi a0, a0, 1365
751 ; CHECK-NEXT: vand.vx v16, v16, a0
752 ; CHECK-NEXT: vsub.vv v8, v8, v16
753 ; CHECK-NEXT: lui a0, 3
754 ; CHECK-NEXT: addi a0, a0, 819
755 ; CHECK-NEXT: vand.vx v16, v8, a0
756 ; CHECK-NEXT: vsrl.vi v8, v8, 2
757 ; CHECK-NEXT: vand.vx v8, v8, a0
758 ; CHECK-NEXT: vadd.vv v8, v16, v8
759 ; CHECK-NEXT: vsrl.vi v16, v8, 4
760 ; CHECK-NEXT: vadd.vv v8, v8, v16
761 ; CHECK-NEXT: lui a0, 1
762 ; CHECK-NEXT: addi a0, a0, -241
763 ; CHECK-NEXT: vand.vx v8, v8, a0
764 ; CHECK-NEXT: li a0, 257
765 ; CHECK-NEXT: vmul.vx v8, v8, a0
766 ; CHECK-NEXT: vsrl.vi v8, v8, 8
767 ; CHECK-NEXT: ret
768 ;
769 ; CHECK-ZVBB-LABEL: cttz_nxv32i16:
770 ; CHECK-ZVBB: # %bb.0:
771 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m8, ta, ma
772 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
773 ; CHECK-ZVBB-NEXT: ret
774 %a = call <vscale x 32 x i16> @llvm.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 false)
775 ret <vscale x 32 x i16> %a
776 }
777 declare <vscale x 32 x i16> @llvm.cttz.nxv32i16(<vscale x 32 x i16>, i1)
779 define <vscale x 1 x i32> @cttz_nxv1i32(<vscale x 1 x i32> %va) {
780 ; CHECK-ZVE64X-LABEL: cttz_nxv1i32:
781 ; CHECK-ZVE64X: # %bb.0:
782 ; CHECK-ZVE64X-NEXT: li a0, 1
783 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
784 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
785 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
786 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
787 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
788 ; CHECK-ZVE64X-NEXT: lui a0, 349525
789 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
790 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
791 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
792 ; CHECK-ZVE64X-NEXT: lui a0, 209715
793 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
794 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
795 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
796 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
797 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
798 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
799 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
800 ; CHECK-ZVE64X-NEXT: lui a0, 61681
801 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
802 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
803 ; CHECK-ZVE64X-NEXT: lui a0, 4112
804 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
805 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
806 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
807 ; CHECK-ZVE64X-NEXT: ret
808 ;
809 ; CHECK-F-LABEL: cttz_nxv1i32:
810 ; CHECK-F: # %bb.0:
811 ; CHECK-F-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
812 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
813 ; CHECK-F-NEXT: vand.vv v9, v8, v9
814 ; CHECK-F-NEXT: fsrmi a0, 1
815 ; CHECK-F-NEXT: vfcvt.f.xu.v v9, v9
816 ; CHECK-F-NEXT: vsrl.vi v9, v9, 23
817 ; CHECK-F-NEXT: li a1, 127
818 ; CHECK-F-NEXT: vsub.vx v9, v9, a1
819 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
820 ; CHECK-F-NEXT: li a1, 32
821 ; CHECK-F-NEXT: vmerge.vxm v8, v9, a1, v0
822 ; CHECK-F-NEXT: fsrm a0
823 ; CHECK-F-NEXT: ret
824 ;
825 ; CHECK-D-LABEL: cttz_nxv1i32:
826 ; CHECK-D: # %bb.0:
827 ; CHECK-D-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
828 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
829 ; CHECK-D-NEXT: vand.vv v9, v8, v9
830 ; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v9
831 ; CHECK-D-NEXT: li a0, 52
832 ; CHECK-D-NEXT: vnsrl.wx v9, v10, a0
833 ; CHECK-D-NEXT: li a0, 1023
834 ; CHECK-D-NEXT: vsub.vx v9, v9, a0
835 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
836 ; CHECK-D-NEXT: li a0, 32
837 ; CHECK-D-NEXT: vmerge.vxm v8, v9, a0, v0
838 ; CHECK-D-NEXT: ret
839 ;
840 ; CHECK-ZVBB-LABEL: cttz_nxv1i32:
841 ; CHECK-ZVBB: # %bb.0:
842 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
843 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
844 ; CHECK-ZVBB-NEXT: ret
845 %a = call <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 false)
846 ret <vscale x 1 x i32> %a
847 }
848 declare <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32>, i1)
850 define <vscale x 2 x i32> @cttz_nxv2i32(<vscale x 2 x i32> %va) {
851 ; CHECK-ZVE64X-LABEL: cttz_nxv2i32:
852 ; CHECK-ZVE64X: # %bb.0:
853 ; CHECK-ZVE64X-NEXT: li a0, 1
854 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m1, ta, ma
855 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
856 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
857 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
858 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
859 ; CHECK-ZVE64X-NEXT: lui a0, 349525
860 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
861 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
862 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
863 ; CHECK-ZVE64X-NEXT: lui a0, 209715
864 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
865 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
866 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
867 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
868 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
869 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
870 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
871 ; CHECK-ZVE64X-NEXT: lui a0, 61681
872 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
873 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
874 ; CHECK-ZVE64X-NEXT: lui a0, 4112
875 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
876 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
877 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
878 ; CHECK-ZVE64X-NEXT: ret
879 ;
880 ; CHECK-F-LABEL: cttz_nxv2i32:
881 ; CHECK-F: # %bb.0:
882 ; CHECK-F-NEXT: vsetvli a0, zero, e32, m1, ta, ma
883 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
884 ; CHECK-F-NEXT: vand.vv v9, v8, v9
885 ; CHECK-F-NEXT: fsrmi a0, 1
886 ; CHECK-F-NEXT: vfcvt.f.xu.v v9, v9
887 ; CHECK-F-NEXT: vsrl.vi v9, v9, 23
888 ; CHECK-F-NEXT: li a1, 127
889 ; CHECK-F-NEXT: vsub.vx v9, v9, a1
890 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
891 ; CHECK-F-NEXT: li a1, 32
892 ; CHECK-F-NEXT: vmerge.vxm v8, v9, a1, v0
893 ; CHECK-F-NEXT: fsrm a0
894 ; CHECK-F-NEXT: ret
895 ;
896 ; CHECK-D-LABEL: cttz_nxv2i32:
897 ; CHECK-D: # %bb.0:
898 ; CHECK-D-NEXT: vsetvli a0, zero, e32, m1, ta, ma
899 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
900 ; CHECK-D-NEXT: vand.vv v9, v8, v9
901 ; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v9
902 ; CHECK-D-NEXT: li a0, 52
903 ; CHECK-D-NEXT: vnsrl.wx v9, v10, a0
904 ; CHECK-D-NEXT: li a0, 1023
905 ; CHECK-D-NEXT: vsub.vx v9, v9, a0
906 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
907 ; CHECK-D-NEXT: li a0, 32
908 ; CHECK-D-NEXT: vmerge.vxm v8, v9, a0, v0
909 ; CHECK-D-NEXT: ret
910 ;
911 ; CHECK-ZVBB-LABEL: cttz_nxv2i32:
912 ; CHECK-ZVBB: # %bb.0:
913 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
914 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
915 ; CHECK-ZVBB-NEXT: ret
916 %a = call <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 false)
917 ret <vscale x 2 x i32> %a
918 }
919 declare <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32>, i1)
921 define <vscale x 4 x i32> @cttz_nxv4i32(<vscale x 4 x i32> %va) {
922 ; CHECK-ZVE64X-LABEL: cttz_nxv4i32:
923 ; CHECK-ZVE64X: # %bb.0:
924 ; CHECK-ZVE64X-NEXT: li a0, 1
925 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m2, ta, ma
926 ; CHECK-ZVE64X-NEXT: vsub.vx v10, v8, a0
927 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
928 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v10
929 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
930 ; CHECK-ZVE64X-NEXT: lui a0, 349525
931 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
932 ; CHECK-ZVE64X-NEXT: vand.vx v10, v10, a0
933 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v10
934 ; CHECK-ZVE64X-NEXT: lui a0, 209715
935 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
936 ; CHECK-ZVE64X-NEXT: vand.vx v10, v8, a0
937 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
938 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
939 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v10, v8
940 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 4
941 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v10
942 ; CHECK-ZVE64X-NEXT: lui a0, 61681
943 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
944 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
945 ; CHECK-ZVE64X-NEXT: lui a0, 4112
946 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
947 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
948 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
949 ; CHECK-ZVE64X-NEXT: ret
950 ;
951 ; CHECK-F-LABEL: cttz_nxv4i32:
952 ; CHECK-F: # %bb.0:
953 ; CHECK-F-NEXT: vsetvli a0, zero, e32, m2, ta, ma
954 ; CHECK-F-NEXT: vrsub.vi v10, v8, 0
955 ; CHECK-F-NEXT: vand.vv v10, v8, v10
956 ; CHECK-F-NEXT: fsrmi a0, 1
957 ; CHECK-F-NEXT: vfcvt.f.xu.v v10, v10
958 ; CHECK-F-NEXT: vsrl.vi v10, v10, 23
959 ; CHECK-F-NEXT: li a1, 127
960 ; CHECK-F-NEXT: vsub.vx v10, v10, a1
961 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
962 ; CHECK-F-NEXT: li a1, 32
963 ; CHECK-F-NEXT: vmerge.vxm v8, v10, a1, v0
964 ; CHECK-F-NEXT: fsrm a0
965 ; CHECK-F-NEXT: ret
966 ;
967 ; CHECK-D-LABEL: cttz_nxv4i32:
968 ; CHECK-D: # %bb.0:
969 ; CHECK-D-NEXT: vsetvli a0, zero, e32, m2, ta, ma
970 ; CHECK-D-NEXT: vrsub.vi v10, v8, 0
971 ; CHECK-D-NEXT: vand.vv v10, v8, v10
972 ; CHECK-D-NEXT: vfwcvt.f.xu.v v12, v10
973 ; CHECK-D-NEXT: li a0, 52
974 ; CHECK-D-NEXT: vnsrl.wx v10, v12, a0
975 ; CHECK-D-NEXT: li a0, 1023
976 ; CHECK-D-NEXT: vsub.vx v10, v10, a0
977 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
978 ; CHECK-D-NEXT: li a0, 32
979 ; CHECK-D-NEXT: vmerge.vxm v8, v10, a0, v0
980 ; CHECK-D-NEXT: ret
981 ;
982 ; CHECK-ZVBB-LABEL: cttz_nxv4i32:
983 ; CHECK-ZVBB: # %bb.0:
984 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m2, ta, ma
985 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
986 ; CHECK-ZVBB-NEXT: ret
987 %a = call <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 false)
988 ret <vscale x 4 x i32> %a
989 }
990 declare <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32>, i1)
992 define <vscale x 8 x i32> @cttz_nxv8i32(<vscale x 8 x i32> %va) {
993 ; CHECK-ZVE64X-LABEL: cttz_nxv8i32:
994 ; CHECK-ZVE64X: # %bb.0:
995 ; CHECK-ZVE64X-NEXT: li a0, 1
996 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m4, ta, ma
997 ; CHECK-ZVE64X-NEXT: vsub.vx v12, v8, a0
998 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
999 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v12
1000 ; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 1
1001 ; CHECK-ZVE64X-NEXT: lui a0, 349525
1002 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
1003 ; CHECK-ZVE64X-NEXT: vand.vx v12, v12, a0
1004 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v12
1005 ; CHECK-ZVE64X-NEXT: lui a0, 209715
1006 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
1007 ; CHECK-ZVE64X-NEXT: vand.vx v12, v8, a0
1008 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
1009 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
1010 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v12, v8
1011 ; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 4
1012 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v12
1013 ; CHECK-ZVE64X-NEXT: lui a0, 61681
1014 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
1015 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
1016 ; CHECK-ZVE64X-NEXT: lui a0, 4112
1017 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
1018 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
1019 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
1020 ; CHECK-ZVE64X-NEXT: ret
1021 ;
1022 ; CHECK-F-LABEL: cttz_nxv8i32:
1023 ; CHECK-F: # %bb.0:
1024 ; CHECK-F-NEXT: vsetvli a0, zero, e32, m4, ta, ma
1025 ; CHECK-F-NEXT: vrsub.vi v12, v8, 0
1026 ; CHECK-F-NEXT: vand.vv v12, v8, v12
1027 ; CHECK-F-NEXT: fsrmi a0, 1
1028 ; CHECK-F-NEXT: vfcvt.f.xu.v v12, v12
1029 ; CHECK-F-NEXT: vsrl.vi v12, v12, 23
1030 ; CHECK-F-NEXT: li a1, 127
1031 ; CHECK-F-NEXT: vsub.vx v12, v12, a1
1032 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
1033 ; CHECK-F-NEXT: li a1, 32
1034 ; CHECK-F-NEXT: vmerge.vxm v8, v12, a1, v0
1035 ; CHECK-F-NEXT: fsrm a0
1036 ; CHECK-F-NEXT: ret
1037 ;
1038 ; CHECK-D-LABEL: cttz_nxv8i32:
1039 ; CHECK-D: # %bb.0:
1040 ; CHECK-D-NEXT: vsetvli a0, zero, e32, m4, ta, ma
1041 ; CHECK-D-NEXT: vrsub.vi v12, v8, 0
1042 ; CHECK-D-NEXT: vand.vv v12, v8, v12
1043 ; CHECK-D-NEXT: vfwcvt.f.xu.v v16, v12
1044 ; CHECK-D-NEXT: li a0, 52
1045 ; CHECK-D-NEXT: vnsrl.wx v12, v16, a0
1046 ; CHECK-D-NEXT: li a0, 1023
1047 ; CHECK-D-NEXT: vsub.vx v12, v12, a0
1048 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
1049 ; CHECK-D-NEXT: li a0, 32
1050 ; CHECK-D-NEXT: vmerge.vxm v8, v12, a0, v0
1051 ; CHECK-D-NEXT: ret
1052 ;
1053 ; CHECK-ZVBB-LABEL: cttz_nxv8i32:
1054 ; CHECK-ZVBB: # %bb.0:
1055 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m4, ta, ma
1056 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1057 ; CHECK-ZVBB-NEXT: ret
1058 %a = call <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 false)
1059 ret <vscale x 8 x i32> %a
1060 }
1061 declare <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32>, i1)
1063 define <vscale x 16 x i32> @cttz_nxv16i32(<vscale x 16 x i32> %va) {
1064 ; CHECK-ZVE64X-LABEL: cttz_nxv16i32:
1065 ; CHECK-ZVE64X: # %bb.0:
1066 ; CHECK-ZVE64X-NEXT: li a0, 1
1067 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1068 ; CHECK-ZVE64X-NEXT: vsub.vx v16, v8, a0
1069 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
1070 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v16
1071 ; CHECK-ZVE64X-NEXT: vsrl.vi v16, v8, 1
1072 ; CHECK-ZVE64X-NEXT: lui a0, 349525
1073 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
1074 ; CHECK-ZVE64X-NEXT: vand.vx v16, v16, a0
1075 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v16
1076 ; CHECK-ZVE64X-NEXT: lui a0, 209715
1077 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
1078 ; CHECK-ZVE64X-NEXT: vand.vx v16, v8, a0
1079 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
1080 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
1081 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v16, v8
1082 ; CHECK-ZVE64X-NEXT: vsrl.vi v16, v8, 4
1083 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v16
1084 ; CHECK-ZVE64X-NEXT: lui a0, 61681
1085 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
1086 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
1087 ; CHECK-ZVE64X-NEXT: lui a0, 4112
1088 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
1089 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
1090 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
1091 ; CHECK-ZVE64X-NEXT: ret
1092 ;
1093 ; CHECK-F-LABEL: cttz_nxv16i32:
1094 ; CHECK-F: # %bb.0:
1095 ; CHECK-F-NEXT: vsetvli a0, zero, e32, m8, ta, ma
1096 ; CHECK-F-NEXT: vrsub.vi v16, v8, 0
1097 ; CHECK-F-NEXT: vand.vv v16, v8, v16
1098 ; CHECK-F-NEXT: fsrmi a0, 1
1099 ; CHECK-F-NEXT: vfcvt.f.xu.v v16, v16
1100 ; CHECK-F-NEXT: vsrl.vi v16, v16, 23
1101 ; CHECK-F-NEXT: li a1, 127
1102 ; CHECK-F-NEXT: vsub.vx v16, v16, a1
1103 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
1104 ; CHECK-F-NEXT: li a1, 32
1105 ; CHECK-F-NEXT: vmerge.vxm v8, v16, a1, v0
1106 ; CHECK-F-NEXT: fsrm a0
1107 ; CHECK-F-NEXT: ret
1108 ;
1109 ; CHECK-D-LABEL: cttz_nxv16i32:
1110 ; CHECK-D: # %bb.0:
1111 ; CHECK-D-NEXT: vsetvli a0, zero, e32, m8, ta, ma
1112 ; CHECK-D-NEXT: vrsub.vi v16, v8, 0
1113 ; CHECK-D-NEXT: vand.vv v16, v8, v16
1114 ; CHECK-D-NEXT: fsrmi a0, 1
1115 ; CHECK-D-NEXT: vfcvt.f.xu.v v16, v16
1116 ; CHECK-D-NEXT: vsrl.vi v16, v16, 23
1117 ; CHECK-D-NEXT: li a1, 127
1118 ; CHECK-D-NEXT: vsub.vx v16, v16, a1
1119 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
1120 ; CHECK-D-NEXT: li a1, 32
1121 ; CHECK-D-NEXT: vmerge.vxm v8, v16, a1, v0
1122 ; CHECK-D-NEXT: fsrm a0
1123 ; CHECK-D-NEXT: ret
1124 ;
1125 ; CHECK-ZVBB-LABEL: cttz_nxv16i32:
1126 ; CHECK-ZVBB: # %bb.0:
1127 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma
1128 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1129 ; CHECK-ZVBB-NEXT: ret
1130 %a = call <vscale x 16 x i32> @llvm.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 false)
1131 ret <vscale x 16 x i32> %a
1132 }
1133 declare <vscale x 16 x i32> @llvm.cttz.nxv16i32(<vscale x 16 x i32>, i1)
1135 define <vscale x 1 x i64> @cttz_nxv1i64(<vscale x 1 x i64> %va) {
1136 ; RV32I-LABEL: cttz_nxv1i64:
1137 ; RV32I: # %bb.0:
1138 ; RV32I-NEXT: li a0, 1
1139 ; RV32I-NEXT: vsetvli a1, zero, e64, m1, ta, ma
1140 ; RV32I-NEXT: vsub.vx v9, v8, a0
1141 ; RV32I-NEXT: vnot.v v8, v8
1142 ; RV32I-NEXT: vand.vv v8, v8, v9
1143 ; RV32I-NEXT: vsrl.vi v9, v8, 1
1144 ; RV32I-NEXT: lui a0, 349525
1145 ; RV32I-NEXT: addi a0, a0, 1365
1146 ; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
1147 ; RV32I-NEXT: vmv.v.x v10, a0
1148 ; RV32I-NEXT: vsetvli a0, zero, e64, m1, ta, ma
1149 ; RV32I-NEXT: vand.vv v9, v9, v10
1150 ; RV32I-NEXT: vsub.vv v8, v8, v9
1151 ; RV32I-NEXT: lui a0, 209715
1152 ; RV32I-NEXT: addi a0, a0, 819
1153 ; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
1154 ; RV32I-NEXT: vmv.v.x v9, a0
1155 ; RV32I-NEXT: vsetvli a0, zero, e64, m1, ta, ma
1156 ; RV32I-NEXT: vand.vv v10, v8, v9
1157 ; RV32I-NEXT: vsrl.vi v8, v8, 2
1158 ; RV32I-NEXT: vand.vv v8, v8, v9
1159 ; RV32I-NEXT: vadd.vv v8, v10, v8
1160 ; RV32I-NEXT: vsrl.vi v9, v8, 4
1161 ; RV32I-NEXT: vadd.vv v8, v8, v9
1162 ; RV32I-NEXT: lui a0, 61681
1163 ; RV32I-NEXT: addi a0, a0, -241
1164 ; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
1165 ; RV32I-NEXT: vmv.v.x v9, a0
1166 ; RV32I-NEXT: vsetvli a0, zero, e64, m1, ta, ma
1167 ; RV32I-NEXT: vand.vv v8, v8, v9
1168 ; RV32I-NEXT: lui a0, 4112
1169 ; RV32I-NEXT: addi a0, a0, 257
1170 ; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
1171 ; RV32I-NEXT: vmv.v.x v9, a0
1172 ; RV32I-NEXT: vsetvli a0, zero, e64, m1, ta, ma
1173 ; RV32I-NEXT: vmul.vv v8, v8, v9
1174 ; RV32I-NEXT: li a0, 56
1175 ; RV32I-NEXT: vsrl.vx v8, v8, a0
1176 ; RV32I-NEXT: ret
1177 ;
1178 ; RV64I-LABEL: cttz_nxv1i64:
1179 ; RV64I: # %bb.0:
1180 ; RV64I-NEXT: li a0, 1
1181 ; RV64I-NEXT: vsetvli a1, zero, e64, m1, ta, ma
1182 ; RV64I-NEXT: vsub.vx v9, v8, a0
1183 ; RV64I-NEXT: vnot.v v8, v8
1184 ; RV64I-NEXT: vand.vv v8, v8, v9
1185 ; RV64I-NEXT: vsrl.vi v9, v8, 1
1186 ; RV64I-NEXT: lui a0, 349525
1187 ; RV64I-NEXT: addiw a0, a0, 1365
1188 ; RV64I-NEXT: slli a1, a0, 32
1189 ; RV64I-NEXT: add a0, a0, a1
1190 ; RV64I-NEXT: vand.vx v9, v9, a0
1191 ; RV64I-NEXT: vsub.vv v8, v8, v9
1192 ; RV64I-NEXT: lui a0, 209715
1193 ; RV64I-NEXT: addiw a0, a0, 819
1194 ; RV64I-NEXT: slli a1, a0, 32
1195 ; RV64I-NEXT: add a0, a0, a1
1196 ; RV64I-NEXT: vand.vx v9, v8, a0
1197 ; RV64I-NEXT: vsrl.vi v8, v8, 2
1198 ; RV64I-NEXT: vand.vx v8, v8, a0
1199 ; RV64I-NEXT: vadd.vv v8, v9, v8
1200 ; RV64I-NEXT: vsrl.vi v9, v8, 4
1201 ; RV64I-NEXT: vadd.vv v8, v8, v9
1202 ; RV64I-NEXT: lui a0, 61681
1203 ; RV64I-NEXT: addiw a0, a0, -241
1204 ; RV64I-NEXT: slli a1, a0, 32
1205 ; RV64I-NEXT: add a0, a0, a1
1206 ; RV64I-NEXT: vand.vx v8, v8, a0
1207 ; RV64I-NEXT: lui a0, 4112
1208 ; RV64I-NEXT: addiw a0, a0, 257
1209 ; RV64I-NEXT: slli a1, a0, 32
1210 ; RV64I-NEXT: add a0, a0, a1
1211 ; RV64I-NEXT: vmul.vx v8, v8, a0
1212 ; RV64I-NEXT: li a0, 56
1213 ; RV64I-NEXT: vsrl.vx v8, v8, a0
1214 ; RV64I-NEXT: ret
1215 ;
1216 ; RV32F-LABEL: cttz_nxv1i64:
1217 ; RV32F: # %bb.0:
1218 ; RV32F-NEXT: vsetvli a0, zero, e64, m1, ta, ma
1219 ; RV32F-NEXT: vmseq.vx v0, v8, zero
1220 ; RV32F-NEXT: vrsub.vi v9, v8, 0
1221 ; RV32F-NEXT: vand.vv v8, v8, v9
1222 ; RV32F-NEXT: fsrmi a0, 1
1223 ; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
1224 ; RV32F-NEXT: vfncvt.f.xu.w v9, v8
1225 ; RV32F-NEXT: vsrl.vi v8, v9, 23
1226 ; RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
1227 ; RV32F-NEXT: vzext.vf2 v9, v8
1228 ; RV32F-NEXT: li a1, 127
1229 ; RV32F-NEXT: vsub.vx v8, v9, a1
1230 ; RV32F-NEXT: li a1, 64
1231 ; RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
1232 ; RV32F-NEXT: fsrm a0
1233 ; RV32F-NEXT: ret
1234 ;
1235 ; RV64F-LABEL: cttz_nxv1i64:
1236 ; RV64F: # %bb.0:
1237 ; RV64F-NEXT: vsetvli a0, zero, e64, m1, ta, ma
1238 ; RV64F-NEXT: vrsub.vi v9, v8, 0
1239 ; RV64F-NEXT: vand.vv v9, v8, v9
1240 ; RV64F-NEXT: fsrmi a0, 1
1241 ; RV64F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
1242 ; RV64F-NEXT: vfncvt.f.xu.w v10, v9
1243 ; RV64F-NEXT: vsrl.vi v9, v10, 23
1244 ; RV64F-NEXT: li a1, 127
1245 ; RV64F-NEXT: vwsubu.vx v10, v9, a1
1246 ; RV64F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
1247 ; RV64F-NEXT: vmseq.vi v0, v8, 0
1248 ; RV64F-NEXT: li a1, 64
1249 ; RV64F-NEXT: vmerge.vxm v8, v10, a1, v0
1250 ; RV64F-NEXT: fsrm a0
1251 ; RV64F-NEXT: ret
1252 ;
1253 ; RV32D-LABEL: cttz_nxv1i64:
1254 ; RV32D: # %bb.0:
1255 ; RV32D-NEXT: vsetvli a0, zero, e64, m1, ta, ma
1256 ; RV32D-NEXT: vmseq.vx v0, v8, zero
1257 ; RV32D-NEXT: vrsub.vi v9, v8, 0
1258 ; RV32D-NEXT: vand.vv v8, v8, v9
1259 ; RV32D-NEXT: fsrmi a0, 1
1260 ; RV32D-NEXT: vfcvt.f.xu.v v8, v8
1261 ; RV32D-NEXT: li a1, 52
1262 ; RV32D-NEXT: vsrl.vx v8, v8, a1
1263 ; RV32D-NEXT: li a1, 1023
1264 ; RV32D-NEXT: vsub.vx v8, v8, a1
1265 ; RV32D-NEXT: li a1, 64
1266 ; RV32D-NEXT: vmerge.vxm v8, v8, a1, v0
1267 ; RV32D-NEXT: fsrm a0
1268 ; RV32D-NEXT: ret
1269 ;
1270 ; RV64D-LABEL: cttz_nxv1i64:
1271 ; RV64D: # %bb.0:
1272 ; RV64D-NEXT: vsetvli a0, zero, e64, m1, ta, ma
1273 ; RV64D-NEXT: vrsub.vi v9, v8, 0
1274 ; RV64D-NEXT: vand.vv v9, v8, v9
1275 ; RV64D-NEXT: fsrmi a0, 1
1276 ; RV64D-NEXT: vfcvt.f.xu.v v9, v9
1277 ; RV64D-NEXT: li a1, 52
1278 ; RV64D-NEXT: vsrl.vx v9, v9, a1
1279 ; RV64D-NEXT: li a1, 1023
1280 ; RV64D-NEXT: vsub.vx v9, v9, a1
1281 ; RV64D-NEXT: vmseq.vi v0, v8, 0
1282 ; RV64D-NEXT: li a1, 64
1283 ; RV64D-NEXT: vmerge.vxm v8, v9, a1, v0
1284 ; RV64D-NEXT: fsrm a0
1285 ; RV64D-NEXT: ret
1286 ;
1287 ; CHECK-ZVBB-LABEL: cttz_nxv1i64:
1288 ; CHECK-ZVBB: # %bb.0:
1289 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma
1290 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1291 ; CHECK-ZVBB-NEXT: ret
1292 %a = call <vscale x 1 x i64> @llvm.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 false)
1293 ret <vscale x 1 x i64> %a
1294 }
1295 declare <vscale x 1 x i64> @llvm.cttz.nxv1i64(<vscale x 1 x i64>, i1)
1297 define <vscale x 2 x i64> @cttz_nxv2i64(<vscale x 2 x i64> %va) {
1298 ; RV32I-LABEL: cttz_nxv2i64:
1299 ; RV32I: # %bb.0:
1300 ; RV32I-NEXT: li a0, 1
1301 ; RV32I-NEXT: vsetvli a1, zero, e64, m2, ta, ma
1302 ; RV32I-NEXT: vsub.vx v10, v8, a0
1303 ; RV32I-NEXT: vnot.v v8, v8
1304 ; RV32I-NEXT: vand.vv v8, v8, v10
1305 ; RV32I-NEXT: vsrl.vi v10, v8, 1
1306 ; RV32I-NEXT: lui a0, 349525
1307 ; RV32I-NEXT: addi a0, a0, 1365
1308 ; RV32I-NEXT: vsetvli a1, zero, e32, m2, ta, ma
1309 ; RV32I-NEXT: vmv.v.x v12, a0
1310 ; RV32I-NEXT: vsetvli a0, zero, e64, m2, ta, ma
1311 ; RV32I-NEXT: vand.vv v10, v10, v12
1312 ; RV32I-NEXT: vsub.vv v8, v8, v10
1313 ; RV32I-NEXT: lui a0, 209715
1314 ; RV32I-NEXT: addi a0, a0, 819
1315 ; RV32I-NEXT: vsetvli a1, zero, e32, m2, ta, ma
1316 ; RV32I-NEXT: vmv.v.x v10, a0
1317 ; RV32I-NEXT: vsetvli a0, zero, e64, m2, ta, ma
1318 ; RV32I-NEXT: vand.vv v12, v8, v10
1319 ; RV32I-NEXT: vsrl.vi v8, v8, 2
1320 ; RV32I-NEXT: vand.vv v8, v8, v10
1321 ; RV32I-NEXT: vadd.vv v8, v12, v8
1322 ; RV32I-NEXT: vsrl.vi v10, v8, 4
1323 ; RV32I-NEXT: vadd.vv v8, v8, v10
1324 ; RV32I-NEXT: lui a0, 61681
1325 ; RV32I-NEXT: addi a0, a0, -241
1326 ; RV32I-NEXT: vsetvli a1, zero, e32, m2, ta, ma
1327 ; RV32I-NEXT: vmv.v.x v10, a0
1328 ; RV32I-NEXT: vsetvli a0, zero, e64, m2, ta, ma
1329 ; RV32I-NEXT: vand.vv v8, v8, v10
1330 ; RV32I-NEXT: lui a0, 4112
1331 ; RV32I-NEXT: addi a0, a0, 257
1332 ; RV32I-NEXT: vsetvli a1, zero, e32, m2, ta, ma
1333 ; RV32I-NEXT: vmv.v.x v10, a0
1334 ; RV32I-NEXT: vsetvli a0, zero, e64, m2, ta, ma
1335 ; RV32I-NEXT: vmul.vv v8, v8, v10
1336 ; RV32I-NEXT: li a0, 56
1337 ; RV32I-NEXT: vsrl.vx v8, v8, a0
1338 ; RV32I-NEXT: ret
1339 ;
1340 ; RV64I-LABEL: cttz_nxv2i64:
1341 ; RV64I: # %bb.0:
1342 ; RV64I-NEXT: li a0, 1
1343 ; RV64I-NEXT: vsetvli a1, zero, e64, m2, ta, ma
1344 ; RV64I-NEXT: vsub.vx v10, v8, a0
1345 ; RV64I-NEXT: vnot.v v8, v8
1346 ; RV64I-NEXT: vand.vv v8, v8, v10
1347 ; RV64I-NEXT: vsrl.vi v10, v8, 1
1348 ; RV64I-NEXT: lui a0, 349525
1349 ; RV64I-NEXT: addiw a0, a0, 1365
1350 ; RV64I-NEXT: slli a1, a0, 32
1351 ; RV64I-NEXT: add a0, a0, a1
1352 ; RV64I-NEXT: vand.vx v10, v10, a0
1353 ; RV64I-NEXT: vsub.vv v8, v8, v10
1354 ; RV64I-NEXT: lui a0, 209715
1355 ; RV64I-NEXT: addiw a0, a0, 819
1356 ; RV64I-NEXT: slli a1, a0, 32
1357 ; RV64I-NEXT: add a0, a0, a1
1358 ; RV64I-NEXT: vand.vx v10, v8, a0
1359 ; RV64I-NEXT: vsrl.vi v8, v8, 2
1360 ; RV64I-NEXT: vand.vx v8, v8, a0
1361 ; RV64I-NEXT: vadd.vv v8, v10, v8
1362 ; RV64I-NEXT: vsrl.vi v10, v8, 4
1363 ; RV64I-NEXT: vadd.vv v8, v8, v10
1364 ; RV64I-NEXT: lui a0, 61681
1365 ; RV64I-NEXT: addiw a0, a0, -241
1366 ; RV64I-NEXT: slli a1, a0, 32
1367 ; RV64I-NEXT: add a0, a0, a1
1368 ; RV64I-NEXT: vand.vx v8, v8, a0
1369 ; RV64I-NEXT: lui a0, 4112
1370 ; RV64I-NEXT: addiw a0, a0, 257
1371 ; RV64I-NEXT: slli a1, a0, 32
1372 ; RV64I-NEXT: add a0, a0, a1
1373 ; RV64I-NEXT: vmul.vx v8, v8, a0
1374 ; RV64I-NEXT: li a0, 56
1375 ; RV64I-NEXT: vsrl.vx v8, v8, a0
1376 ; RV64I-NEXT: ret
1377 ;
1378 ; RV32F-LABEL: cttz_nxv2i64:
1379 ; RV32F: # %bb.0:
1380 ; RV32F-NEXT: vsetvli a0, zero, e64, m2, ta, ma
1381 ; RV32F-NEXT: vmseq.vx v0, v8, zero
1382 ; RV32F-NEXT: vrsub.vi v10, v8, 0
1383 ; RV32F-NEXT: vand.vv v8, v8, v10
1384 ; RV32F-NEXT: fsrmi a0, 1
1385 ; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
1386 ; RV32F-NEXT: vfncvt.f.xu.w v10, v8
1387 ; RV32F-NEXT: vsrl.vi v8, v10, 23
1388 ; RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
1389 ; RV32F-NEXT: vzext.vf2 v10, v8
1390 ; RV32F-NEXT: li a1, 127
1391 ; RV32F-NEXT: vsub.vx v8, v10, a1
1392 ; RV32F-NEXT: li a1, 64
1393 ; RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
1394 ; RV32F-NEXT: fsrm a0
1395 ; RV32F-NEXT: ret
1396 ;
1397 ; RV64F-LABEL: cttz_nxv2i64:
1398 ; RV64F: # %bb.0:
1399 ; RV64F-NEXT: vsetvli a0, zero, e64, m2, ta, ma
1400 ; RV64F-NEXT: vrsub.vi v10, v8, 0
1401 ; RV64F-NEXT: vand.vv v10, v8, v10
1402 ; RV64F-NEXT: fsrmi a0, 1
1403 ; RV64F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
1404 ; RV64F-NEXT: vfncvt.f.xu.w v12, v10
1405 ; RV64F-NEXT: vsrl.vi v10, v12, 23
1406 ; RV64F-NEXT: li a1, 127
1407 ; RV64F-NEXT: vwsubu.vx v12, v10, a1
1408 ; RV64F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
1409 ; RV64F-NEXT: vmseq.vi v0, v8, 0
1410 ; RV64F-NEXT: li a1, 64
1411 ; RV64F-NEXT: vmerge.vxm v8, v12, a1, v0
1412 ; RV64F-NEXT: fsrm a0
1413 ; RV64F-NEXT: ret
1414 ;
1415 ; RV32D-LABEL: cttz_nxv2i64:
1416 ; RV32D: # %bb.0:
1417 ; RV32D-NEXT: vsetvli a0, zero, e64, m2, ta, ma
1418 ; RV32D-NEXT: vmseq.vx v0, v8, zero
1419 ; RV32D-NEXT: vrsub.vi v10, v8, 0
1420 ; RV32D-NEXT: vand.vv v8, v8, v10
1421 ; RV32D-NEXT: fsrmi a0, 1
1422 ; RV32D-NEXT: vfcvt.f.xu.v v8, v8
1423 ; RV32D-NEXT: li a1, 52
1424 ; RV32D-NEXT: vsrl.vx v8, v8, a1
1425 ; RV32D-NEXT: li a1, 1023
1426 ; RV32D-NEXT: vsub.vx v8, v8, a1
1427 ; RV32D-NEXT: li a1, 64
1428 ; RV32D-NEXT: vmerge.vxm v8, v8, a1, v0
1429 ; RV32D-NEXT: fsrm a0
1430 ; RV32D-NEXT: ret
1431 ;
1432 ; RV64D-LABEL: cttz_nxv2i64:
1433 ; RV64D: # %bb.0:
1434 ; RV64D-NEXT: vsetvli a0, zero, e64, m2, ta, ma
1435 ; RV64D-NEXT: vrsub.vi v10, v8, 0
1436 ; RV64D-NEXT: vand.vv v10, v8, v10
1437 ; RV64D-NEXT: fsrmi a0, 1
1438 ; RV64D-NEXT: vfcvt.f.xu.v v10, v10
1439 ; RV64D-NEXT: li a1, 52
1440 ; RV64D-NEXT: vsrl.vx v10, v10, a1
1441 ; RV64D-NEXT: li a1, 1023
1442 ; RV64D-NEXT: vsub.vx v10, v10, a1
1443 ; RV64D-NEXT: vmseq.vi v0, v8, 0
1444 ; RV64D-NEXT: li a1, 64
1445 ; RV64D-NEXT: vmerge.vxm v8, v10, a1, v0
1446 ; RV64D-NEXT: fsrm a0
1447 ; RV64D-NEXT: ret
1448 ;
1449 ; CHECK-ZVBB-LABEL: cttz_nxv2i64:
1450 ; CHECK-ZVBB: # %bb.0:
1451 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
1452 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1453 ; CHECK-ZVBB-NEXT: ret
1454 %a = call <vscale x 2 x i64> @llvm.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 false)
1455 ret <vscale x 2 x i64> %a
1456 }
1457 declare <vscale x 2 x i64> @llvm.cttz.nxv2i64(<vscale x 2 x i64>, i1)
1459 define <vscale x 4 x i64> @cttz_nxv4i64(<vscale x 4 x i64> %va) {
1460 ; RV32I-LABEL: cttz_nxv4i64:
1461 ; RV32I: # %bb.0:
1462 ; RV32I-NEXT: li a0, 1
1463 ; RV32I-NEXT: vsetvli a1, zero, e64, m4, ta, ma
1464 ; RV32I-NEXT: vsub.vx v12, v8, a0
1465 ; RV32I-NEXT: vnot.v v8, v8
1466 ; RV32I-NEXT: vand.vv v8, v8, v12
1467 ; RV32I-NEXT: vsrl.vi v12, v8, 1
1468 ; RV32I-NEXT: lui a0, 349525
1469 ; RV32I-NEXT: addi a0, a0, 1365
1470 ; RV32I-NEXT: vsetvli a1, zero, e32, m4, ta, ma
1471 ; RV32I-NEXT: vmv.v.x v16, a0
1472 ; RV32I-NEXT: vsetvli a0, zero, e64, m4, ta, ma
1473 ; RV32I-NEXT: vand.vv v12, v12, v16
1474 ; RV32I-NEXT: vsub.vv v8, v8, v12
1475 ; RV32I-NEXT: lui a0, 209715
1476 ; RV32I-NEXT: addi a0, a0, 819
1477 ; RV32I-NEXT: vsetvli a1, zero, e32, m4, ta, ma
1478 ; RV32I-NEXT: vmv.v.x v12, a0
1479 ; RV32I-NEXT: vsetvli a0, zero, e64, m4, ta, ma
1480 ; RV32I-NEXT: vand.vv v16, v8, v12
1481 ; RV32I-NEXT: vsrl.vi v8, v8, 2
1482 ; RV32I-NEXT: vand.vv v8, v8, v12
1483 ; RV32I-NEXT: vadd.vv v8, v16, v8
1484 ; RV32I-NEXT: vsrl.vi v12, v8, 4
1485 ; RV32I-NEXT: vadd.vv v8, v8, v12
1486 ; RV32I-NEXT: lui a0, 61681
1487 ; RV32I-NEXT: addi a0, a0, -241
1488 ; RV32I-NEXT: vsetvli a1, zero, e32, m4, ta, ma
1489 ; RV32I-NEXT: vmv.v.x v12, a0
1490 ; RV32I-NEXT: vsetvli a0, zero, e64, m4, ta, ma
1491 ; RV32I-NEXT: vand.vv v8, v8, v12
1492 ; RV32I-NEXT: lui a0, 4112
1493 ; RV32I-NEXT: addi a0, a0, 257
1494 ; RV32I-NEXT: vsetvli a1, zero, e32, m4, ta, ma
1495 ; RV32I-NEXT: vmv.v.x v12, a0
1496 ; RV32I-NEXT: vsetvli a0, zero, e64, m4, ta, ma
1497 ; RV32I-NEXT: vmul.vv v8, v8, v12
1498 ; RV32I-NEXT: li a0, 56
1499 ; RV32I-NEXT: vsrl.vx v8, v8, a0
1500 ; RV32I-NEXT: ret
1501 ;
1502 ; RV64I-LABEL: cttz_nxv4i64:
1503 ; RV64I: # %bb.0:
1504 ; RV64I-NEXT: li a0, 1
1505 ; RV64I-NEXT: vsetvli a1, zero, e64, m4, ta, ma
1506 ; RV64I-NEXT: vsub.vx v12, v8, a0
1507 ; RV64I-NEXT: vnot.v v8, v8
1508 ; RV64I-NEXT: vand.vv v8, v8, v12
1509 ; RV64I-NEXT: vsrl.vi v12, v8, 1
1510 ; RV64I-NEXT: lui a0, 349525
1511 ; RV64I-NEXT: addiw a0, a0, 1365
1512 ; RV64I-NEXT: slli a1, a0, 32
1513 ; RV64I-NEXT: add a0, a0, a1
1514 ; RV64I-NEXT: vand.vx v12, v12, a0
1515 ; RV64I-NEXT: vsub.vv v8, v8, v12
1516 ; RV64I-NEXT: lui a0, 209715
1517 ; RV64I-NEXT: addiw a0, a0, 819
1518 ; RV64I-NEXT: slli a1, a0, 32
1519 ; RV64I-NEXT: add a0, a0, a1
1520 ; RV64I-NEXT: vand.vx v12, v8, a0
1521 ; RV64I-NEXT: vsrl.vi v8, v8, 2
1522 ; RV64I-NEXT: vand.vx v8, v8, a0
1523 ; RV64I-NEXT: vadd.vv v8, v12, v8
1524 ; RV64I-NEXT: vsrl.vi v12, v8, 4
1525 ; RV64I-NEXT: vadd.vv v8, v8, v12
1526 ; RV64I-NEXT: lui a0, 61681
1527 ; RV64I-NEXT: addiw a0, a0, -241
1528 ; RV64I-NEXT: slli a1, a0, 32
1529 ; RV64I-NEXT: add a0, a0, a1
1530 ; RV64I-NEXT: vand.vx v8, v8, a0
1531 ; RV64I-NEXT: lui a0, 4112
1532 ; RV64I-NEXT: addiw a0, a0, 257
1533 ; RV64I-NEXT: slli a1, a0, 32
1534 ; RV64I-NEXT: add a0, a0, a1
1535 ; RV64I-NEXT: vmul.vx v8, v8, a0
1536 ; RV64I-NEXT: li a0, 56
1537 ; RV64I-NEXT: vsrl.vx v8, v8, a0
1538 ; RV64I-NEXT: ret
1539 ;
1540 ; RV32F-LABEL: cttz_nxv4i64:
1541 ; RV32F: # %bb.0:
1542 ; RV32F-NEXT: vsetvli a0, zero, e64, m4, ta, ma
1543 ; RV32F-NEXT: vmseq.vx v0, v8, zero
1544 ; RV32F-NEXT: vrsub.vi v12, v8, 0
1545 ; RV32F-NEXT: vand.vv v8, v8, v12
1546 ; RV32F-NEXT: fsrmi a0, 1
1547 ; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
1548 ; RV32F-NEXT: vfncvt.f.xu.w v12, v8
1549 ; RV32F-NEXT: vsrl.vi v8, v12, 23
1550 ; RV32F-NEXT: vsetvli zero, zero, e64, m4, ta, ma
1551 ; RV32F-NEXT: vzext.vf2 v12, v8
1552 ; RV32F-NEXT: li a1, 127
1553 ; RV32F-NEXT: vsub.vx v8, v12, a1
1554 ; RV32F-NEXT: li a1, 64
1555 ; RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
1556 ; RV32F-NEXT: fsrm a0
1557 ; RV32F-NEXT: ret
1558 ;
1559 ; RV64F-LABEL: cttz_nxv4i64:
1560 ; RV64F: # %bb.0:
1561 ; RV64F-NEXT: vsetvli a0, zero, e64, m4, ta, ma
1562 ; RV64F-NEXT: vrsub.vi v12, v8, 0
1563 ; RV64F-NEXT: vand.vv v12, v8, v12
1564 ; RV64F-NEXT: fsrmi a0, 1
1565 ; RV64F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
1566 ; RV64F-NEXT: vfncvt.f.xu.w v16, v12
1567 ; RV64F-NEXT: vsrl.vi v12, v16, 23
1568 ; RV64F-NEXT: li a1, 127
1569 ; RV64F-NEXT: vwsubu.vx v16, v12, a1
1570 ; RV64F-NEXT: vsetvli zero, zero, e64, m4, ta, ma
1571 ; RV64F-NEXT: vmseq.vi v0, v8, 0
1572 ; RV64F-NEXT: li a1, 64
1573 ; RV64F-NEXT: vmerge.vxm v8, v16, a1, v0
1574 ; RV64F-NEXT: fsrm a0
1575 ; RV64F-NEXT: ret
1576 ;
1577 ; RV32D-LABEL: cttz_nxv4i64:
1578 ; RV32D: # %bb.0:
1579 ; RV32D-NEXT: vsetvli a0, zero, e64, m4, ta, ma
1580 ; RV32D-NEXT: vmseq.vx v0, v8, zero
1581 ; RV32D-NEXT: vrsub.vi v12, v8, 0
1582 ; RV32D-NEXT: vand.vv v8, v8, v12
1583 ; RV32D-NEXT: fsrmi a0, 1
1584 ; RV32D-NEXT: vfcvt.f.xu.v v8, v8
1585 ; RV32D-NEXT: li a1, 52
1586 ; RV32D-NEXT: vsrl.vx v8, v8, a1
1587 ; RV32D-NEXT: li a1, 1023
1588 ; RV32D-NEXT: vsub.vx v8, v8, a1
1589 ; RV32D-NEXT: li a1, 64
1590 ; RV32D-NEXT: vmerge.vxm v8, v8, a1, v0
1591 ; RV32D-NEXT: fsrm a0
1592 ; RV32D-NEXT: ret
1593 ;
1594 ; RV64D-LABEL: cttz_nxv4i64:
1595 ; RV64D: # %bb.0:
1596 ; RV64D-NEXT: vsetvli a0, zero, e64, m4, ta, ma
1597 ; RV64D-NEXT: vrsub.vi v12, v8, 0
1598 ; RV64D-NEXT: vand.vv v12, v8, v12
1599 ; RV64D-NEXT: fsrmi a0, 1
1600 ; RV64D-NEXT: vfcvt.f.xu.v v12, v12
1601 ; RV64D-NEXT: li a1, 52
1602 ; RV64D-NEXT: vsrl.vx v12, v12, a1
1603 ; RV64D-NEXT: li a1, 1023
1604 ; RV64D-NEXT: vsub.vx v12, v12, a1
1605 ; RV64D-NEXT: vmseq.vi v0, v8, 0
1606 ; RV64D-NEXT: li a1, 64
1607 ; RV64D-NEXT: vmerge.vxm v8, v12, a1, v0
1608 ; RV64D-NEXT: fsrm a0
1609 ; RV64D-NEXT: ret
1610 ;
1611 ; CHECK-ZVBB-LABEL: cttz_nxv4i64:
1612 ; CHECK-ZVBB: # %bb.0:
1613 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma
1614 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1615 ; CHECK-ZVBB-NEXT: ret
1616 %a = call <vscale x 4 x i64> @llvm.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 false)
1617 ret <vscale x 4 x i64> %a
1618 }
1619 declare <vscale x 4 x i64> @llvm.cttz.nxv4i64(<vscale x 4 x i64>, i1)
1621 define <vscale x 8 x i64> @cttz_nxv8i64(<vscale x 8 x i64> %va) {
1622 ; RV32I-LABEL: cttz_nxv8i64:
1623 ; RV32I: # %bb.0:
1624 ; RV32I-NEXT: li a0, 1
1625 ; RV32I-NEXT: vsetvli a1, zero, e64, m8, ta, ma
1626 ; RV32I-NEXT: vsub.vx v16, v8, a0
1627 ; RV32I-NEXT: vnot.v v8, v8
1628 ; RV32I-NEXT: vand.vv v8, v8, v16
1629 ; RV32I-NEXT: vsrl.vi v16, v8, 1
1630 ; RV32I-NEXT: lui a0, 349525
1631 ; RV32I-NEXT: addi a0, a0, 1365
1632 ; RV32I-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1633 ; RV32I-NEXT: vmv.v.x v24, a0
1634 ; RV32I-NEXT: vsetvli a0, zero, e64, m8, ta, ma
1635 ; RV32I-NEXT: vand.vv v16, v16, v24
1636 ; RV32I-NEXT: vsub.vv v8, v8, v16
1637 ; RV32I-NEXT: lui a0, 209715
1638 ; RV32I-NEXT: addi a0, a0, 819
1639 ; RV32I-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1640 ; RV32I-NEXT: vmv.v.x v16, a0
1641 ; RV32I-NEXT: vsetvli a0, zero, e64, m8, ta, ma
1642 ; RV32I-NEXT: vand.vv v24, v8, v16
1643 ; RV32I-NEXT: vsrl.vi v8, v8, 2
1644 ; RV32I-NEXT: vand.vv v8, v8, v16
1645 ; RV32I-NEXT: vadd.vv v8, v24, v8
1646 ; RV32I-NEXT: vsrl.vi v16, v8, 4
1647 ; RV32I-NEXT: vadd.vv v8, v8, v16
1648 ; RV32I-NEXT: lui a0, 61681
1649 ; RV32I-NEXT: addi a0, a0, -241
1650 ; RV32I-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1651 ; RV32I-NEXT: vmv.v.x v16, a0
1652 ; RV32I-NEXT: vsetvli a0, zero, e64, m8, ta, ma
1653 ; RV32I-NEXT: vand.vv v8, v8, v16
1654 ; RV32I-NEXT: lui a0, 4112
1655 ; RV32I-NEXT: addi a0, a0, 257
1656 ; RV32I-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1657 ; RV32I-NEXT: vmv.v.x v16, a0
1658 ; RV32I-NEXT: vsetvli a0, zero, e64, m8, ta, ma
1659 ; RV32I-NEXT: vmul.vv v8, v8, v16
1660 ; RV32I-NEXT: li a0, 56
1661 ; RV32I-NEXT: vsrl.vx v8, v8, a0
1662 ; RV32I-NEXT: ret
1663 ;
1664 ; RV64I-LABEL: cttz_nxv8i64:
1665 ; RV64I: # %bb.0:
1666 ; RV64I-NEXT: li a0, 1
1667 ; RV64I-NEXT: vsetvli a1, zero, e64, m8, ta, ma
1668 ; RV64I-NEXT: vsub.vx v16, v8, a0
1669 ; RV64I-NEXT: vnot.v v8, v8
1670 ; RV64I-NEXT: vand.vv v8, v8, v16
1671 ; RV64I-NEXT: vsrl.vi v16, v8, 1
1672 ; RV64I-NEXT: lui a0, 349525
1673 ; RV64I-NEXT: addiw a0, a0, 1365
1674 ; RV64I-NEXT: slli a1, a0, 32
1675 ; RV64I-NEXT: add a0, a0, a1
1676 ; RV64I-NEXT: vand.vx v16, v16, a0
1677 ; RV64I-NEXT: vsub.vv v8, v8, v16
1678 ; RV64I-NEXT: lui a0, 209715
1679 ; RV64I-NEXT: addiw a0, a0, 819
1680 ; RV64I-NEXT: slli a1, a0, 32
1681 ; RV64I-NEXT: add a0, a0, a1
1682 ; RV64I-NEXT: vand.vx v16, v8, a0
1683 ; RV64I-NEXT: vsrl.vi v8, v8, 2
1684 ; RV64I-NEXT: vand.vx v8, v8, a0
1685 ; RV64I-NEXT: vadd.vv v8, v16, v8
1686 ; RV64I-NEXT: vsrl.vi v16, v8, 4
1687 ; RV64I-NEXT: vadd.vv v8, v8, v16
1688 ; RV64I-NEXT: lui a0, 61681
1689 ; RV64I-NEXT: addiw a0, a0, -241
1690 ; RV64I-NEXT: slli a1, a0, 32
1691 ; RV64I-NEXT: add a0, a0, a1
1692 ; RV64I-NEXT: vand.vx v8, v8, a0
1693 ; RV64I-NEXT: lui a0, 4112
1694 ; RV64I-NEXT: addiw a0, a0, 257
1695 ; RV64I-NEXT: slli a1, a0, 32
1696 ; RV64I-NEXT: add a0, a0, a1
1697 ; RV64I-NEXT: vmul.vx v8, v8, a0
1698 ; RV64I-NEXT: li a0, 56
1699 ; RV64I-NEXT: vsrl.vx v8, v8, a0
1700 ; RV64I-NEXT: ret
1701 ;
1702 ; RV32F-LABEL: cttz_nxv8i64:
1703 ; RV32F: # %bb.0:
1704 ; RV32F-NEXT: vsetvli a0, zero, e64, m8, ta, ma
1705 ; RV32F-NEXT: vmseq.vx v0, v8, zero
1706 ; RV32F-NEXT: vrsub.vi v16, v8, 0
1707 ; RV32F-NEXT: vand.vv v8, v8, v16
1708 ; RV32F-NEXT: fsrmi a0, 1
1709 ; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
1710 ; RV32F-NEXT: vfncvt.f.xu.w v16, v8
1711 ; RV32F-NEXT: vsrl.vi v8, v16, 23
1712 ; RV32F-NEXT: vsetvli zero, zero, e64, m8, ta, ma
1713 ; RV32F-NEXT: vzext.vf2 v16, v8
1714 ; RV32F-NEXT: li a1, 127
1715 ; RV32F-NEXT: vsub.vx v8, v16, a1
1716 ; RV32F-NEXT: li a1, 64
1717 ; RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
1718 ; RV32F-NEXT: fsrm a0
1719 ; RV32F-NEXT: ret
1720 ;
1721 ; RV64F-LABEL: cttz_nxv8i64:
1722 ; RV64F: # %bb.0:
1723 ; RV64F-NEXT: vsetvli a0, zero, e64, m8, ta, ma
1724 ; RV64F-NEXT: vrsub.vi v16, v8, 0
1725 ; RV64F-NEXT: vand.vv v16, v8, v16
1726 ; RV64F-NEXT: fsrmi a0, 1
1727 ; RV64F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
1728 ; RV64F-NEXT: vfncvt.f.xu.w v24, v16
1729 ; RV64F-NEXT: vsrl.vi v16, v24, 23
1730 ; RV64F-NEXT: li a1, 127
1731 ; RV64F-NEXT: vwsubu.vx v24, v16, a1
1732 ; RV64F-NEXT: vsetvli zero, zero, e64, m8, ta, ma
1733 ; RV64F-NEXT: vmseq.vi v0, v8, 0
1734 ; RV64F-NEXT: li a1, 64
1735 ; RV64F-NEXT: vmerge.vxm v8, v24, a1, v0
1736 ; RV64F-NEXT: fsrm a0
1737 ; RV64F-NEXT: ret
1738 ;
1739 ; RV32D-LABEL: cttz_nxv8i64:
1740 ; RV32D: # %bb.0:
1741 ; RV32D-NEXT: vsetvli a0, zero, e64, m8, ta, ma
1742 ; RV32D-NEXT: vmseq.vx v0, v8, zero
1743 ; RV32D-NEXT: vrsub.vi v16, v8, 0
1744 ; RV32D-NEXT: vand.vv v8, v8, v16
1745 ; RV32D-NEXT: fsrmi a0, 1
1746 ; RV32D-NEXT: vfcvt.f.xu.v v8, v8
1747 ; RV32D-NEXT: li a1, 52
1748 ; RV32D-NEXT: vsrl.vx v8, v8, a1
1749 ; RV32D-NEXT: li a1, 1023
1750 ; RV32D-NEXT: vsub.vx v8, v8, a1
1751 ; RV32D-NEXT: li a1, 64
1752 ; RV32D-NEXT: vmerge.vxm v8, v8, a1, v0
1753 ; RV32D-NEXT: fsrm a0
1754 ; RV32D-NEXT: ret
1755 ;
1756 ; RV64D-LABEL: cttz_nxv8i64:
1757 ; RV64D: # %bb.0:
1758 ; RV64D-NEXT: vsetvli a0, zero, e64, m8, ta, ma
1759 ; RV64D-NEXT: vrsub.vi v16, v8, 0
1760 ; RV64D-NEXT: vand.vv v16, v8, v16
1761 ; RV64D-NEXT: fsrmi a0, 1
1762 ; RV64D-NEXT: vfcvt.f.xu.v v16, v16
1763 ; RV64D-NEXT: li a1, 52
1764 ; RV64D-NEXT: vsrl.vx v16, v16, a1
1765 ; RV64D-NEXT: li a1, 1023
1766 ; RV64D-NEXT: vsub.vx v16, v16, a1
1767 ; RV64D-NEXT: vmseq.vi v0, v8, 0
1768 ; RV64D-NEXT: li a1, 64
1769 ; RV64D-NEXT: vmerge.vxm v8, v16, a1, v0
1770 ; RV64D-NEXT: fsrm a0
1771 ; RV64D-NEXT: ret
1772 ;
1773 ; CHECK-ZVBB-LABEL: cttz_nxv8i64:
1774 ; CHECK-ZVBB: # %bb.0:
1775 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
1776 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1777 ; CHECK-ZVBB-NEXT: ret
1778 %a = call <vscale x 8 x i64> @llvm.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 false)
1779 ret <vscale x 8 x i64> %a
1780 }
1781 declare <vscale x 8 x i64> @llvm.cttz.nxv8i64(<vscale x 8 x i64>, i1)
1783 define <vscale x 1 x i8> @cttz_zero_undef_nxv1i8(<vscale x 1 x i8> %va) {
1784 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv1i8:
1785 ; CHECK-ZVE64X: # %bb.0:
1786 ; CHECK-ZVE64X-NEXT: li a0, 1
1787 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
1788 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
1789 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
1790 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
1791 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
1792 ; CHECK-ZVE64X-NEXT: li a0, 85
1793 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
1794 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
1795 ; CHECK-ZVE64X-NEXT: li a0, 51
1796 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
1797 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
1798 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
1799 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
1800 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
1801 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
1802 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
1803 ; CHECK-ZVE64X-NEXT: ret
1804 ;
1805 ; CHECK-F-LABEL: cttz_zero_undef_nxv1i8:
1806 ; CHECK-F: # %bb.0:
1807 ; CHECK-F-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
1808 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
1809 ; CHECK-F-NEXT: vand.vv v8, v8, v9
1810 ; CHECK-F-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
1811 ; CHECK-F-NEXT: vzext.vf2 v9, v8
1812 ; CHECK-F-NEXT: vfwcvt.f.xu.v v8, v9
1813 ; CHECK-F-NEXT: vnsrl.wi v8, v8, 23
1814 ; CHECK-F-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
1815 ; CHECK-F-NEXT: vnsrl.wi v8, v8, 0
1816 ; CHECK-F-NEXT: li a0, 127
1817 ; CHECK-F-NEXT: vsub.vx v8, v8, a0
1818 ; CHECK-F-NEXT: ret
1819 ;
1820 ; CHECK-D-LABEL: cttz_zero_undef_nxv1i8:
1821 ; CHECK-D: # %bb.0:
1822 ; CHECK-D-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
1823 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
1824 ; CHECK-D-NEXT: vand.vv v8, v8, v9
1825 ; CHECK-D-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
1826 ; CHECK-D-NEXT: vzext.vf2 v9, v8
1827 ; CHECK-D-NEXT: vfwcvt.f.xu.v v8, v9
1828 ; CHECK-D-NEXT: vnsrl.wi v8, v8, 23
1829 ; CHECK-D-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
1830 ; CHECK-D-NEXT: vnsrl.wi v8, v8, 0
1831 ; CHECK-D-NEXT: li a0, 127
1832 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
1833 ; CHECK-D-NEXT: ret
1834 ;
1835 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv1i8:
1836 ; CHECK-ZVBB: # %bb.0:
1837 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
1838 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1839 ; CHECK-ZVBB-NEXT: ret
1840 %a = call <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 true)
1841 ret <vscale x 1 x i8> %a
1842 }
1844 define <vscale x 2 x i8> @cttz_zero_undef_nxv2i8(<vscale x 2 x i8> %va) {
1845 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv2i8:
1846 ; CHECK-ZVE64X: # %bb.0:
1847 ; CHECK-ZVE64X-NEXT: li a0, 1
1848 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
1849 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
1850 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
1851 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
1852 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
1853 ; CHECK-ZVE64X-NEXT: li a0, 85
1854 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
1855 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
1856 ; CHECK-ZVE64X-NEXT: li a0, 51
1857 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
1858 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
1859 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
1860 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
1861 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
1862 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
1863 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
1864 ; CHECK-ZVE64X-NEXT: ret
1865 ;
1866 ; CHECK-F-LABEL: cttz_zero_undef_nxv2i8:
1867 ; CHECK-F: # %bb.0:
1868 ; CHECK-F-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
1869 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
1870 ; CHECK-F-NEXT: vand.vv v8, v8, v9
1871 ; CHECK-F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
1872 ; CHECK-F-NEXT: vzext.vf2 v9, v8
1873 ; CHECK-F-NEXT: vfwcvt.f.xu.v v8, v9
1874 ; CHECK-F-NEXT: vnsrl.wi v8, v8, 23
1875 ; CHECK-F-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
1876 ; CHECK-F-NEXT: vnsrl.wi v8, v8, 0
1877 ; CHECK-F-NEXT: li a0, 127
1878 ; CHECK-F-NEXT: vsub.vx v8, v8, a0
1879 ; CHECK-F-NEXT: ret
1880 ;
1881 ; CHECK-D-LABEL: cttz_zero_undef_nxv2i8:
1882 ; CHECK-D: # %bb.0:
1883 ; CHECK-D-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
1884 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
1885 ; CHECK-D-NEXT: vand.vv v8, v8, v9
1886 ; CHECK-D-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
1887 ; CHECK-D-NEXT: vzext.vf2 v9, v8
1888 ; CHECK-D-NEXT: vfwcvt.f.xu.v v8, v9
1889 ; CHECK-D-NEXT: vnsrl.wi v8, v8, 23
1890 ; CHECK-D-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
1891 ; CHECK-D-NEXT: vnsrl.wi v8, v8, 0
1892 ; CHECK-D-NEXT: li a0, 127
1893 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
1894 ; CHECK-D-NEXT: ret
1895 ;
1896 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv2i8:
1897 ; CHECK-ZVBB: # %bb.0:
1898 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
1899 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1900 ; CHECK-ZVBB-NEXT: ret
1901 %a = call <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 true)
1902 ret <vscale x 2 x i8> %a
1903 }
1905 define <vscale x 4 x i8> @cttz_zero_undef_nxv4i8(<vscale x 4 x i8> %va) {
1906 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv4i8:
1907 ; CHECK-ZVE64X: # %bb.0:
1908 ; CHECK-ZVE64X-NEXT: li a0, 1
1909 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
1910 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
1911 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
1912 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
1913 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
1914 ; CHECK-ZVE64X-NEXT: li a0, 85
1915 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
1916 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
1917 ; CHECK-ZVE64X-NEXT: li a0, 51
1918 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
1919 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
1920 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
1921 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
1922 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
1923 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
1924 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
1925 ; CHECK-ZVE64X-NEXT: ret
1926 ;
1927 ; CHECK-F-LABEL: cttz_zero_undef_nxv4i8:
1928 ; CHECK-F: # %bb.0:
1929 ; CHECK-F-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
1930 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
1931 ; CHECK-F-NEXT: vand.vv v8, v8, v9
1932 ; CHECK-F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
1933 ; CHECK-F-NEXT: vzext.vf2 v9, v8
1934 ; CHECK-F-NEXT: vfwcvt.f.xu.v v10, v9
1935 ; CHECK-F-NEXT: vnsrl.wi v8, v10, 23
1936 ; CHECK-F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
1937 ; CHECK-F-NEXT: vnsrl.wi v8, v8, 0
1938 ; CHECK-F-NEXT: li a0, 127
1939 ; CHECK-F-NEXT: vsub.vx v8, v8, a0
1940 ; CHECK-F-NEXT: ret
1941 ;
1942 ; CHECK-D-LABEL: cttz_zero_undef_nxv4i8:
1943 ; CHECK-D: # %bb.0:
1944 ; CHECK-D-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
1945 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
1946 ; CHECK-D-NEXT: vand.vv v8, v8, v9
1947 ; CHECK-D-NEXT: vsetvli zero, zero, e16, m1, ta, ma
1948 ; CHECK-D-NEXT: vzext.vf2 v9, v8
1949 ; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v9
1950 ; CHECK-D-NEXT: vnsrl.wi v8, v10, 23
1951 ; CHECK-D-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
1952 ; CHECK-D-NEXT: vnsrl.wi v8, v8, 0
1953 ; CHECK-D-NEXT: li a0, 127
1954 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
1955 ; CHECK-D-NEXT: ret
1956 ;
1957 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv4i8:
1958 ; CHECK-ZVBB: # %bb.0:
1959 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
1960 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1961 ; CHECK-ZVBB-NEXT: ret
1962 %a = call <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 true)
1963 ret <vscale x 4 x i8> %a
1964 }
1966 define <vscale x 8 x i8> @cttz_zero_undef_nxv8i8(<vscale x 8 x i8> %va) {
1967 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv8i8:
1968 ; CHECK-ZVE64X: # %bb.0:
1969 ; CHECK-ZVE64X-NEXT: li a0, 1
1970 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, m1, ta, ma
1971 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
1972 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
1973 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
1974 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
1975 ; CHECK-ZVE64X-NEXT: li a0, 85
1976 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
1977 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
1978 ; CHECK-ZVE64X-NEXT: li a0, 51
1979 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
1980 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
1981 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
1982 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
1983 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
1984 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
1985 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
1986 ; CHECK-ZVE64X-NEXT: ret
1987 ;
1988 ; CHECK-F-LABEL: cttz_zero_undef_nxv8i8:
1989 ; CHECK-F: # %bb.0:
1990 ; CHECK-F-NEXT: vsetvli a0, zero, e8, m1, ta, ma
1991 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
1992 ; CHECK-F-NEXT: vand.vv v8, v8, v9
1993 ; CHECK-F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
1994 ; CHECK-F-NEXT: vzext.vf2 v10, v8
1995 ; CHECK-F-NEXT: vfwcvt.f.xu.v v12, v10
1996 ; CHECK-F-NEXT: vnsrl.wi v8, v12, 23
1997 ; CHECK-F-NEXT: vsetvli zero, zero, e8, m1, ta, ma
1998 ; CHECK-F-NEXT: vnsrl.wi v10, v8, 0
1999 ; CHECK-F-NEXT: li a0, 127
2000 ; CHECK-F-NEXT: vsub.vx v8, v10, a0
2001 ; CHECK-F-NEXT: ret
2002 ;
2003 ; CHECK-D-LABEL: cttz_zero_undef_nxv8i8:
2004 ; CHECK-D: # %bb.0:
2005 ; CHECK-D-NEXT: vsetvli a0, zero, e8, m1, ta, ma
2006 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
2007 ; CHECK-D-NEXT: vand.vv v8, v8, v9
2008 ; CHECK-D-NEXT: vsetvli zero, zero, e16, m2, ta, ma
2009 ; CHECK-D-NEXT: vzext.vf2 v10, v8
2010 ; CHECK-D-NEXT: vfwcvt.f.xu.v v12, v10
2011 ; CHECK-D-NEXT: vnsrl.wi v8, v12, 23
2012 ; CHECK-D-NEXT: vsetvli zero, zero, e8, m1, ta, ma
2013 ; CHECK-D-NEXT: vnsrl.wi v10, v8, 0
2014 ; CHECK-D-NEXT: li a0, 127
2015 ; CHECK-D-NEXT: vsub.vx v8, v10, a0
2016 ; CHECK-D-NEXT: ret
2017 ;
2018 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv8i8:
2019 ; CHECK-ZVBB: # %bb.0:
2020 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
2021 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2022 ; CHECK-ZVBB-NEXT: ret
2023 %a = call <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 true)
2024 ret <vscale x 8 x i8> %a
2025 }
2027 define <vscale x 16 x i8> @cttz_zero_undef_nxv16i8(<vscale x 16 x i8> %va) {
2028 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv16i8:
2029 ; CHECK-ZVE64X: # %bb.0:
2030 ; CHECK-ZVE64X-NEXT: li a0, 1
2031 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, m2, ta, ma
2032 ; CHECK-ZVE64X-NEXT: vsub.vx v10, v8, a0
2033 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2034 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v10
2035 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
2036 ; CHECK-ZVE64X-NEXT: li a0, 85
2037 ; CHECK-ZVE64X-NEXT: vand.vx v10, v10, a0
2038 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v10
2039 ; CHECK-ZVE64X-NEXT: li a0, 51
2040 ; CHECK-ZVE64X-NEXT: vand.vx v10, v8, a0
2041 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2042 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2043 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v10, v8
2044 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 4
2045 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v10
2046 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
2047 ; CHECK-ZVE64X-NEXT: ret
2048 ;
2049 ; CHECK-F-LABEL: cttz_zero_undef_nxv16i8:
2050 ; CHECK-F: # %bb.0:
2051 ; CHECK-F-NEXT: vsetvli a0, zero, e8, m2, ta, ma
2052 ; CHECK-F-NEXT: vrsub.vi v10, v8, 0
2053 ; CHECK-F-NEXT: vand.vv v8, v8, v10
2054 ; CHECK-F-NEXT: vsetvli zero, zero, e16, m4, ta, ma
2055 ; CHECK-F-NEXT: vzext.vf2 v12, v8
2056 ; CHECK-F-NEXT: vfwcvt.f.xu.v v16, v12
2057 ; CHECK-F-NEXT: vnsrl.wi v8, v16, 23
2058 ; CHECK-F-NEXT: vsetvli zero, zero, e8, m2, ta, ma
2059 ; CHECK-F-NEXT: vnsrl.wi v12, v8, 0
2060 ; CHECK-F-NEXT: li a0, 127
2061 ; CHECK-F-NEXT: vsub.vx v8, v12, a0
2062 ; CHECK-F-NEXT: ret
2063 ;
2064 ; CHECK-D-LABEL: cttz_zero_undef_nxv16i8:
2065 ; CHECK-D: # %bb.0:
2066 ; CHECK-D-NEXT: vsetvli a0, zero, e8, m2, ta, ma
2067 ; CHECK-D-NEXT: vrsub.vi v10, v8, 0
2068 ; CHECK-D-NEXT: vand.vv v8, v8, v10
2069 ; CHECK-D-NEXT: vsetvli zero, zero, e16, m4, ta, ma
2070 ; CHECK-D-NEXT: vzext.vf2 v12, v8
2071 ; CHECK-D-NEXT: vfwcvt.f.xu.v v16, v12
2072 ; CHECK-D-NEXT: vnsrl.wi v8, v16, 23
2073 ; CHECK-D-NEXT: vsetvli zero, zero, e8, m2, ta, ma
2074 ; CHECK-D-NEXT: vnsrl.wi v12, v8, 0
2075 ; CHECK-D-NEXT: li a0, 127
2076 ; CHECK-D-NEXT: vsub.vx v8, v12, a0
2077 ; CHECK-D-NEXT: ret
2078 ;
2079 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv16i8:
2080 ; CHECK-ZVBB: # %bb.0:
2081 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
2082 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2083 ; CHECK-ZVBB-NEXT: ret
2084 %a = call <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 true)
2085 ret <vscale x 16 x i8> %a
2086 }
2088 define <vscale x 32 x i8> @cttz_zero_undef_nxv32i8(<vscale x 32 x i8> %va) {
2089 ; CHECK-LABEL: cttz_zero_undef_nxv32i8:
2090 ; CHECK: # %bb.0:
2091 ; CHECK-NEXT: li a0, 1
2092 ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
2093 ; CHECK-NEXT: vsub.vx v12, v8, a0
2094 ; CHECK-NEXT: vnot.v v8, v8
2095 ; CHECK-NEXT: vand.vv v8, v8, v12
2096 ; CHECK-NEXT: vsrl.vi v12, v8, 1
2097 ; CHECK-NEXT: li a0, 85
2098 ; CHECK-NEXT: vand.vx v12, v12, a0
2099 ; CHECK-NEXT: vsub.vv v8, v8, v12
2100 ; CHECK-NEXT: li a0, 51
2101 ; CHECK-NEXT: vand.vx v12, v8, a0
2102 ; CHECK-NEXT: vsrl.vi v8, v8, 2
2103 ; CHECK-NEXT: vand.vx v8, v8, a0
2104 ; CHECK-NEXT: vadd.vv v8, v12, v8
2105 ; CHECK-NEXT: vsrl.vi v12, v8, 4
2106 ; CHECK-NEXT: vadd.vv v8, v8, v12
2107 ; CHECK-NEXT: vand.vi v8, v8, 15
2108 ; CHECK-NEXT: ret
2109 ;
2110 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv32i8:
2111 ; CHECK-ZVBB: # %bb.0:
2112 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m4, ta, ma
2113 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2114 ; CHECK-ZVBB-NEXT: ret
2115 %a = call <vscale x 32 x i8> @llvm.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 true)
2116 ret <vscale x 32 x i8> %a
2117 }
2119 define <vscale x 64 x i8> @cttz_zero_undef_nxv64i8(<vscale x 64 x i8> %va) {
2120 ; CHECK-LABEL: cttz_zero_undef_nxv64i8:
2121 ; CHECK: # %bb.0:
2122 ; CHECK-NEXT: li a0, 1
2123 ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
2124 ; CHECK-NEXT: vsub.vx v16, v8, a0
2125 ; CHECK-NEXT: vnot.v v8, v8
2126 ; CHECK-NEXT: vand.vv v8, v8, v16
2127 ; CHECK-NEXT: vsrl.vi v16, v8, 1
2128 ; CHECK-NEXT: li a0, 85
2129 ; CHECK-NEXT: vand.vx v16, v16, a0
2130 ; CHECK-NEXT: vsub.vv v8, v8, v16
2131 ; CHECK-NEXT: li a0, 51
2132 ; CHECK-NEXT: vand.vx v16, v8, a0
2133 ; CHECK-NEXT: vsrl.vi v8, v8, 2
2134 ; CHECK-NEXT: vand.vx v8, v8, a0
2135 ; CHECK-NEXT: vadd.vv v8, v16, v8
2136 ; CHECK-NEXT: vsrl.vi v16, v8, 4
2137 ; CHECK-NEXT: vadd.vv v8, v8, v16
2138 ; CHECK-NEXT: vand.vi v8, v8, 15
2139 ; CHECK-NEXT: ret
2140 ;
2141 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv64i8:
2142 ; CHECK-ZVBB: # %bb.0:
2143 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m8, ta, ma
2144 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2145 ; CHECK-ZVBB-NEXT: ret
2146 %a = call <vscale x 64 x i8> @llvm.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 true)
2147 ret <vscale x 64 x i8> %a
2148 }
2150 define <vscale x 1 x i16> @cttz_zero_undef_nxv1i16(<vscale x 1 x i16> %va) {
2151 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv1i16:
2152 ; CHECK-ZVE64X: # %bb.0:
2153 ; CHECK-ZVE64X-NEXT: li a0, 1
2154 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
2155 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
2156 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2157 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
2158 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
2159 ; CHECK-ZVE64X-NEXT: lui a0, 5
2160 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2161 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
2162 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
2163 ; CHECK-ZVE64X-NEXT: lui a0, 3
2164 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2165 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
2166 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2167 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2168 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
2169 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
2170 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
2171 ; CHECK-ZVE64X-NEXT: lui a0, 1
2172 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2173 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2174 ; CHECK-ZVE64X-NEXT: li a0, 257
2175 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2176 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
2177 ; CHECK-ZVE64X-NEXT: ret
2178 ;
2179 ; CHECK-F-LABEL: cttz_zero_undef_nxv1i16:
2180 ; CHECK-F: # %bb.0:
2181 ; CHECK-F-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
2182 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
2183 ; CHECK-F-NEXT: vand.vv v8, v8, v9
2184 ; CHECK-F-NEXT: vfwcvt.f.xu.v v9, v8
2185 ; CHECK-F-NEXT: vnsrl.wi v8, v9, 23
2186 ; CHECK-F-NEXT: li a0, 127
2187 ; CHECK-F-NEXT: vsub.vx v8, v8, a0
2188 ; CHECK-F-NEXT: ret
2189 ;
2190 ; CHECK-D-LABEL: cttz_zero_undef_nxv1i16:
2191 ; CHECK-D: # %bb.0:
2192 ; CHECK-D-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
2193 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
2194 ; CHECK-D-NEXT: vand.vv v8, v8, v9
2195 ; CHECK-D-NEXT: vfwcvt.f.xu.v v9, v8
2196 ; CHECK-D-NEXT: vnsrl.wi v8, v9, 23
2197 ; CHECK-D-NEXT: li a0, 127
2198 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
2199 ; CHECK-D-NEXT: ret
2200 ;
2201 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv1i16:
2202 ; CHECK-ZVBB: # %bb.0:
2203 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
2204 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2205 ; CHECK-ZVBB-NEXT: ret
2206 %a = call <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 true)
2207 ret <vscale x 1 x i16> %a
2208 }
2210 define <vscale x 2 x i16> @cttz_zero_undef_nxv2i16(<vscale x 2 x i16> %va) {
2211 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv2i16:
2212 ; CHECK-ZVE64X: # %bb.0:
2213 ; CHECK-ZVE64X-NEXT: li a0, 1
2214 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
2215 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
2216 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2217 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
2218 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
2219 ; CHECK-ZVE64X-NEXT: lui a0, 5
2220 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2221 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
2222 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
2223 ; CHECK-ZVE64X-NEXT: lui a0, 3
2224 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2225 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
2226 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2227 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2228 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
2229 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
2230 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
2231 ; CHECK-ZVE64X-NEXT: lui a0, 1
2232 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2233 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2234 ; CHECK-ZVE64X-NEXT: li a0, 257
2235 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2236 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
2237 ; CHECK-ZVE64X-NEXT: ret
2238 ;
2239 ; CHECK-F-LABEL: cttz_zero_undef_nxv2i16:
2240 ; CHECK-F: # %bb.0:
2241 ; CHECK-F-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
2242 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
2243 ; CHECK-F-NEXT: vand.vv v8, v8, v9
2244 ; CHECK-F-NEXT: vfwcvt.f.xu.v v9, v8
2245 ; CHECK-F-NEXT: vnsrl.wi v8, v9, 23
2246 ; CHECK-F-NEXT: li a0, 127
2247 ; CHECK-F-NEXT: vsub.vx v8, v8, a0
2248 ; CHECK-F-NEXT: ret
2249 ;
2250 ; CHECK-D-LABEL: cttz_zero_undef_nxv2i16:
2251 ; CHECK-D: # %bb.0:
2252 ; CHECK-D-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
2253 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
2254 ; CHECK-D-NEXT: vand.vv v8, v8, v9
2255 ; CHECK-D-NEXT: vfwcvt.f.xu.v v9, v8
2256 ; CHECK-D-NEXT: vnsrl.wi v8, v9, 23
2257 ; CHECK-D-NEXT: li a0, 127
2258 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
2259 ; CHECK-D-NEXT: ret
2260 ;
2261 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv2i16:
2262 ; CHECK-ZVBB: # %bb.0:
2263 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
2264 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2265 ; CHECK-ZVBB-NEXT: ret
2266 %a = call <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 true)
2267 ret <vscale x 2 x i16> %a
2268 }
2270 define <vscale x 4 x i16> @cttz_zero_undef_nxv4i16(<vscale x 4 x i16> %va) {
2271 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv4i16:
2272 ; CHECK-ZVE64X: # %bb.0:
2273 ; CHECK-ZVE64X-NEXT: li a0, 1
2274 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, m1, ta, ma
2275 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
2276 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2277 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
2278 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
2279 ; CHECK-ZVE64X-NEXT: lui a0, 5
2280 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2281 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
2282 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
2283 ; CHECK-ZVE64X-NEXT: lui a0, 3
2284 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2285 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
2286 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2287 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2288 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
2289 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
2290 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
2291 ; CHECK-ZVE64X-NEXT: lui a0, 1
2292 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2293 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2294 ; CHECK-ZVE64X-NEXT: li a0, 257
2295 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2296 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
2297 ; CHECK-ZVE64X-NEXT: ret
2298 ;
2299 ; CHECK-F-LABEL: cttz_zero_undef_nxv4i16:
2300 ; CHECK-F: # %bb.0:
2301 ; CHECK-F-NEXT: vsetvli a0, zero, e16, m1, ta, ma
2302 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
2303 ; CHECK-F-NEXT: vand.vv v8, v8, v9
2304 ; CHECK-F-NEXT: vfwcvt.f.xu.v v10, v8
2305 ; CHECK-F-NEXT: vnsrl.wi v8, v10, 23
2306 ; CHECK-F-NEXT: li a0, 127
2307 ; CHECK-F-NEXT: vsub.vx v8, v8, a0
2308 ; CHECK-F-NEXT: ret
2309 ;
2310 ; CHECK-D-LABEL: cttz_zero_undef_nxv4i16:
2311 ; CHECK-D: # %bb.0:
2312 ; CHECK-D-NEXT: vsetvli a0, zero, e16, m1, ta, ma
2313 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
2314 ; CHECK-D-NEXT: vand.vv v8, v8, v9
2315 ; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v8
2316 ; CHECK-D-NEXT: vnsrl.wi v8, v10, 23
2317 ; CHECK-D-NEXT: li a0, 127
2318 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
2319 ; CHECK-D-NEXT: ret
2320 ;
2321 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv4i16:
2322 ; CHECK-ZVBB: # %bb.0:
2323 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
2324 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2325 ; CHECK-ZVBB-NEXT: ret
2326 %a = call <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 true)
2327 ret <vscale x 4 x i16> %a
2328 }
2330 define <vscale x 8 x i16> @cttz_zero_undef_nxv8i16(<vscale x 8 x i16> %va) {
2331 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv8i16:
2332 ; CHECK-ZVE64X: # %bb.0:
2333 ; CHECK-ZVE64X-NEXT: li a0, 1
2334 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, m2, ta, ma
2335 ; CHECK-ZVE64X-NEXT: vsub.vx v10, v8, a0
2336 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2337 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v10
2338 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
2339 ; CHECK-ZVE64X-NEXT: lui a0, 5
2340 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2341 ; CHECK-ZVE64X-NEXT: vand.vx v10, v10, a0
2342 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v10
2343 ; CHECK-ZVE64X-NEXT: lui a0, 3
2344 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2345 ; CHECK-ZVE64X-NEXT: vand.vx v10, v8, a0
2346 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2347 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2348 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v10, v8
2349 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 4
2350 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v10
2351 ; CHECK-ZVE64X-NEXT: lui a0, 1
2352 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2353 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2354 ; CHECK-ZVE64X-NEXT: li a0, 257
2355 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2356 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
2357 ; CHECK-ZVE64X-NEXT: ret
2358 ;
2359 ; CHECK-F-LABEL: cttz_zero_undef_nxv8i16:
2360 ; CHECK-F: # %bb.0:
2361 ; CHECK-F-NEXT: vsetvli a0, zero, e16, m2, ta, ma
2362 ; CHECK-F-NEXT: vrsub.vi v10, v8, 0
2363 ; CHECK-F-NEXT: vand.vv v8, v8, v10
2364 ; CHECK-F-NEXT: vfwcvt.f.xu.v v12, v8
2365 ; CHECK-F-NEXT: vnsrl.wi v8, v12, 23
2366 ; CHECK-F-NEXT: li a0, 127
2367 ; CHECK-F-NEXT: vsub.vx v8, v8, a0
2368 ; CHECK-F-NEXT: ret
2369 ;
2370 ; CHECK-D-LABEL: cttz_zero_undef_nxv8i16:
2371 ; CHECK-D: # %bb.0:
2372 ; CHECK-D-NEXT: vsetvli a0, zero, e16, m2, ta, ma
2373 ; CHECK-D-NEXT: vrsub.vi v10, v8, 0
2374 ; CHECK-D-NEXT: vand.vv v8, v8, v10
2375 ; CHECK-D-NEXT: vfwcvt.f.xu.v v12, v8
2376 ; CHECK-D-NEXT: vnsrl.wi v8, v12, 23
2377 ; CHECK-D-NEXT: li a0, 127
2378 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
2379 ; CHECK-D-NEXT: ret
2380 ;
2381 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv8i16:
2382 ; CHECK-ZVBB: # %bb.0:
2383 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma
2384 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2385 ; CHECK-ZVBB-NEXT: ret
2386 %a = call <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 true)
2387 ret <vscale x 8 x i16> %a
2388 }
2390 define <vscale x 16 x i16> @cttz_zero_undef_nxv16i16(<vscale x 16 x i16> %va) {
2391 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv16i16:
2392 ; CHECK-ZVE64X: # %bb.0:
2393 ; CHECK-ZVE64X-NEXT: li a0, 1
2394 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, m4, ta, ma
2395 ; CHECK-ZVE64X-NEXT: vsub.vx v12, v8, a0
2396 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2397 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v12
2398 ; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 1
2399 ; CHECK-ZVE64X-NEXT: lui a0, 5
2400 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2401 ; CHECK-ZVE64X-NEXT: vand.vx v12, v12, a0
2402 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v12
2403 ; CHECK-ZVE64X-NEXT: lui a0, 3
2404 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2405 ; CHECK-ZVE64X-NEXT: vand.vx v12, v8, a0
2406 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2407 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2408 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v12, v8
2409 ; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 4
2410 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v12
2411 ; CHECK-ZVE64X-NEXT: lui a0, 1
2412 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2413 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2414 ; CHECK-ZVE64X-NEXT: li a0, 257
2415 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2416 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
2417 ; CHECK-ZVE64X-NEXT: ret
2418 ;
2419 ; CHECK-F-LABEL: cttz_zero_undef_nxv16i16:
2420 ; CHECK-F: # %bb.0:
2421 ; CHECK-F-NEXT: vsetvli a0, zero, e16, m4, ta, ma
2422 ; CHECK-F-NEXT: vrsub.vi v12, v8, 0
2423 ; CHECK-F-NEXT: vand.vv v8, v8, v12
2424 ; CHECK-F-NEXT: vfwcvt.f.xu.v v16, v8
2425 ; CHECK-F-NEXT: vnsrl.wi v8, v16, 23
2426 ; CHECK-F-NEXT: li a0, 127
2427 ; CHECK-F-NEXT: vsub.vx v8, v8, a0
2428 ; CHECK-F-NEXT: ret
2429 ;
2430 ; CHECK-D-LABEL: cttz_zero_undef_nxv16i16:
2431 ; CHECK-D: # %bb.0:
2432 ; CHECK-D-NEXT: vsetvli a0, zero, e16, m4, ta, ma
2433 ; CHECK-D-NEXT: vrsub.vi v12, v8, 0
2434 ; CHECK-D-NEXT: vand.vv v8, v8, v12
2435 ; CHECK-D-NEXT: vfwcvt.f.xu.v v16, v8
2436 ; CHECK-D-NEXT: vnsrl.wi v8, v16, 23
2437 ; CHECK-D-NEXT: li a0, 127
2438 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
2439 ; CHECK-D-NEXT: ret
2440 ;
2441 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv16i16:
2442 ; CHECK-ZVBB: # %bb.0:
2443 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma
2444 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2445 ; CHECK-ZVBB-NEXT: ret
2446 %a = call <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 true)
2447 ret <vscale x 16 x i16> %a
2448 }
2450 define <vscale x 32 x i16> @cttz_zero_undef_nxv32i16(<vscale x 32 x i16> %va) {
2451 ; CHECK-LABEL: cttz_zero_undef_nxv32i16:
2452 ; CHECK: # %bb.0:
2453 ; CHECK-NEXT: li a0, 1
2454 ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
2455 ; CHECK-NEXT: vsub.vx v16, v8, a0
2456 ; CHECK-NEXT: vnot.v v8, v8
2457 ; CHECK-NEXT: vand.vv v8, v8, v16
2458 ; CHECK-NEXT: vsrl.vi v16, v8, 1
2459 ; CHECK-NEXT: lui a0, 5
2460 ; CHECK-NEXT: addi a0, a0, 1365
2461 ; CHECK-NEXT: vand.vx v16, v16, a0
2462 ; CHECK-NEXT: vsub.vv v8, v8, v16
2463 ; CHECK-NEXT: lui a0, 3
2464 ; CHECK-NEXT: addi a0, a0, 819
2465 ; CHECK-NEXT: vand.vx v16, v8, a0
2466 ; CHECK-NEXT: vsrl.vi v8, v8, 2
2467 ; CHECK-NEXT: vand.vx v8, v8, a0
2468 ; CHECK-NEXT: vadd.vv v8, v16, v8
2469 ; CHECK-NEXT: vsrl.vi v16, v8, 4
2470 ; CHECK-NEXT: vadd.vv v8, v8, v16
2471 ; CHECK-NEXT: lui a0, 1
2472 ; CHECK-NEXT: addi a0, a0, -241
2473 ; CHECK-NEXT: vand.vx v8, v8, a0
2474 ; CHECK-NEXT: li a0, 257
2475 ; CHECK-NEXT: vmul.vx v8, v8, a0
2476 ; CHECK-NEXT: vsrl.vi v8, v8, 8
2477 ; CHECK-NEXT: ret
2478 ;
2479 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv32i16:
2480 ; CHECK-ZVBB: # %bb.0:
2481 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m8, ta, ma
2482 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2483 ; CHECK-ZVBB-NEXT: ret
2484 %a = call <vscale x 32 x i16> @llvm.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 true)
2485 ret <vscale x 32 x i16> %a
2486 }
2488 define <vscale x 1 x i32> @cttz_zero_undef_nxv1i32(<vscale x 1 x i32> %va) {
2489 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv1i32:
2490 ; CHECK-ZVE64X: # %bb.0:
2491 ; CHECK-ZVE64X-NEXT: li a0, 1
2492 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
2493 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
2494 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2495 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
2496 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
2497 ; CHECK-ZVE64X-NEXT: lui a0, 349525
2498 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2499 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
2500 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
2501 ; CHECK-ZVE64X-NEXT: lui a0, 209715
2502 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2503 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
2504 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2505 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2506 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
2507 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
2508 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
2509 ; CHECK-ZVE64X-NEXT: lui a0, 61681
2510 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2511 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2512 ; CHECK-ZVE64X-NEXT: lui a0, 4112
2513 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
2514 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2515 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
2516 ; CHECK-ZVE64X-NEXT: ret
2517 ;
2518 ; CHECK-F-LABEL: cttz_zero_undef_nxv1i32:
2519 ; CHECK-F: # %bb.0:
2520 ; CHECK-F-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
2521 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
2522 ; CHECK-F-NEXT: vand.vv v8, v8, v9
2523 ; CHECK-F-NEXT: fsrmi a0, 1
2524 ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
2525 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23
2526 ; CHECK-F-NEXT: li a1, 127
2527 ; CHECK-F-NEXT: vsub.vx v8, v8, a1
2528 ; CHECK-F-NEXT: fsrm a0
2529 ; CHECK-F-NEXT: ret
2530 ;
2531 ; CHECK-D-LABEL: cttz_zero_undef_nxv1i32:
2532 ; CHECK-D: # %bb.0:
2533 ; CHECK-D-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
2534 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
2535 ; CHECK-D-NEXT: vand.vv v8, v8, v9
2536 ; CHECK-D-NEXT: vfwcvt.f.xu.v v9, v8
2537 ; CHECK-D-NEXT: li a0, 52
2538 ; CHECK-D-NEXT: vnsrl.wx v8, v9, a0
2539 ; CHECK-D-NEXT: li a0, 1023
2540 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
2541 ; CHECK-D-NEXT: ret
2542 ;
2543 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv1i32:
2544 ; CHECK-ZVBB: # %bb.0:
2545 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
2546 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2547 ; CHECK-ZVBB-NEXT: ret
2548 %a = call <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 true)
2549 ret <vscale x 1 x i32> %a
2550 }
2552 define <vscale x 2 x i32> @cttz_zero_undef_nxv2i32(<vscale x 2 x i32> %va) {
2553 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv2i32:
2554 ; CHECK-ZVE64X: # %bb.0:
2555 ; CHECK-ZVE64X-NEXT: li a0, 1
2556 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m1, ta, ma
2557 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
2558 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2559 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
2560 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
2561 ; CHECK-ZVE64X-NEXT: lui a0, 349525
2562 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2563 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
2564 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
2565 ; CHECK-ZVE64X-NEXT: lui a0, 209715
2566 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2567 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
2568 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2569 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2570 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
2571 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
2572 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
2573 ; CHECK-ZVE64X-NEXT: lui a0, 61681
2574 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2575 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2576 ; CHECK-ZVE64X-NEXT: lui a0, 4112
2577 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
2578 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2579 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
2580 ; CHECK-ZVE64X-NEXT: ret
2581 ;
2582 ; CHECK-F-LABEL: cttz_zero_undef_nxv2i32:
2583 ; CHECK-F: # %bb.0:
2584 ; CHECK-F-NEXT: vsetvli a0, zero, e32, m1, ta, ma
2585 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
2586 ; CHECK-F-NEXT: vand.vv v8, v8, v9
2587 ; CHECK-F-NEXT: fsrmi a0, 1
2588 ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
2589 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23
2590 ; CHECK-F-NEXT: li a1, 127
2591 ; CHECK-F-NEXT: vsub.vx v8, v8, a1
2592 ; CHECK-F-NEXT: fsrm a0
2593 ; CHECK-F-NEXT: ret
2594 ;
2595 ; CHECK-D-LABEL: cttz_zero_undef_nxv2i32:
2596 ; CHECK-D: # %bb.0:
2597 ; CHECK-D-NEXT: vsetvli a0, zero, e32, m1, ta, ma
2598 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
2599 ; CHECK-D-NEXT: vand.vv v8, v8, v9
2600 ; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v8
2601 ; CHECK-D-NEXT: li a0, 52
2602 ; CHECK-D-NEXT: vnsrl.wx v8, v10, a0
2603 ; CHECK-D-NEXT: li a0, 1023
2604 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
2605 ; CHECK-D-NEXT: ret
2606 ;
2607 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv2i32:
2608 ; CHECK-ZVBB: # %bb.0:
2609 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
2610 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2611 ; CHECK-ZVBB-NEXT: ret
2612 %a = call <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 true)
2613 ret <vscale x 2 x i32> %a
2614 }
2616 define <vscale x 4 x i32> @cttz_zero_undef_nxv4i32(<vscale x 4 x i32> %va) {
2617 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv4i32:
2618 ; CHECK-ZVE64X: # %bb.0:
2619 ; CHECK-ZVE64X-NEXT: li a0, 1
2620 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m2, ta, ma
2621 ; CHECK-ZVE64X-NEXT: vsub.vx v10, v8, a0
2622 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2623 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v10
2624 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
2625 ; CHECK-ZVE64X-NEXT: lui a0, 349525
2626 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2627 ; CHECK-ZVE64X-NEXT: vand.vx v10, v10, a0
2628 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v10
2629 ; CHECK-ZVE64X-NEXT: lui a0, 209715
2630 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2631 ; CHECK-ZVE64X-NEXT: vand.vx v10, v8, a0
2632 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2633 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2634 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v10, v8
2635 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 4
2636 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v10
2637 ; CHECK-ZVE64X-NEXT: lui a0, 61681
2638 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2639 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2640 ; CHECK-ZVE64X-NEXT: lui a0, 4112
2641 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
2642 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2643 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
2644 ; CHECK-ZVE64X-NEXT: ret
2645 ;
2646 ; CHECK-F-LABEL: cttz_zero_undef_nxv4i32:
2647 ; CHECK-F: # %bb.0:
2648 ; CHECK-F-NEXT: vsetvli a0, zero, e32, m2, ta, ma
2649 ; CHECK-F-NEXT: vrsub.vi v10, v8, 0
2650 ; CHECK-F-NEXT: vand.vv v8, v8, v10
2651 ; CHECK-F-NEXT: fsrmi a0, 1
2652 ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
2653 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23
2654 ; CHECK-F-NEXT: li a1, 127
2655 ; CHECK-F-NEXT: vsub.vx v8, v8, a1
2656 ; CHECK-F-NEXT: fsrm a0
2657 ; CHECK-F-NEXT: ret
2658 ;
2659 ; CHECK-D-LABEL: cttz_zero_undef_nxv4i32:
2660 ; CHECK-D: # %bb.0:
2661 ; CHECK-D-NEXT: vsetvli a0, zero, e32, m2, ta, ma
2662 ; CHECK-D-NEXT: vrsub.vi v10, v8, 0
2663 ; CHECK-D-NEXT: vand.vv v8, v8, v10
2664 ; CHECK-D-NEXT: vfwcvt.f.xu.v v12, v8
2665 ; CHECK-D-NEXT: li a0, 52
2666 ; CHECK-D-NEXT: vnsrl.wx v8, v12, a0
2667 ; CHECK-D-NEXT: li a0, 1023
2668 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
2669 ; CHECK-D-NEXT: ret
2670 ;
2671 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv4i32:
2672 ; CHECK-ZVBB: # %bb.0:
2673 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m2, ta, ma
2674 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2675 ; CHECK-ZVBB-NEXT: ret
2676 %a = call <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 true)
2677 ret <vscale x 4 x i32> %a
2678 }
2680 define <vscale x 8 x i32> @cttz_zero_undef_nxv8i32(<vscale x 8 x i32> %va) {
2681 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv8i32:
2682 ; CHECK-ZVE64X: # %bb.0:
2683 ; CHECK-ZVE64X-NEXT: li a0, 1
2684 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m4, ta, ma
2685 ; CHECK-ZVE64X-NEXT: vsub.vx v12, v8, a0
2686 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2687 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v12
2688 ; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 1
2689 ; CHECK-ZVE64X-NEXT: lui a0, 349525
2690 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2691 ; CHECK-ZVE64X-NEXT: vand.vx v12, v12, a0
2692 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v12
2693 ; CHECK-ZVE64X-NEXT: lui a0, 209715
2694 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2695 ; CHECK-ZVE64X-NEXT: vand.vx v12, v8, a0
2696 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2697 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2698 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v12, v8
2699 ; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 4
2700 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v12
2701 ; CHECK-ZVE64X-NEXT: lui a0, 61681
2702 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2703 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2704 ; CHECK-ZVE64X-NEXT: lui a0, 4112
2705 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
2706 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2707 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
2708 ; CHECK-ZVE64X-NEXT: ret
2709 ;
2710 ; CHECK-F-LABEL: cttz_zero_undef_nxv8i32:
2711 ; CHECK-F: # %bb.0:
2712 ; CHECK-F-NEXT: vsetvli a0, zero, e32, m4, ta, ma
2713 ; CHECK-F-NEXT: vrsub.vi v12, v8, 0
2714 ; CHECK-F-NEXT: vand.vv v8, v8, v12
2715 ; CHECK-F-NEXT: fsrmi a0, 1
2716 ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
2717 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23
2718 ; CHECK-F-NEXT: li a1, 127
2719 ; CHECK-F-NEXT: vsub.vx v8, v8, a1
2720 ; CHECK-F-NEXT: fsrm a0
2721 ; CHECK-F-NEXT: ret
2722 ;
2723 ; CHECK-D-LABEL: cttz_zero_undef_nxv8i32:
2724 ; CHECK-D: # %bb.0:
2725 ; CHECK-D-NEXT: vsetvli a0, zero, e32, m4, ta, ma
2726 ; CHECK-D-NEXT: vrsub.vi v12, v8, 0
2727 ; CHECK-D-NEXT: vand.vv v8, v8, v12
2728 ; CHECK-D-NEXT: vfwcvt.f.xu.v v16, v8
2729 ; CHECK-D-NEXT: li a0, 52
2730 ; CHECK-D-NEXT: vnsrl.wx v8, v16, a0
2731 ; CHECK-D-NEXT: li a0, 1023
2732 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
2733 ; CHECK-D-NEXT: ret
2734 ;
2735 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv8i32:
2736 ; CHECK-ZVBB: # %bb.0:
2737 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m4, ta, ma
2738 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2739 ; CHECK-ZVBB-NEXT: ret
2740 %a = call <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 true)
2741 ret <vscale x 8 x i32> %a
2742 }
2744 define <vscale x 16 x i32> @cttz_zero_undef_nxv16i32(<vscale x 16 x i32> %va) {
2745 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv16i32:
2746 ; CHECK-ZVE64X: # %bb.0:
2747 ; CHECK-ZVE64X-NEXT: li a0, 1
2748 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m8, ta, ma
2749 ; CHECK-ZVE64X-NEXT: vsub.vx v16, v8, a0
2750 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2751 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v16
2752 ; CHECK-ZVE64X-NEXT: vsrl.vi v16, v8, 1
2753 ; CHECK-ZVE64X-NEXT: lui a0, 349525
2754 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2755 ; CHECK-ZVE64X-NEXT: vand.vx v16, v16, a0
2756 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v16
2757 ; CHECK-ZVE64X-NEXT: lui a0, 209715
2758 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2759 ; CHECK-ZVE64X-NEXT: vand.vx v16, v8, a0
2760 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2761 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2762 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v16, v8
2763 ; CHECK-ZVE64X-NEXT: vsrl.vi v16, v8, 4
2764 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v16
2765 ; CHECK-ZVE64X-NEXT: lui a0, 61681
2766 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2767 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2768 ; CHECK-ZVE64X-NEXT: lui a0, 4112
2769 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
2770 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2771 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
2772 ; CHECK-ZVE64X-NEXT: ret
2773 ;
2774 ; CHECK-F-LABEL: cttz_zero_undef_nxv16i32:
2775 ; CHECK-F: # %bb.0:
2776 ; CHECK-F-NEXT: vsetvli a0, zero, e32, m8, ta, ma
2777 ; CHECK-F-NEXT: vrsub.vi v16, v8, 0
2778 ; CHECK-F-NEXT: vand.vv v8, v8, v16
2779 ; CHECK-F-NEXT: fsrmi a0, 1
2780 ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
2781 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23
2782 ; CHECK-F-NEXT: li a1, 127
2783 ; CHECK-F-NEXT: vsub.vx v8, v8, a1
2784 ; CHECK-F-NEXT: fsrm a0
2785 ; CHECK-F-NEXT: ret
2786 ;
2787 ; CHECK-D-LABEL: cttz_zero_undef_nxv16i32:
2788 ; CHECK-D: # %bb.0:
2789 ; CHECK-D-NEXT: vsetvli a0, zero, e32, m8, ta, ma
2790 ; CHECK-D-NEXT: vrsub.vi v16, v8, 0
2791 ; CHECK-D-NEXT: vand.vv v8, v8, v16
2792 ; CHECK-D-NEXT: fsrmi a0, 1
2793 ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
2794 ; CHECK-D-NEXT: vsrl.vi v8, v8, 23
2795 ; CHECK-D-NEXT: li a1, 127
2796 ; CHECK-D-NEXT: vsub.vx v8, v8, a1
2797 ; CHECK-D-NEXT: fsrm a0
2798 ; CHECK-D-NEXT: ret
2799 ;
2800 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv16i32:
2801 ; CHECK-ZVBB: # %bb.0:
2802 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma
2803 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2804 ; CHECK-ZVBB-NEXT: ret
2805 %a = call <vscale x 16 x i32> @llvm.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 true)
2806 ret <vscale x 16 x i32> %a
2807 }
2809 define <vscale x 1 x i64> @cttz_zero_undef_nxv1i64(<vscale x 1 x i64> %va) {
2810 ; RV32I-LABEL: cttz_zero_undef_nxv1i64:
2811 ; RV32I: # %bb.0:
2812 ; RV32I-NEXT: li a0, 1
2813 ; RV32I-NEXT: vsetvli a1, zero, e64, m1, ta, ma
2814 ; RV32I-NEXT: vsub.vx v9, v8, a0
2815 ; RV32I-NEXT: vnot.v v8, v8
2816 ; RV32I-NEXT: vand.vv v8, v8, v9
2817 ; RV32I-NEXT: vsrl.vi v9, v8, 1
2818 ; RV32I-NEXT: lui a0, 349525
2819 ; RV32I-NEXT: addi a0, a0, 1365
2820 ; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
2821 ; RV32I-NEXT: vmv.v.x v10, a0
2822 ; RV32I-NEXT: vsetvli a0, zero, e64, m1, ta, ma
2823 ; RV32I-NEXT: vand.vv v9, v9, v10
2824 ; RV32I-NEXT: vsub.vv v8, v8, v9
2825 ; RV32I-NEXT: lui a0, 209715
2826 ; RV32I-NEXT: addi a0, a0, 819
2827 ; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
2828 ; RV32I-NEXT: vmv.v.x v9, a0
2829 ; RV32I-NEXT: vsetvli a0, zero, e64, m1, ta, ma
2830 ; RV32I-NEXT: vand.vv v10, v8, v9
2831 ; RV32I-NEXT: vsrl.vi v8, v8, 2
2832 ; RV32I-NEXT: vand.vv v8, v8, v9
2833 ; RV32I-NEXT: vadd.vv v8, v10, v8
2834 ; RV32I-NEXT: vsrl.vi v9, v8, 4
2835 ; RV32I-NEXT: vadd.vv v8, v8, v9
2836 ; RV32I-NEXT: lui a0, 61681
2837 ; RV32I-NEXT: addi a0, a0, -241
2838 ; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
2839 ; RV32I-NEXT: vmv.v.x v9, a0
2840 ; RV32I-NEXT: vsetvli a0, zero, e64, m1, ta, ma
2841 ; RV32I-NEXT: vand.vv v8, v8, v9
2842 ; RV32I-NEXT: lui a0, 4112
2843 ; RV32I-NEXT: addi a0, a0, 257
2844 ; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
2845 ; RV32I-NEXT: vmv.v.x v9, a0
2846 ; RV32I-NEXT: vsetvli a0, zero, e64, m1, ta, ma
2847 ; RV32I-NEXT: vmul.vv v8, v8, v9
2848 ; RV32I-NEXT: li a0, 56
2849 ; RV32I-NEXT: vsrl.vx v8, v8, a0
2850 ; RV32I-NEXT: ret
2851 ;
2852 ; RV64I-LABEL: cttz_zero_undef_nxv1i64:
2853 ; RV64I: # %bb.0:
2854 ; RV64I-NEXT: li a0, 1
2855 ; RV64I-NEXT: vsetvli a1, zero, e64, m1, ta, ma
2856 ; RV64I-NEXT: vsub.vx v9, v8, a0
2857 ; RV64I-NEXT: vnot.v v8, v8
2858 ; RV64I-NEXT: vand.vv v8, v8, v9
2859 ; RV64I-NEXT: vsrl.vi v9, v8, 1
2860 ; RV64I-NEXT: lui a0, 349525
2861 ; RV64I-NEXT: addiw a0, a0, 1365
2862 ; RV64I-NEXT: slli a1, a0, 32
2863 ; RV64I-NEXT: add a0, a0, a1
2864 ; RV64I-NEXT: vand.vx v9, v9, a0
2865 ; RV64I-NEXT: vsub.vv v8, v8, v9
2866 ; RV64I-NEXT: lui a0, 209715
2867 ; RV64I-NEXT: addiw a0, a0, 819
2868 ; RV64I-NEXT: slli a1, a0, 32
2869 ; RV64I-NEXT: add a0, a0, a1
2870 ; RV64I-NEXT: vand.vx v9, v8, a0
2871 ; RV64I-NEXT: vsrl.vi v8, v8, 2
2872 ; RV64I-NEXT: vand.vx v8, v8, a0
2873 ; RV64I-NEXT: vadd.vv v8, v9, v8
2874 ; RV64I-NEXT: vsrl.vi v9, v8, 4
2875 ; RV64I-NEXT: vadd.vv v8, v8, v9
2876 ; RV64I-NEXT: lui a0, 61681
2877 ; RV64I-NEXT: addiw a0, a0, -241
2878 ; RV64I-NEXT: slli a1, a0, 32
2879 ; RV64I-NEXT: add a0, a0, a1
2880 ; RV64I-NEXT: vand.vx v8, v8, a0
2881 ; RV64I-NEXT: lui a0, 4112
2882 ; RV64I-NEXT: addiw a0, a0, 257
2883 ; RV64I-NEXT: slli a1, a0, 32
2884 ; RV64I-NEXT: add a0, a0, a1
2885 ; RV64I-NEXT: vmul.vx v8, v8, a0
2886 ; RV64I-NEXT: li a0, 56
2887 ; RV64I-NEXT: vsrl.vx v8, v8, a0
2888 ; RV64I-NEXT: ret
2889 ;
2890 ; RV32F-LABEL: cttz_zero_undef_nxv1i64:
2891 ; RV32F: # %bb.0:
2892 ; RV32F-NEXT: vsetvli a0, zero, e64, m1, ta, ma
2893 ; RV32F-NEXT: vrsub.vi v9, v8, 0
2894 ; RV32F-NEXT: vand.vv v8, v8, v9
2895 ; RV32F-NEXT: fsrmi a0, 1
2896 ; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
2897 ; RV32F-NEXT: vfncvt.f.xu.w v9, v8
2898 ; RV32F-NEXT: vsrl.vi v8, v9, 23
2899 ; RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
2900 ; RV32F-NEXT: vzext.vf2 v9, v8
2901 ; RV32F-NEXT: li a1, 127
2902 ; RV32F-NEXT: vsub.vx v8, v9, a1
2903 ; RV32F-NEXT: fsrm a0
2904 ; RV32F-NEXT: ret
2905 ;
2906 ; RV64F-LABEL: cttz_zero_undef_nxv1i64:
2907 ; RV64F: # %bb.0:
2908 ; RV64F-NEXT: vsetvli a0, zero, e64, m1, ta, ma
2909 ; RV64F-NEXT: vrsub.vi v9, v8, 0
2910 ; RV64F-NEXT: vand.vv v8, v8, v9
2911 ; RV64F-NEXT: fsrmi a0, 1
2912 ; RV64F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
2913 ; RV64F-NEXT: vfncvt.f.xu.w v9, v8
2914 ; RV64F-NEXT: vsrl.vi v9, v9, 23
2915 ; RV64F-NEXT: li a1, 127
2916 ; RV64F-NEXT: vwsubu.vx v8, v9, a1
2917 ; RV64F-NEXT: fsrm a0
2918 ; RV64F-NEXT: ret
2919 ;
2920 ; CHECK-D-LABEL: cttz_zero_undef_nxv1i64:
2921 ; CHECK-D: # %bb.0:
2922 ; CHECK-D-NEXT: vsetvli a0, zero, e64, m1, ta, ma
2923 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
2924 ; CHECK-D-NEXT: vand.vv v8, v8, v9
2925 ; CHECK-D-NEXT: fsrmi a0, 1
2926 ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
2927 ; CHECK-D-NEXT: li a1, 52
2928 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1
2929 ; CHECK-D-NEXT: li a1, 1023
2930 ; CHECK-D-NEXT: vsub.vx v8, v8, a1
2931 ; CHECK-D-NEXT: fsrm a0
2932 ; CHECK-D-NEXT: ret
2933 ;
2934 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv1i64:
2935 ; CHECK-ZVBB: # %bb.0:
2936 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma
2937 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2938 ; CHECK-ZVBB-NEXT: ret
2939 %a = call <vscale x 1 x i64> @llvm.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 true)
2940 ret <vscale x 1 x i64> %a
2941 }
2943 define <vscale x 2 x i64> @cttz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
2944 ; RV32I-LABEL: cttz_zero_undef_nxv2i64:
2945 ; RV32I: # %bb.0:
2946 ; RV32I-NEXT: li a0, 1
2947 ; RV32I-NEXT: vsetvli a1, zero, e64, m2, ta, ma
2948 ; RV32I-NEXT: vsub.vx v10, v8, a0
2949 ; RV32I-NEXT: vnot.v v8, v8
2950 ; RV32I-NEXT: vand.vv v8, v8, v10
2951 ; RV32I-NEXT: vsrl.vi v10, v8, 1
2952 ; RV32I-NEXT: lui a0, 349525
2953 ; RV32I-NEXT: addi a0, a0, 1365
2954 ; RV32I-NEXT: vsetvli a1, zero, e32, m2, ta, ma
2955 ; RV32I-NEXT: vmv.v.x v12, a0
2956 ; RV32I-NEXT: vsetvli a0, zero, e64, m2, ta, ma
2957 ; RV32I-NEXT: vand.vv v10, v10, v12
2958 ; RV32I-NEXT: vsub.vv v8, v8, v10
2959 ; RV32I-NEXT: lui a0, 209715
2960 ; RV32I-NEXT: addi a0, a0, 819
2961 ; RV32I-NEXT: vsetvli a1, zero, e32, m2, ta, ma
2962 ; RV32I-NEXT: vmv.v.x v10, a0
2963 ; RV32I-NEXT: vsetvli a0, zero, e64, m2, ta, ma
2964 ; RV32I-NEXT: vand.vv v12, v8, v10
2965 ; RV32I-NEXT: vsrl.vi v8, v8, 2
2966 ; RV32I-NEXT: vand.vv v8, v8, v10
2967 ; RV32I-NEXT: vadd.vv v8, v12, v8
2968 ; RV32I-NEXT: vsrl.vi v10, v8, 4
2969 ; RV32I-NEXT: vadd.vv v8, v8, v10
2970 ; RV32I-NEXT: lui a0, 61681
2971 ; RV32I-NEXT: addi a0, a0, -241
2972 ; RV32I-NEXT: vsetvli a1, zero, e32, m2, ta, ma
2973 ; RV32I-NEXT: vmv.v.x v10, a0
2974 ; RV32I-NEXT: vsetvli a0, zero, e64, m2, ta, ma
2975 ; RV32I-NEXT: vand.vv v8, v8, v10
2976 ; RV32I-NEXT: lui a0, 4112
2977 ; RV32I-NEXT: addi a0, a0, 257
2978 ; RV32I-NEXT: vsetvli a1, zero, e32, m2, ta, ma
2979 ; RV32I-NEXT: vmv.v.x v10, a0
2980 ; RV32I-NEXT: vsetvli a0, zero, e64, m2, ta, ma
2981 ; RV32I-NEXT: vmul.vv v8, v8, v10
2982 ; RV32I-NEXT: li a0, 56
2983 ; RV32I-NEXT: vsrl.vx v8, v8, a0
2984 ; RV32I-NEXT: ret
2985 ;
2986 ; RV64I-LABEL: cttz_zero_undef_nxv2i64:
2987 ; RV64I: # %bb.0:
2988 ; RV64I-NEXT: li a0, 1
2989 ; RV64I-NEXT: vsetvli a1, zero, e64, m2, ta, ma
2990 ; RV64I-NEXT: vsub.vx v10, v8, a0
2991 ; RV64I-NEXT: vnot.v v8, v8
2992 ; RV64I-NEXT: vand.vv v8, v8, v10
2993 ; RV64I-NEXT: vsrl.vi v10, v8, 1
2994 ; RV64I-NEXT: lui a0, 349525
2995 ; RV64I-NEXT: addiw a0, a0, 1365
2996 ; RV64I-NEXT: slli a1, a0, 32
2997 ; RV64I-NEXT: add a0, a0, a1
2998 ; RV64I-NEXT: vand.vx v10, v10, a0
2999 ; RV64I-NEXT: vsub.vv v8, v8, v10
3000 ; RV64I-NEXT: lui a0, 209715
3001 ; RV64I-NEXT: addiw a0, a0, 819
3002 ; RV64I-NEXT: slli a1, a0, 32
3003 ; RV64I-NEXT: add a0, a0, a1
3004 ; RV64I-NEXT: vand.vx v10, v8, a0
3005 ; RV64I-NEXT: vsrl.vi v8, v8, 2
3006 ; RV64I-NEXT: vand.vx v8, v8, a0
3007 ; RV64I-NEXT: vadd.vv v8, v10, v8
3008 ; RV64I-NEXT: vsrl.vi v10, v8, 4
3009 ; RV64I-NEXT: vadd.vv v8, v8, v10
3010 ; RV64I-NEXT: lui a0, 61681
3011 ; RV64I-NEXT: addiw a0, a0, -241
3012 ; RV64I-NEXT: slli a1, a0, 32
3013 ; RV64I-NEXT: add a0, a0, a1
3014 ; RV64I-NEXT: vand.vx v8, v8, a0
3015 ; RV64I-NEXT: lui a0, 4112
3016 ; RV64I-NEXT: addiw a0, a0, 257
3017 ; RV64I-NEXT: slli a1, a0, 32
3018 ; RV64I-NEXT: add a0, a0, a1
3019 ; RV64I-NEXT: vmul.vx v8, v8, a0
3020 ; RV64I-NEXT: li a0, 56
3021 ; RV64I-NEXT: vsrl.vx v8, v8, a0
3022 ; RV64I-NEXT: ret
3023 ;
3024 ; RV32F-LABEL: cttz_zero_undef_nxv2i64:
3025 ; RV32F: # %bb.0:
3026 ; RV32F-NEXT: vsetvli a0, zero, e64, m2, ta, ma
3027 ; RV32F-NEXT: vrsub.vi v10, v8, 0
3028 ; RV32F-NEXT: vand.vv v8, v8, v10
3029 ; RV32F-NEXT: fsrmi a0, 1
3030 ; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
3031 ; RV32F-NEXT: vfncvt.f.xu.w v10, v8
3032 ; RV32F-NEXT: vsrl.vi v8, v10, 23
3033 ; RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
3034 ; RV32F-NEXT: vzext.vf2 v10, v8
3035 ; RV32F-NEXT: li a1, 127
3036 ; RV32F-NEXT: vsub.vx v8, v10, a1
3037 ; RV32F-NEXT: fsrm a0
3038 ; RV32F-NEXT: ret
3039 ;
3040 ; RV64F-LABEL: cttz_zero_undef_nxv2i64:
3041 ; RV64F: # %bb.0:
3042 ; RV64F-NEXT: vsetvli a0, zero, e64, m2, ta, ma
3043 ; RV64F-NEXT: vrsub.vi v10, v8, 0
3044 ; RV64F-NEXT: vand.vv v8, v8, v10
3045 ; RV64F-NEXT: fsrmi a0, 1
3046 ; RV64F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
3047 ; RV64F-NEXT: vfncvt.f.xu.w v10, v8
3048 ; RV64F-NEXT: vsrl.vi v10, v10, 23
3049 ; RV64F-NEXT: li a1, 127
3050 ; RV64F-NEXT: vwsubu.vx v8, v10, a1
3051 ; RV64F-NEXT: fsrm a0
3052 ; RV64F-NEXT: ret
3053 ;
3054 ; CHECK-D-LABEL: cttz_zero_undef_nxv2i64:
3055 ; CHECK-D: # %bb.0:
3056 ; CHECK-D-NEXT: vsetvli a0, zero, e64, m2, ta, ma
3057 ; CHECK-D-NEXT: vrsub.vi v10, v8, 0
3058 ; CHECK-D-NEXT: vand.vv v8, v8, v10
3059 ; CHECK-D-NEXT: fsrmi a0, 1
3060 ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
3061 ; CHECK-D-NEXT: li a1, 52
3062 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1
3063 ; CHECK-D-NEXT: li a1, 1023
3064 ; CHECK-D-NEXT: vsub.vx v8, v8, a1
3065 ; CHECK-D-NEXT: fsrm a0
3066 ; CHECK-D-NEXT: ret
3067 ;
3068 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv2i64:
3069 ; CHECK-ZVBB: # %bb.0:
3070 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
3071 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
3072 ; CHECK-ZVBB-NEXT: ret
3073 %a = call <vscale x 2 x i64> @llvm.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 true)
3074 ret <vscale x 2 x i64> %a
3075 }
3077 define <vscale x 4 x i64> @cttz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
3078 ; RV32I-LABEL: cttz_zero_undef_nxv4i64:
3079 ; RV32I: # %bb.0:
3080 ; RV32I-NEXT: li a0, 1
3081 ; RV32I-NEXT: vsetvli a1, zero, e64, m4, ta, ma
3082 ; RV32I-NEXT: vsub.vx v12, v8, a0
3083 ; RV32I-NEXT: vnot.v v8, v8
3084 ; RV32I-NEXT: vand.vv v8, v8, v12
3085 ; RV32I-NEXT: vsrl.vi v12, v8, 1
3086 ; RV32I-NEXT: lui a0, 349525
3087 ; RV32I-NEXT: addi a0, a0, 1365
3088 ; RV32I-NEXT: vsetvli a1, zero, e32, m4, ta, ma
3089 ; RV32I-NEXT: vmv.v.x v16, a0
3090 ; RV32I-NEXT: vsetvli a0, zero, e64, m4, ta, ma
3091 ; RV32I-NEXT: vand.vv v12, v12, v16
3092 ; RV32I-NEXT: vsub.vv v8, v8, v12
3093 ; RV32I-NEXT: lui a0, 209715
3094 ; RV32I-NEXT: addi a0, a0, 819
3095 ; RV32I-NEXT: vsetvli a1, zero, e32, m4, ta, ma
3096 ; RV32I-NEXT: vmv.v.x v12, a0
3097 ; RV32I-NEXT: vsetvli a0, zero, e64, m4, ta, ma
3098 ; RV32I-NEXT: vand.vv v16, v8, v12
3099 ; RV32I-NEXT: vsrl.vi v8, v8, 2
3100 ; RV32I-NEXT: vand.vv v8, v8, v12
3101 ; RV32I-NEXT: vadd.vv v8, v16, v8
3102 ; RV32I-NEXT: vsrl.vi v12, v8, 4
3103 ; RV32I-NEXT: vadd.vv v8, v8, v12
3104 ; RV32I-NEXT: lui a0, 61681
3105 ; RV32I-NEXT: addi a0, a0, -241
3106 ; RV32I-NEXT: vsetvli a1, zero, e32, m4, ta, ma
3107 ; RV32I-NEXT: vmv.v.x v12, a0
3108 ; RV32I-NEXT: vsetvli a0, zero, e64, m4, ta, ma
3109 ; RV32I-NEXT: vand.vv v8, v8, v12
3110 ; RV32I-NEXT: lui a0, 4112
3111 ; RV32I-NEXT: addi a0, a0, 257
3112 ; RV32I-NEXT: vsetvli a1, zero, e32, m4, ta, ma
3113 ; RV32I-NEXT: vmv.v.x v12, a0
3114 ; RV32I-NEXT: vsetvli a0, zero, e64, m4, ta, ma
3115 ; RV32I-NEXT: vmul.vv v8, v8, v12
3116 ; RV32I-NEXT: li a0, 56
3117 ; RV32I-NEXT: vsrl.vx v8, v8, a0
3118 ; RV32I-NEXT: ret
3119 ;
3120 ; RV64I-LABEL: cttz_zero_undef_nxv4i64:
3121 ; RV64I: # %bb.0:
3122 ; RV64I-NEXT: li a0, 1
3123 ; RV64I-NEXT: vsetvli a1, zero, e64, m4, ta, ma
3124 ; RV64I-NEXT: vsub.vx v12, v8, a0
3125 ; RV64I-NEXT: vnot.v v8, v8
3126 ; RV64I-NEXT: vand.vv v8, v8, v12
3127 ; RV64I-NEXT: vsrl.vi v12, v8, 1
3128 ; RV64I-NEXT: lui a0, 349525
3129 ; RV64I-NEXT: addiw a0, a0, 1365
3130 ; RV64I-NEXT: slli a1, a0, 32
3131 ; RV64I-NEXT: add a0, a0, a1
3132 ; RV64I-NEXT: vand.vx v12, v12, a0
3133 ; RV64I-NEXT: vsub.vv v8, v8, v12
3134 ; RV64I-NEXT: lui a0, 209715
3135 ; RV64I-NEXT: addiw a0, a0, 819
3136 ; RV64I-NEXT: slli a1, a0, 32
3137 ; RV64I-NEXT: add a0, a0, a1
3138 ; RV64I-NEXT: vand.vx v12, v8, a0
3139 ; RV64I-NEXT: vsrl.vi v8, v8, 2
3140 ; RV64I-NEXT: vand.vx v8, v8, a0
3141 ; RV64I-NEXT: vadd.vv v8, v12, v8
3142 ; RV64I-NEXT: vsrl.vi v12, v8, 4
3143 ; RV64I-NEXT: vadd.vv v8, v8, v12
3144 ; RV64I-NEXT: lui a0, 61681
3145 ; RV64I-NEXT: addiw a0, a0, -241
3146 ; RV64I-NEXT: slli a1, a0, 32
3147 ; RV64I-NEXT: add a0, a0, a1
3148 ; RV64I-NEXT: vand.vx v8, v8, a0
3149 ; RV64I-NEXT: lui a0, 4112
3150 ; RV64I-NEXT: addiw a0, a0, 257
3151 ; RV64I-NEXT: slli a1, a0, 32
3152 ; RV64I-NEXT: add a0, a0, a1
3153 ; RV64I-NEXT: vmul.vx v8, v8, a0
3154 ; RV64I-NEXT: li a0, 56
3155 ; RV64I-NEXT: vsrl.vx v8, v8, a0
3156 ; RV64I-NEXT: ret
3157 ;
3158 ; RV32F-LABEL: cttz_zero_undef_nxv4i64:
3159 ; RV32F: # %bb.0:
3160 ; RV32F-NEXT: vsetvli a0, zero, e64, m4, ta, ma
3161 ; RV32F-NEXT: vrsub.vi v12, v8, 0
3162 ; RV32F-NEXT: vand.vv v8, v8, v12
3163 ; RV32F-NEXT: fsrmi a0, 1
3164 ; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
3165 ; RV32F-NEXT: vfncvt.f.xu.w v12, v8
3166 ; RV32F-NEXT: vsrl.vi v8, v12, 23
3167 ; RV32F-NEXT: vsetvli zero, zero, e64, m4, ta, ma
3168 ; RV32F-NEXT: vzext.vf2 v12, v8
3169 ; RV32F-NEXT: li a1, 127
3170 ; RV32F-NEXT: vsub.vx v8, v12, a1
3171 ; RV32F-NEXT: fsrm a0
3172 ; RV32F-NEXT: ret
3173 ;
3174 ; RV64F-LABEL: cttz_zero_undef_nxv4i64:
3175 ; RV64F: # %bb.0:
3176 ; RV64F-NEXT: vsetvli a0, zero, e64, m4, ta, ma
3177 ; RV64F-NEXT: vrsub.vi v12, v8, 0
3178 ; RV64F-NEXT: vand.vv v8, v8, v12
3179 ; RV64F-NEXT: fsrmi a0, 1
3180 ; RV64F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
3181 ; RV64F-NEXT: vfncvt.f.xu.w v12, v8
3182 ; RV64F-NEXT: vsrl.vi v12, v12, 23
3183 ; RV64F-NEXT: li a1, 127
3184 ; RV64F-NEXT: vwsubu.vx v8, v12, a1
3185 ; RV64F-NEXT: fsrm a0
3186 ; RV64F-NEXT: ret
3187 ;
3188 ; CHECK-D-LABEL: cttz_zero_undef_nxv4i64:
3189 ; CHECK-D: # %bb.0:
3190 ; CHECK-D-NEXT: vsetvli a0, zero, e64, m4, ta, ma
3191 ; CHECK-D-NEXT: vrsub.vi v12, v8, 0
3192 ; CHECK-D-NEXT: vand.vv v8, v8, v12
3193 ; CHECK-D-NEXT: fsrmi a0, 1
3194 ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
3195 ; CHECK-D-NEXT: li a1, 52
3196 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1
3197 ; CHECK-D-NEXT: li a1, 1023
3198 ; CHECK-D-NEXT: vsub.vx v8, v8, a1
3199 ; CHECK-D-NEXT: fsrm a0
3200 ; CHECK-D-NEXT: ret
3201 ;
3202 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv4i64:
3203 ; CHECK-ZVBB: # %bb.0:
3204 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma
3205 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
3206 ; CHECK-ZVBB-NEXT: ret
3207 %a = call <vscale x 4 x i64> @llvm.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 true)
3208 ret <vscale x 4 x i64> %a
3209 }
3211 define <vscale x 8 x i64> @cttz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
3212 ; RV32I-LABEL: cttz_zero_undef_nxv8i64:
3213 ; RV32I: # %bb.0:
3214 ; RV32I-NEXT: li a0, 1
3215 ; RV32I-NEXT: vsetvli a1, zero, e64, m8, ta, ma
3216 ; RV32I-NEXT: vsub.vx v16, v8, a0
3217 ; RV32I-NEXT: vnot.v v8, v8
3218 ; RV32I-NEXT: vand.vv v8, v8, v16
3219 ; RV32I-NEXT: vsrl.vi v16, v8, 1
3220 ; RV32I-NEXT: lui a0, 349525
3221 ; RV32I-NEXT: addi a0, a0, 1365
3222 ; RV32I-NEXT: vsetvli a1, zero, e32, m8, ta, ma
3223 ; RV32I-NEXT: vmv.v.x v24, a0
3224 ; RV32I-NEXT: vsetvli a0, zero, e64, m8, ta, ma
3225 ; RV32I-NEXT: vand.vv v16, v16, v24
3226 ; RV32I-NEXT: vsub.vv v8, v8, v16
3227 ; RV32I-NEXT: lui a0, 209715
3228 ; RV32I-NEXT: addi a0, a0, 819
3229 ; RV32I-NEXT: vsetvli a1, zero, e32, m8, ta, ma
3230 ; RV32I-NEXT: vmv.v.x v16, a0
3231 ; RV32I-NEXT: vsetvli a0, zero, e64, m8, ta, ma
3232 ; RV32I-NEXT: vand.vv v24, v8, v16
3233 ; RV32I-NEXT: vsrl.vi v8, v8, 2
3234 ; RV32I-NEXT: vand.vv v8, v8, v16
3235 ; RV32I-NEXT: vadd.vv v8, v24, v8
3236 ; RV32I-NEXT: vsrl.vi v16, v8, 4
3237 ; RV32I-NEXT: vadd.vv v8, v8, v16
3238 ; RV32I-NEXT: lui a0, 61681
3239 ; RV32I-NEXT: addi a0, a0, -241
3240 ; RV32I-NEXT: vsetvli a1, zero, e32, m8, ta, ma
3241 ; RV32I-NEXT: vmv.v.x v16, a0
3242 ; RV32I-NEXT: vsetvli a0, zero, e64, m8, ta, ma
3243 ; RV32I-NEXT: vand.vv v8, v8, v16
3244 ; RV32I-NEXT: lui a0, 4112
3245 ; RV32I-NEXT: addi a0, a0, 257
3246 ; RV32I-NEXT: vsetvli a1, zero, e32, m8, ta, ma
3247 ; RV32I-NEXT: vmv.v.x v16, a0
3248 ; RV32I-NEXT: vsetvli a0, zero, e64, m8, ta, ma
3249 ; RV32I-NEXT: vmul.vv v8, v8, v16
3250 ; RV32I-NEXT: li a0, 56
3251 ; RV32I-NEXT: vsrl.vx v8, v8, a0
3252 ; RV32I-NEXT: ret
3253 ;
3254 ; RV64I-LABEL: cttz_zero_undef_nxv8i64:
3255 ; RV64I: # %bb.0:
3256 ; RV64I-NEXT: li a0, 1
3257 ; RV64I-NEXT: vsetvli a1, zero, e64, m8, ta, ma
3258 ; RV64I-NEXT: vsub.vx v16, v8, a0
3259 ; RV64I-NEXT: vnot.v v8, v8
3260 ; RV64I-NEXT: vand.vv v8, v8, v16
3261 ; RV64I-NEXT: vsrl.vi v16, v8, 1
3262 ; RV64I-NEXT: lui a0, 349525
3263 ; RV64I-NEXT: addiw a0, a0, 1365
3264 ; RV64I-NEXT: slli a1, a0, 32
3265 ; RV64I-NEXT: add a0, a0, a1
3266 ; RV64I-NEXT: vand.vx v16, v16, a0
3267 ; RV64I-NEXT: vsub.vv v8, v8, v16
3268 ; RV64I-NEXT: lui a0, 209715
3269 ; RV64I-NEXT: addiw a0, a0, 819
3270 ; RV64I-NEXT: slli a1, a0, 32
3271 ; RV64I-NEXT: add a0, a0, a1
3272 ; RV64I-NEXT: vand.vx v16, v8, a0
3273 ; RV64I-NEXT: vsrl.vi v8, v8, 2
3274 ; RV64I-NEXT: vand.vx v8, v8, a0
3275 ; RV64I-NEXT: vadd.vv v8, v16, v8
3276 ; RV64I-NEXT: vsrl.vi v16, v8, 4
3277 ; RV64I-NEXT: vadd.vv v8, v8, v16
3278 ; RV64I-NEXT: lui a0, 61681
3279 ; RV64I-NEXT: addiw a0, a0, -241
3280 ; RV64I-NEXT: slli a1, a0, 32
3281 ; RV64I-NEXT: add a0, a0, a1
3282 ; RV64I-NEXT: vand.vx v8, v8, a0
3283 ; RV64I-NEXT: lui a0, 4112
3284 ; RV64I-NEXT: addiw a0, a0, 257
3285 ; RV64I-NEXT: slli a1, a0, 32
3286 ; RV64I-NEXT: add a0, a0, a1
3287 ; RV64I-NEXT: vmul.vx v8, v8, a0
3288 ; RV64I-NEXT: li a0, 56
3289 ; RV64I-NEXT: vsrl.vx v8, v8, a0
3290 ; RV64I-NEXT: ret
3291 ;
3292 ; RV32F-LABEL: cttz_zero_undef_nxv8i64:
3293 ; RV32F: # %bb.0:
3294 ; RV32F-NEXT: vsetvli a0, zero, e64, m8, ta, ma
3295 ; RV32F-NEXT: vrsub.vi v16, v8, 0
3296 ; RV32F-NEXT: vand.vv v8, v8, v16
3297 ; RV32F-NEXT: fsrmi a0, 1
3298 ; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
3299 ; RV32F-NEXT: vfncvt.f.xu.w v16, v8
3300 ; RV32F-NEXT: vsrl.vi v8, v16, 23
3301 ; RV32F-NEXT: vsetvli zero, zero, e64, m8, ta, ma
3302 ; RV32F-NEXT: vzext.vf2 v16, v8
3303 ; RV32F-NEXT: li a1, 127
3304 ; RV32F-NEXT: vsub.vx v8, v16, a1
3305 ; RV32F-NEXT: fsrm a0
3306 ; RV32F-NEXT: ret
3307 ;
3308 ; RV64F-LABEL: cttz_zero_undef_nxv8i64:
3309 ; RV64F: # %bb.0:
3310 ; RV64F-NEXT: vsetvli a0, zero, e64, m8, ta, ma
3311 ; RV64F-NEXT: vrsub.vi v16, v8, 0
3312 ; RV64F-NEXT: vand.vv v8, v8, v16
3313 ; RV64F-NEXT: fsrmi a0, 1
3314 ; RV64F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
3315 ; RV64F-NEXT: vfncvt.f.xu.w v16, v8
3316 ; RV64F-NEXT: vsrl.vi v16, v16, 23
3317 ; RV64F-NEXT: li a1, 127
3318 ; RV64F-NEXT: vwsubu.vx v8, v16, a1
3319 ; RV64F-NEXT: fsrm a0
3320 ; RV64F-NEXT: ret
3321 ;
3322 ; CHECK-D-LABEL: cttz_zero_undef_nxv8i64:
3323 ; CHECK-D: # %bb.0:
3324 ; CHECK-D-NEXT: vsetvli a0, zero, e64, m8, ta, ma
3325 ; CHECK-D-NEXT: vrsub.vi v16, v8, 0
3326 ; CHECK-D-NEXT: vand.vv v8, v8, v16
3327 ; CHECK-D-NEXT: fsrmi a0, 1
3328 ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
3329 ; CHECK-D-NEXT: li a1, 52
3330 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1
3331 ; CHECK-D-NEXT: li a1, 1023
3332 ; CHECK-D-NEXT: vsub.vx v8, v8, a1
3333 ; CHECK-D-NEXT: fsrm a0
3334 ; CHECK-D-NEXT: ret
3335 ;
3336 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv8i64:
3337 ; CHECK-ZVBB: # %bb.0:
3338 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
3339 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
3340 ; CHECK-ZVBB-NEXT: ret
3341 %a = call <vscale x 8 x i64> @llvm.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 true)
3342 ret <vscale x 8 x i64> %a
3343 }
3344 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
3345 ; RV32: {{.*}}
3346 ; RV64: {{.*}}