1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple=riscv32 -mattr=+v -riscv-enable-subreg-liveness -run-pass init-undef -run-pass machineverifier %s -o - | FileCheck %s
5 source_filename = "<stdin>"
6 target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
7 target triple = "riscv64"
9 define <vscale x 2 x float> @undef_early_clobber_chain(ptr %p) #0 {
11 %0 = tail call <vscale x 2 x float> @llvm.riscv.vrgather.vx.nxv2f32.i64(<vscale x 2 x float> undef, <vscale x 2 x float> undef, i64 0, i64 0)
12 ret <vscale x 2 x float> %0
15 declare <vscale x 2 x float> @llvm.riscv.vrgather.vx.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64) #1
17 attributes #0 = { "target-features"="+v" }
18 attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) "target-features"="+v" }
22 name: undef_early_clobber_chain
24 exposesReturnsTwice: false
26 regBankSelected: false
29 tracksRegLiveness: true
32 callsUnwindInit: false
38 failsVerification: false
39 tracksDebugUserValues: false
41 - { id: 0, class: gpr, preferred-register: '' }
42 - { id: 1, class: vr, preferred-register: '' }
43 - { id: 2, class: vr, preferred-register: '' }
44 - { id: 3, class: vr, preferred-register: '' }
47 isFrameAddressTaken: false
48 isReturnAddressTaken: false
58 maxCallFrameSize: 4294967295
59 cvBytesOfCalleeSavedRegisters: 0
60 hasOpaqueSPAdjustment: false
62 hasMustTailInVarArgFunc: false
71 debugValueSubstitutions: []
78 ; CHECK-LABEL: name: undef_early_clobber_chain
79 ; CHECK: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
80 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
81 ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
82 ; CHECK-NEXT: early-clobber %1:vr = PseudoVRGATHER_VI_M1 undef [[DEF]], [[PseudoRVVInitUndefM1_]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
83 ; CHECK-NEXT: $v8 = COPY %1
84 ; CHECK-NEXT: PseudoRET implicit $v8
86 dead $x0 = PseudoVSETIVLI 0, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
87 early-clobber %1:vr = PseudoVRGATHER_VI_M1 undef %2, undef %2, 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
89 PseudoRET implicit $v8