llvm/lib/Target/AArch64/AArch64.td

   1 //=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 //
  10 //===----------------------------------------------------------------------===//
  11
  12 //===----------------------------------------------------------------------===//
  13 // Target-independent interfaces which we are implementing.
  14 //===----------------------------------------------------------------------===//
  15
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // Subtarget features.
  20 //===----------------------------------------------------------------------===//
  21 include "AArch64Features.td"
  22
  23 //===----------------------------------------------------------------------===//
  24 // Register File Description
  25 //===----------------------------------------------------------------------===//
  26
  27 include "AArch64RegisterInfo.td"
  28 include "AArch64RegisterBanks.td"
  29 include "AArch64CallingConvention.td"
  30
  31 //===----------------------------------------------------------------------===//
  32 // Instruction Descriptions
  33 //===----------------------------------------------------------------------===//
  34
  35 include "AArch64Schedule.td"
  36 include "AArch64InstrInfo.td"
  37 include "AArch64SchedPredicates.td"
  38 include "AArch64SchedPredExynos.td"
  39 include "AArch64SchedPredNeoverse.td"
  40 include "AArch64Combine.td"
  41
  42 def AArch64InstrInfo : InstrInfo;
  43
  44 //===----------------------------------------------------------------------===//
  45 // Named operands for MRS/MSR/TLBI/...
  46 //===----------------------------------------------------------------------===//
  47
  48 include "AArch64SystemOperands.td"
  49
  50 //===----------------------------------------------------------------------===//
  51 // AArch64 Processors supported.
  52 //
  53
  54 //===----------------------------------------------------------------------===//
  55 // Unsupported features to disable for scheduling models
  56 //===----------------------------------------------------------------------===//
  57
  58 class AArch64Unsupported { list<Predicate> F; }
  59
  60 let F = [HasSVE2p1, HasSVE2p1_or_HasSME2, HasSVE2p1_or_HasSME2p1] in
  61 def SVE2p1Unsupported : AArch64Unsupported;
  62
  63 def SVE2Unsupported : AArch64Unsupported {
  64   let F = !listconcat([HasSVE2, HasSVE2orSME, HasSVE2orSME2, HasSSVE_FP8FMA, HasSMEF8F16,
  65                        HasSMEF8F32, HasSVE2AES, HasSVE2SHA3, HasSVE2SM4, HasSVE2BitPerm],
  66                        SVE2p1Unsupported.F);
  67 }
  68
  69 def SVEUnsupported : AArch64Unsupported {
  70   let F = !listconcat([HasSVE, HasSVEorSME],
  71                       SVE2Unsupported.F);
  72 }
  73
  74 let F = [HasSME2p1, HasSVE2p1_or_HasSME2p1] in
  75 def SME2p1Unsupported : AArch64Unsupported;
  76
  77 def SME2Unsupported : AArch64Unsupported {
  78   let F = !listconcat([HasSME2, HasSVE2orSME2, HasSVE2p1_or_HasSME2, HasSSVE_FP8FMA,
  79                       HasSMEF8F16, HasSMEF8F32, HasSMEF16F16orSMEF8F16],
  80                       SME2p1Unsupported.F);
  81 }
  82
  83 def SMEUnsupported : AArch64Unsupported {
  84   let F = !listconcat([HasSME, HasSMEI16I64, HasSMEF16F16, HasSMEF64F64, HasSMEFA64],
  85                       SME2Unsupported.F);
  86 }
  87
  88 let F = [HasPAuth, HasPAuthLR] in
  89 def PAUnsupported : AArch64Unsupported;
  90
  91 include "AArch64SchedA53.td"
  92 include "AArch64SchedA55.td"
  93 include "AArch64SchedA510.td"
  94 include "AArch64SchedA57.td"
  95 include "AArch64SchedCyclone.td"
  96 include "AArch64SchedFalkor.td"
  97 include "AArch64SchedKryo.td"
  98 include "AArch64SchedExynosM3.td"
  99 include "AArch64SchedExynosM4.td"
 100 include "AArch64SchedExynosM5.td"
 101 include "AArch64SchedThunderX.td"
 102 include "AArch64SchedThunderX2T99.td"
 103 include "AArch64SchedA64FX.td"
 104 include "AArch64SchedThunderX3T110.td"
 105 include "AArch64SchedTSV110.td"
 106 include "AArch64SchedAmpere1.td"
 107 include "AArch64SchedAmpere1B.td"
 108 include "AArch64SchedNeoverseN1.td"
 109 include "AArch64SchedNeoverseN2.td"
 110 include "AArch64SchedNeoverseV1.td"
 111 include "AArch64SchedNeoverseV2.td"
 112
 113 include "AArch64Processors.td"
 114
 115 //===----------------------------------------------------------------------===//
 116 // Assembly parser
 117 //===----------------------------------------------------------------------===//
 118
 119 def GenericAsmParserVariant : AsmParserVariant {
 120   int Variant = 0;
 121   string Name = "generic";
 122   string BreakCharacters = ".";
 123   string TokenizingCharacters = "[]*!/";
 124 }
 125
 126 def AppleAsmParserVariant : AsmParserVariant {
 127   int Variant = 1;
 128   string Name = "apple-neon";
 129   string BreakCharacters = ".";
 130   string TokenizingCharacters = "[]*!/";
 131 }
 132
 133 //===----------------------------------------------------------------------===//
 134 // Assembly printer
 135 //===----------------------------------------------------------------------===//
 136 // AArch64 Uses the MC printer for asm output, so make sure the TableGen
 137 // AsmWriter bits get associated with the correct class.
 138 def GenericAsmWriter : AsmWriter {
 139   string AsmWriterClassName  = "InstPrinter";
 140   int PassSubtarget = 1;
 141   int Variant = 0;
 142   bit isMCAsmWriter = 1;
 143 }
 144
 145 def AppleAsmWriter : AsmWriter {
 146   let AsmWriterClassName = "AppleInstPrinter";
 147   int PassSubtarget = 1;
 148   int Variant = 1;
 149   int isMCAsmWriter = 1;
 150 }
 151
 152 //===----------------------------------------------------------------------===//
 153 // Target Declaration
 154 //===----------------------------------------------------------------------===//
 155
 156 def AArch64 : Target {
 157   let InstructionSet = AArch64InstrInfo;
 158   let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
 159   let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
 160   let AllowRegisterRenaming = 1;
 161 }
 162
 163 //===----------------------------------------------------------------------===//
 164 // Pfm Counters
 165 //===----------------------------------------------------------------------===//
 166
 167 include "AArch64PfmCounters.td"