llvm/lib/Target/AArch64/AArch64SchedExynosM5.td

   1 //=- AArch64SchedExynosM5.td - Samsung Exynos M5 Sched Defs --*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the machine model for the Samsung Exynos M5 to support
  10 // instruction scheduling and other instruction cost heuristics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // The Exynos-M5 is an advanced superscalar microprocessor with a 6-wide
  16 // in-order stage for decode and dispatch and a wider issue stage.
  17 // The execution units and loads and stores are out-of-order.
  18
  19 def ExynosM5Model : SchedMachineModel {
  20   let IssueWidth            =   6; // Up to 6 uops per cycle.
  21   let MicroOpBufferSize     = 228; // ROB size.
  22   let LoopMicroOpBufferSize =  60; // Based on the instruction queue size.
  23   let LoadLatency           =   4; // Optimistic load cases.
  24   let MispredictPenalty     =  15; // Minimum branch misprediction penalty.
  25   let CompleteModel         =   1; // Use the default model otherwise.
  26
  27   list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
  28                                                     PAUnsupported.F,
  29                                                     SMEUnsupported.F,
  30                                                     [HasMTE, HasCSSC]);
  31 }
  32
  33 //===----------------------------------------------------------------------===//
  34 // Define each kind of processor resource and number available on the Exynos-M5.
  35
  36 let SchedModel = ExynosM5Model in {
  37
  38 def M5UnitA  : ProcResource<2>; // Simple integer
  39 def M5UnitC  : ProcResource<2>; // Simple and complex integer
  40 let Super =  M5UnitC, BufferSize = 1 in
  41 def M5UnitD  : ProcResource<1>; // Integer division (inside C0, serialized)
  42 def M5UnitE  : ProcResource<2>; // Simple 32-bit integer
  43 let Super =  M5UnitC in
  44 def M5UnitF  : ProcResource<2>; // CRC (inside C)
  45 def M5UnitB  : ProcResource<1>; // Branch
  46 def M5UnitL0 : ProcResource<1>; // Load
  47 def M5UnitS0 : ProcResource<1>; // Store
  48 def M5PipeLS : ProcResource<1>; // Load/Store
  49 let Super = M5PipeLS in {
  50   def M5UnitL1 : ProcResource<1>;
  51   def M5UnitS1 : ProcResource<1>;
  52 }
  53 def M5PipeF0 : ProcResource<1>; // FP #0
  54 let Super = M5PipeF0 in {
  55   def M5UnitFMAC0 : ProcResource<1>; // FP multiplication
  56   def M5UnitFADD0 : ProcResource<1>; // Simple FP
  57   def M5UnitNALU0 : ProcResource<1>; // Simple vector
  58   def M5UnitNDOT0 : ProcResource<1>; // Dot product vector
  59   def M5UnitNHAD  : ProcResource<1>; // Horizontal vector
  60   def M5UnitNMSC  : ProcResource<1>; // FP and vector miscellanea
  61   def M5UnitNMUL0 : ProcResource<1>; // Vector multiplication
  62   def M5UnitNSHT0 : ProcResource<1>; // Vector shifting
  63   def M5UnitNSHF0 : ProcResource<1>; // Vector shuffling
  64   def M5UnitNCRY0 : ProcResource<1>; // Cryptographic
  65 }
  66 def M5PipeF1 : ProcResource<1>; // FP #1
  67 let Super = M5PipeF1 in {
  68   def M5UnitFMAC1 : ProcResource<1>; // FP multiplication
  69   def M5UnitFADD1 : ProcResource<1>; // Simple FP
  70   def M5UnitFCVT0 : ProcResource<1>; // FP conversion
  71   def M5UnitFDIV0 : ProcResource<2>; // FP division (serialized)
  72   def M5UnitFSQR0 : ProcResource<2>; // FP square root (serialized)
  73   def M5UnitFST0  : ProcResource<1>; // FP store
  74   def M5UnitNALU1 : ProcResource<1>; // Simple vector
  75   def M5UnitNDOT1 : ProcResource<1>; // Dot product vector
  76   def M5UnitNSHT1 : ProcResource<1>; // Vector shifting
  77   def M5UnitNSHF1 : ProcResource<1>; // Vector shuffling
  78 }
  79 def M5PipeF2 : ProcResource<1>; // FP #2
  80 let Super = M5PipeF2 in {
  81   def M5UnitFMAC2 : ProcResource<1>; // FP multiplication
  82   def M5UnitFADD2 : ProcResource<1>; // Simple FP
  83   def M5UnitFCVT1 : ProcResource<1>; // FP conversion
  84   def M5UnitFDIV1 : ProcResource<2>; // FP division (serialized)
  85   def M5UnitFSQR1 : ProcResource<2>; // FP square root (serialized)
  86   def M5UnitFST1  : ProcResource<1>; // FP store
  87   def M5UnitNALU2 : ProcResource<1>; // Simple vector
  88   def M5UnitNDOT2 : ProcResource<1>; // Dot product vector
  89   def M5UnitNMUL1 : ProcResource<1>; // Vector multiplication
  90   def M5UnitNSHT2 : ProcResource<1>; // Vector shifting
  91   def M5UnitNCRY1 : ProcResource<1>; // Cryptographic
  92 }
  93
  94 def M5UnitAX    : ProcResGroup<[M5UnitA,
  95                                 M5UnitC]>;
  96 def M5UnitAW    : ProcResGroup<[M5UnitA,
  97                                 M5UnitC,
  98                                 M5UnitE]>;
  99 def M5UnitL     : ProcResGroup<[M5UnitL0,
 100                                 M5UnitL1]>;
 101 def M5UnitS     : ProcResGroup<[M5UnitS0,
 102                                 M5UnitS1]>;
 103 def M5UnitFMAC  : ProcResGroup<[M5UnitFMAC0,
 104                                 M5UnitFMAC1,
 105                                 M5UnitFMAC2]>;
 106 def M5UnitFADD  : ProcResGroup<[M5UnitFADD0,
 107                                 M5UnitFADD1,
 108                                 M5UnitFADD2]>;
 109 def M5UnitFCVT  : ProcResGroup<[M5UnitFCVT0,
 110                                 M5UnitFCVT1]>;
 111 def M5UnitFDIV  : ProcResGroup<[M5UnitFDIV0,
 112                                 M5UnitFDIV1]>;
 113 def M5UnitFSQR  : ProcResGroup<[M5UnitFSQR0,
 114                                 M5UnitFSQR1]>;
 115 def M5UnitFST   : ProcResGroup<[M5UnitFST0,
 116                                 M5UnitFST1]>;
 117 def M5UnitNALU  : ProcResGroup<[M5UnitNALU0,
 118                                 M5UnitNALU1,
 119                                 M5UnitNALU2]>;
 120 def M5UnitNDOT  : ProcResGroup<[M5UnitNDOT0,
 121                                 M5UnitNDOT1,
 122                                 M5UnitNDOT2]>;
 123 def M5UnitNMUL  : ProcResGroup<[M5UnitNMUL0,
 124                                 M5UnitNMUL1]>;
 125 def M5UnitNSHT  : ProcResGroup<[M5UnitNSHT0,
 126                                 M5UnitNSHT1,
 127                                 M5UnitNSHT2]>;
 128 def M5UnitNSHF  : ProcResGroup<[M5UnitNSHF0,
 129                                 M5UnitNSHF1]>;
 130 def M5UnitNCRY  : ProcResGroup<[M5UnitNCRY0,
 131                                 M5UnitNCRY1]>;
 132
 133 //===----------------------------------------------------------------------===//
 134 // Resources details.
 135
 136 def M5WriteZ0 : SchedWriteRes<[]> { let Latency = 0; }
 137 def M5WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
 138                                     let NumMicroOps = 0; }
 139 def M5WriteZ4 : SchedWriteRes<[]> { let Latency = 4;
 140                                     let NumMicroOps = 0; }
 141
 142 def M5WriteA1W : SchedWriteRes<[M5UnitAW]> { let Latency = 1; }
 143 def M5WriteA1X : SchedWriteRes<[M5UnitAX]> { let Latency = 1; }
 144 def M5WriteAAW : SchedWriteRes<[M5UnitAW]> { let Latency = 2;
 145                                              let ReleaseAtCycles = [2]; }
 146 def M5WriteAAX : SchedWriteRes<[M5UnitAX]> { let Latency = 2;
 147                                              let ReleaseAtCycles = [2]; }
 148 def M5WriteAB  : SchedWriteRes<[M5UnitAX,
 149                                 M5UnitC,
 150                                 M5UnitE]>  { let Latency = 2;
 151                                              let NumMicroOps = 2; }
 152 def M5WriteAC  : SchedWriteRes<[M5UnitAX,
 153                                 M5UnitAX,
 154                                 M5UnitC]>  { let Latency = 3;
 155                                              let NumMicroOps = 3; }
 156 def M5WriteAD  : SchedWriteRes<[M5UnitAW,
 157                                 M5UnitC]>  { let Latency = 2;
 158                                               let NumMicroOps = 2; }
 159 def M5WriteAFW : SchedWriteRes<[M5UnitAW]> { let Latency = 2;
 160                                              let NumMicroOps = 2; }
 161 def M5WriteAFX : SchedWriteRes<[M5UnitAX]> { let Latency = 2;
 162                                              let NumMicroOps = 2; }
 163 def M5WriteAUW : SchedWriteVariant<[SchedVar<IsCopyIdiomPred,   [M5WriteZ0]>,
 164                                     SchedVar<ExynosArithPred,   [M5WriteA1W]>,
 165                                     SchedVar<ExynosLogicExPred, [M5WriteA1W]>,
 166                                     SchedVar<NoSchedPred,       [M5WriteAAW]>]>;
 167 def M5WriteAUX : SchedWriteVariant<[SchedVar<IsCopyIdiomPred,   [M5WriteZ0]>,
 168                                     SchedVar<ExynosArithPred,   [M5WriteA1X]>,
 169                                     SchedVar<ExynosLogicExPred, [M5WriteA1X]>,
 170                                     SchedVar<NoSchedPred,       [M5WriteAAX]>]>;
 171 def M5WriteAVW : SchedWriteVariant<[SchedVar<ExynosResetPred,   [M5WriteZ0]>,
 172                                     SchedVar<ExynosArithPred,   [M5WriteA1W]>,
 173                                     SchedVar<ExynosLogicExPred, [M5WriteA1W]>,
 174                                     SchedVar<NoSchedPred,       [M5WriteAAW]>]>;
 175 def M5WriteAVX : SchedWriteVariant<[SchedVar<ExynosResetPred,   [M5WriteZ0]>,
 176                                     SchedVar<ExynosArithPred,   [M5WriteA1X]>,
 177                                     SchedVar<ExynosLogicExPred, [M5WriteA1X]>,
 178                                     SchedVar<NoSchedPred,       [M5WriteAAX]>]>;
 179 def M5WriteAXW : SchedWriteVariant<[SchedVar<ExynosArithPred,   [M5WriteA1W]>,
 180                                     SchedVar<ExynosLogicExPred, [M5WriteA1W]>,
 181                                     SchedVar<NoSchedPred,       [M5WriteAAW]>]>;
 182 def M5WriteAXX : SchedWriteVariant<[SchedVar<ExynosArithPred,   [M5WriteA1X]>,
 183                                     SchedVar<ExynosLogicExPred, [M5WriteA1X]>,
 184                                     SchedVar<NoSchedPred,       [M5WriteAAX]>]>;
 185 def M5WriteAYW : SchedWriteVariant<[SchedVar<IsRORImmIdiomPred, [M5WriteA1W]>,
 186                                     SchedVar<NoSchedPred,       [M5WriteAFW]>]>;
 187 def M5WriteAYX : SchedWriteVariant<[SchedVar<IsRORImmIdiomPred, [M5WriteA1X]>,
 188                                     SchedVar<NoSchedPred,       [M5WriteAFX]>]>;
 189
 190 def M5WriteB1 : SchedWriteRes<[M5UnitB]> { let Latency = 1; }
 191 def M5WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M5WriteAC]>,
 192                                    SchedVar<NoSchedPred,            [M5WriteAB]>]>;
 193
 194 def M5WriteC1 : SchedWriteRes<[M5UnitC]> { let Latency = 1; }
 195 def M5WriteC2 : SchedWriteRes<[M5UnitC]> { let Latency = 2; }
 196 def M5WriteCA : SchedWriteRes<[M5UnitC]> { let Latency = 3;
 197                                            let ReleaseAtCycles = [2]; }
 198
 199 def M5WriteD10 : SchedWriteRes<[M5UnitD]> { let Latency = 10;
 200                                             let ReleaseAtCycles = [10]; }
 201 def M5WriteD16 : SchedWriteRes<[M5UnitD]> { let Latency = 16;
 202                                             let ReleaseAtCycles = [16]; }
 203
 204 def M5WriteF2 : SchedWriteRes<[M5UnitF]> { let Latency = 2; }
 205
 206 def M5WriteL4 : SchedWriteRes<[M5UnitL]> { let Latency = 4; }
 207 def M5WriteL5 : SchedWriteRes<[M5UnitL]> { let Latency = 5; }
 208 def M5WriteL6 : SchedWriteRes<[M5UnitL]> { let Latency = 6; }
 209 def M5WriteLA : SchedWriteRes<[M5UnitL,
 210                                M5UnitL]> { let Latency = 6;
 211                                            let NumMicroOps = 1; }
 212 def M5WriteLB : SchedWriteRes<[M5UnitAX,
 213                                M5UnitL]> { let Latency = 6;
 214                                            let NumMicroOps = 2; }
 215 def M5WriteLC : SchedWriteRes<[M5UnitAX,
 216                                M5UnitL,
 217                                M5UnitL]> { let Latency = 6;
 218                                            let NumMicroOps = 2; }
 219 def M5WriteLD : SchedWriteRes<[M5UnitAX,
 220                                M5UnitL]> { let Latency = 4;
 221                                            let NumMicroOps = 2; }
 222 def M5WriteLE : SchedWriteRes<[M5UnitAX,
 223                                M5UnitL]> { let Latency = 7;
 224                                            let NumMicroOps = 2; }
 225 def M5WriteLFW : SchedWriteRes<[M5UnitAW,
 226                                 M5UnitAW,
 227                                 M5UnitAW,
 228                                 M5UnitAW,
 229                                 M5UnitL]>  { let Latency = 15;
 230                                              let NumMicroOps = 6;
 231                                              let ReleaseAtCycles = [1, 1, 1, 1, 15]; }
 232 def M5WriteLFX : SchedWriteRes<[M5UnitAX,
 233                                 M5UnitAX,
 234                                 M5UnitAX,
 235                                 M5UnitAX,
 236                                 M5UnitL]>  { let Latency = 15;
 237                                              let NumMicroOps = 6;
 238                                              let ReleaseAtCycles = [1, 1, 1, 1, 15]; }
 239 def M5WriteLGW : SchedWriteRes<[M5UnitAW,
 240                                 M5UnitL]>  { let Latency = 13;
 241                                              let NumMicroOps = 1;
 242                                              let ReleaseAtCycles = [1, 13]; }
 243 def M5WriteLGX : SchedWriteRes<[M5UnitAX,
 244                                 M5UnitL]>  { let Latency = 13;
 245                                              let NumMicroOps = 1;
 246                                              let ReleaseAtCycles = [1, 13]; }
 247 def M5WriteLH : SchedWriteRes<[]>        { let Latency = 6;
 248                                            let NumMicroOps = 0; }
 249 def M5WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteL5]>,
 250                                    SchedVar<NoSchedPred,         [M5WriteL4]>]>;
 251 def M5WriteLY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteLE]>,
 252                                    SchedVar<NoSchedPred,         [M5WriteL6]>]>;
 253
 254 def M5WriteS1  : SchedWriteRes<[M5UnitS]>  { let Latency = 1; }
 255 def M5WriteSA  : SchedWriteRes<[M5UnitS0]> { let Latency = 4; }
 256 def M5WriteSB  : SchedWriteRes<[M5UnitAX,
 257                                 M5UnitS]>  { let Latency = 2;
 258                                              let NumMicroOps = 1; }
 259 def M5WriteSX  : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteSB]>,
 260                                     SchedVar<NoSchedPred,         [M5WriteS1]>]>;
 261
 262 def M5ReadAdrBase : SchedReadVariant<[SchedVar<
 263                                         MCSchedPredicate<
 264                                           CheckAny<
 265                                             [ScaledIdxFn,
 266                                              ExynosScaledIdxFn]>>, [ReadDefault]>,
 267                                       SchedVar<NoSchedPred,        [ReadDefault]>]>;
 268
 269 def M5WriteNEONB   : SchedWriteRes<[M5UnitNALU,
 270                                     M5UnitS0]>    { let Latency = 5;
 271                                                     let NumMicroOps = 2; }
 272 def M5WriteNEONH   : SchedWriteRes<[M5UnitNALU,
 273                                     M5UnitS0]>    { let Latency = 2;
 274                                                     let NumMicroOps = 2; }
 275 def M5WriteNEONI   : SchedWriteRes<[M5UnitS0,
 276                                     M5UnitNSHF]>  { let Latency = 6;
 277                                                     let NumMicroOps = 2; }
 278 def M5WriteNEONK   : SchedWriteRes<[M5UnitNSHF,
 279                                     M5UnitFCVT0,
 280                                     M5UnitS0]>    { let Latency = 5;
 281                                                     let NumMicroOps = 2; }
 282 def M5WriteNEONN   : SchedWriteRes<[M5UnitNMSC,
 283                                     M5UnitNMSC]>  { let Latency = 5;
 284                                                     let NumMicroOps = 2;
 285                                                     let ReleaseAtCycles = [7, 7]; }
 286 def M5WriteNEONO   : SchedWriteRes<[M5UnitNMSC,
 287                                     M5UnitNMSC,
 288                                     M5UnitNMSC]>  { let Latency = 8;
 289                                                     let NumMicroOps = 3;
 290                                                     let ReleaseAtCycles = [10, 10, 10]; }
 291 def M5WriteNEONP   : SchedWriteRes<[M5UnitNSHF,
 292                                     M5UnitS0,
 293                                     M5UnitFCVT]>  { let Latency = 7;
 294                                                     let NumMicroOps = 2; }
 295 def M5WriteNEONQ   : SchedWriteRes<[M5UnitNMSC,
 296                                     M5UnitC]>     { let Latency = 3;
 297                                                     let NumMicroOps = 1; }
 298 def M5WriteNEONU   : SchedWriteRes<[M5UnitFSQR,
 299                                     M5UnitFSQR]>  { let Latency = 7;
 300                                                     let ReleaseAtCycles = [4, 4]; }
 301 def M5WriteNEONV   : SchedWriteRes<[M5UnitFDIV,
 302                                     M5UnitFDIV]>  { let Latency = 7;
 303                                                     let ReleaseAtCycles = [6, 6]; }
 304 def M5WriteNEONW   : SchedWriteRes<[M5UnitFDIV,
 305                                     M5UnitFDIV]>  { let Latency = 12;
 306                                                     let ReleaseAtCycles = [9, 9]; }
 307 def M5WriteNEONX   : SchedWriteRes<[M5UnitFSQR,
 308                                     M5UnitFSQR]>  { let Latency = 8;
 309                                                     let ReleaseAtCycles = [5, 5]; }
 310 def M5WriteNEONY   : SchedWriteRes<[M5UnitFSQR,
 311                                     M5UnitFSQR]>  { let Latency = 12;
 312                                                     let ReleaseAtCycles = [9, 9]; }
 313 def M5WriteNEONZ   : SchedWriteVariant<[SchedVar<ExynosQFormPred, [M5WriteNEONO]>,
 314                                         SchedVar<NoSchedPred,     [M5WriteNEONN]>]>;
 315
 316 def M5WriteFADD2   : SchedWriteRes<[M5UnitFADD]>  { let Latency = 2; }
 317
 318 def M5WriteFCVT2   : SchedWriteRes<[M5UnitFCVT]>  { let Latency = 2; }
 319 def M5WriteFCVT2A  : SchedWriteRes<[M5UnitFCVT0]> { let Latency = 2; }
 320 def M5WriteFCVT3   : SchedWriteRes<[M5UnitFCVT]>  { let Latency = 3; }
 321 def M5WriteFCVT3A  : SchedWriteRes<[M5UnitFCVT0]> { let Latency = 3; }
 322 def M5WriteFCVTA   : SchedWriteRes<[M5UnitFCVT0,
 323                                     M5UnitS0]>    { let Latency = 3;
 324                                                     let NumMicroOps = 1; }
 325 def M5WriteFCVTB   : SchedWriteRes<[M5UnitFCVT,
 326                                     M5UnitS0]>    { let Latency = 4;
 327                                                     let NumMicroOps = 1; }
 328 def M5WriteFCVTC   : SchedWriteRes<[M5UnitFCVT,
 329                                     M5UnitS0]>    { let Latency = 6;
 330                                                     let NumMicroOps = 1; }
 331
 332 def M5WriteFDIV5   : SchedWriteRes<[M5UnitFDIV]>  { let Latency = 5;
 333                                                     let ReleaseAtCycles = [2]; }
 334 def M5WriteFDIV7   : SchedWriteRes<[M5UnitFDIV]>  { let Latency = 7;
 335                                                     let ReleaseAtCycles = [4]; }
 336 def M5WriteFDIV12  : SchedWriteRes<[M5UnitFDIV]>  { let Latency = 12;
 337                                                     let ReleaseAtCycles = [9]; }
 338
 339 def M5WriteFMAC3   : SchedWriteRes<[M5UnitFMAC]>  { let Latency = 3; }
 340 def M5WriteFMAC4   : SchedWriteRes<[M5UnitFMAC]>  { let Latency = 4; }
 341
 342 def M5WriteFSQR5   : SchedWriteRes<[M5UnitFSQR]>  { let Latency = 5;
 343                                                     let ReleaseAtCycles = [2]; }
 344 def M5WriteFSQR7   : SchedWriteRes<[M5UnitFSQR]>  { let Latency = 7;
 345                                                     let ReleaseAtCycles = [4]; }
 346 def M5WriteFSQR8   : SchedWriteRes<[M5UnitFSQR]>  { let Latency = 8;
 347                                                     let ReleaseAtCycles = [5]; }
 348 def M5WriteFSQR12  : SchedWriteRes<[M5UnitFSQR]>  { let Latency = 12;
 349                                                     let ReleaseAtCycles = [9]; }
 350
 351 def M5WriteNALU1   : SchedWriteRes<[M5UnitNALU]>  { let Latency = 1; }
 352 def M5WriteNALU2   : SchedWriteRes<[M5UnitNALU]>  { let Latency = 2; }
 353
 354 def M5WriteNDOT2   : SchedWriteRes<[M5UnitNDOT]>  { let Latency = 2; }
 355
 356 def M5WriteNCRY2   : SchedWriteRes<[M5UnitNCRY]>  { let Latency = 2; }
 357 def M5WriteNCRY1A  : SchedWriteRes<[M5UnitNCRY0]> { let Latency = 1; }
 358 def M5WriteNCRY2A  : SchedWriteRes<[M5UnitNCRY0]> { let Latency = 2; }
 359 def M5WriteNCRY3A  : SchedWriteRes<[M5UnitNCRY0]> { let Latency = 3; }
 360 def M5WriteNCRY5A  : SchedWriteRes<[M5UnitNCRY]>  { let Latency = 5; }
 361
 362 def M5WriteNHAD1   : SchedWriteRes<[M5UnitNHAD]>  { let Latency = 1; }
 363 def M5WriteNHAD3   : SchedWriteRes<[M5UnitNHAD]>  { let Latency = 3; }
 364
 365 def M5WriteNMSC1   : SchedWriteRes<[M5UnitNMSC]>  { let Latency = 1; }
 366 def M5WriteNMSC2   : SchedWriteRes<[M5UnitNMSC]>  { let Latency = 2; }
 367
 368 def M5WriteNMUL3   : SchedWriteRes<[M5UnitNMUL]>  { let Latency = 3; }
 369
 370 def M5WriteNSHF1   : SchedWriteRes<[M5UnitNSHF]>  { let Latency = 1; }
 371 def M5WriteNSHF2   : SchedWriteRes<[M5UnitNSHF]>  { let Latency = 2; }
 372 def M5WriteNSHFA   : SchedWriteRes<[M5UnitNSHF]>  { let Latency = 2; }
 373 def M5WriteNSHFB   : SchedWriteRes<[M5UnitNSHF]>  { let Latency = 4;
 374                                                     let NumMicroOps = 2; }
 375 def M5WriteNSHFC   : SchedWriteRes<[M5UnitNSHF]>  { let Latency = 6;
 376                                                     let NumMicroOps = 3; }
 377 def M5WriteNSHFD   : SchedWriteRes<[M5UnitNSHF]>  { let Latency = 8;
 378                                                     let NumMicroOps = 4; }
 379
 380 def M5WriteNSHT2   : SchedWriteRes<[M5UnitNSHT]>  { let Latency = 2; }
 381 def M5WriteNSHT4A  : SchedWriteRes<[M5UnitNSHT1]> { let Latency = 4; }
 382
 383 def M5WriteVLDA    : SchedWriteRes<[M5UnitL,
 384                                     M5UnitL]>     { let Latency = 6;
 385                                                     let NumMicroOps = 2; }
 386 def M5WriteVLDB    : SchedWriteRes<[M5UnitL,
 387                                     M5UnitL,
 388                                     M5UnitL]>     { let Latency = 7;
 389                                                     let NumMicroOps = 3; }
 390 def M5WriteVLDC    : SchedWriteRes<[M5UnitL,
 391                                     M5UnitL,
 392                                     M5UnitL,
 393                                     M5UnitL]>     { let Latency = 7;
 394                                                     let NumMicroOps = 4; }
 395 def M5WriteVLDD    : SchedWriteRes<[M5UnitL,
 396                                     M5UnitNSHF]>  { let Latency = 7;
 397                                                     let NumMicroOps = 2;
 398                                                     let ReleaseAtCycles = [2, 1]; }
 399 def M5WriteVLDF    : SchedWriteRes<[M5UnitL,
 400                                     M5UnitL]>     { let Latency = 11;
 401                                                     let NumMicroOps = 2;
 402                                                     let ReleaseAtCycles = [6, 5]; }
 403 def M5WriteVLDG    : SchedWriteRes<[M5UnitL,
 404                                     M5UnitNSHF,
 405                                     M5UnitNSHF]>  { let Latency = 7;
 406                                                     let NumMicroOps = 3;
 407                                                     let ReleaseAtCycles = [2, 1, 1]; }
 408 def M5WriteVLDI    : SchedWriteRes<[M5UnitL,
 409                                     M5UnitL,
 410                                     M5UnitL]>     { let Latency = 13;
 411                                                     let NumMicroOps = 3; }
 412 def M5WriteVLDJ    : SchedWriteRes<[M5UnitL,
 413                                     M5UnitNSHF,
 414                                     M5UnitNSHF,
 415                                     M5UnitNSHF]>  { let Latency = 8;
 416                                                     let NumMicroOps = 4; }
 417 def M5WriteVLDK    : SchedWriteRes<[M5UnitL,
 418                                     M5UnitNSHF,
 419                                     M5UnitNSHF,
 420                                     M5UnitNSHF,
 421                                     M5UnitNSHF]>  { let Latency = 8;
 422                                                     let NumMicroOps = 5; }
 423 def M5WriteVLDL    : SchedWriteRes<[M5UnitL,
 424                                     M5UnitNSHF,
 425                                     M5UnitNSHF,
 426                                     M5UnitL,
 427                                     M5UnitNSHF]>  { let Latency = 8;
 428                                                     let NumMicroOps = 5; }
 429 def M5WriteVLDM    : SchedWriteRes<[M5UnitL,
 430                                     M5UnitNSHF,
 431                                     M5UnitNSHF,
 432                                     M5UnitL,
 433                                     M5UnitNSHF,
 434                                     M5UnitNSHF]>  { let Latency = 8;
 435                                                     let NumMicroOps = 6; }
 436 def M5WriteVLDN    : SchedWriteRes<[M5UnitL,
 437                                     M5UnitL,
 438                                     M5UnitL,
 439                                     M5UnitL]>     { let Latency = 15;
 440                                                     let NumMicroOps = 4;
 441                                                     let ReleaseAtCycles = [2, 2, 2, 2]; }
 442
 443 def M5WriteVST1    : SchedWriteRes<[M5UnitS,
 444                                     M5UnitFST]> { let Latency = 1;
 445                                                   let NumMicroOps = 1; }
 446 def M5WriteVSTA    : SchedWriteRes<[M5UnitS,
 447                                     M5UnitFST,
 448                                     M5UnitS,
 449                                     M5UnitFST]> { let Latency = 2;
 450                                                   let NumMicroOps = 2; }
 451 def M5WriteVSTB    : SchedWriteRes<[M5UnitS,
 452                                     M5UnitFST,
 453                                     M5UnitS,
 454                                     M5UnitFST,
 455                                     M5UnitS,
 456                                     M5UnitFST]> { let Latency = 3;
 457                                                   let NumMicroOps = 3; }
 458 def M5WriteVSTC    : SchedWriteRes<[M5UnitS,
 459                                     M5UnitFST,
 460                                     M5UnitS,
 461                                     M5UnitFST,
 462                                     M5UnitS,
 463                                     M5UnitFST,
 464                                     M5UnitS,
 465                                     M5UnitFST]> { let Latency = 4;
 466                                                   let NumMicroOps = 4; }
 467 def M5WriteVSTD    : SchedWriteRes<[M5UnitS,
 468                                     M5UnitFST]> { let Latency = 2; }
 469 def M5WriteVSTE    : SchedWriteRes<[M5UnitS,
 470                                     M5UnitFST,
 471                                     M5UnitS,
 472                                     M5UnitFST]> { let Latency = 2;
 473                                                   let NumMicroOps = 1; }
 474 def M5WriteVSTF    : SchedWriteRes<[M5UnitNSHF,
 475                                     M5UnitNSHF,
 476                                     M5UnitS,
 477                                     M5UnitFST]> { let Latency = 4;
 478                                                   let NumMicroOps = 3; }
 479 def M5WriteVSTG    : SchedWriteRes<[M5UnitNSHF,
 480                                     M5UnitNSHF,
 481                                     M5UnitNSHF,
 482                                     M5UnitS,
 483                                     M5UnitFST,
 484                                     M5UnitS,
 485                                     M5UnitFST]> { let Latency = 4;
 486                                                   let NumMicroOps = 5; }
 487 def M5WriteVSTH    : SchedWriteRes<[M5UnitS0,
 488                                     M5UnitFST]> { let Latency = 1;
 489                                                   let NumMicroOps = 1; }
 490 def M5WriteVSTI    : SchedWriteRes<[M5UnitNSHF,
 491                                     M5UnitNSHF,
 492                                     M5UnitNSHF,
 493                                     M5UnitNSHF,
 494                                     M5UnitS,
 495                                     M5UnitFST,
 496                                     M5UnitS,
 497                                     M5UnitFST,
 498                                     M5UnitS,
 499                                     M5UnitFST,
 500                                     M5UnitS,
 501                                     M5UnitFST]> { let Latency = 8;
 502                                                   let NumMicroOps = 5;
 503                                                   let ReleaseAtCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; }
 504 def M5WriteVSTJ    : SchedWriteRes<[M5UnitA,
 505                                     M5UnitS0,
 506                                     M5UnitFST]> { let Latency = 1;
 507                                                   let NumMicroOps = 1; }
 508 def M5WriteVSTK    : SchedWriteRes<[M5UnitAX,
 509                                     M5UnitS,
 510                                     M5UnitFST]> { let Latency = 3;
 511                                                   let NumMicroOps = 2; }
 512 def M5WriteVSTL    : SchedWriteRes<[M5UnitNSHF,
 513                                     M5UnitNSHF,
 514                                     M5UnitS,
 515                                     M5UnitFST,
 516                                     M5UnitS,
 517                                     M5UnitFST]> { let Latency = 4;
 518                                                     let NumMicroOps = 4;
 519                                                     let ReleaseAtCycles = [1, 1, 2, 1, 2, 1]; }
 520 def M5WriteVSTY   : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteVSTK]>,
 521                                        SchedVar<NoSchedPred,         [WriteVST]>]>;
 522
 523 // Special cases.
 524 def M5WriteCOPY    : SchedWriteVariant<[SchedVar<ExynosFPPred, [M5WriteNALU2]>,
 525                                         SchedVar<NoSchedPred,  [M5WriteZ0]>]>;
 526 def M5WriteMOVI    : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M5WriteZ0]>,
 527                                         SchedVar<NoSchedPred,       [M5WriteNALU1]>]>;
 528
 529 // Fast forwarding.
 530 def M5ReadFM1      : SchedReadAdvance<+1, [M5WriteF2]>;
 531 def M5ReadAESM2    : SchedReadAdvance<+2, [M5WriteNCRY2]>;
 532 def M5ReadFMACM1   : SchedReadAdvance<+1, [M5WriteFMAC4]>;
 533 def M5ReadNMULM1   : SchedReadAdvance<+1, [M5WriteNMUL3]>;
 534
 535 //===----------------------------------------------------------------------===//
 536 // Coarse scheduling model.
 537
 538 // Branch instructions.
 539 def : SchedAlias<WriteBr,    M5WriteZ0>;
 540 def : SchedAlias<WriteBrReg, M5WriteC1>;
 541
 542 // Arithmetic and logical integer instructions.
 543 def : SchedAlias<WriteI,     M5WriteA1W>;
 544 def : SchedAlias<WriteIEReg, M5WriteA1W>; // FIXME: M5WriteAX crashes TableGen.
 545 def : SchedAlias<WriteISReg, M5WriteA1W>; // FIXME: M5WriteAX crashes TableGen.
 546 def : SchedAlias<WriteIS,    M5WriteA1W>;
 547
 548 // Move instructions.
 549 def : SchedAlias<WriteImm, M5WriteA1W>;
 550
 551 // Divide and multiply instructions.
 552 def : SchedAlias<WriteID32, M5WriteD10>;
 553 def : SchedAlias<WriteID64, M5WriteD16>;
 554 def : SchedAlias<WriteIM32, M5WriteC2>;
 555 def : SchedAlias<WriteIM64, M5WriteCA>;
 556
 557 // Miscellaneous instructions.
 558 def : SchedAlias<WriteExtr, M5WriteAYW>;
 559
 560 // Addressing modes.
 561 def : SchedAlias<WriteAdr,    M5WriteZ1>;
 562 def : SchedAlias<ReadAdrBase, M5ReadAdrBase>;
 563
 564 // Load instructions.
 565 def : SchedAlias<WriteLD,    M5WriteL4>;
 566 def : SchedAlias<WriteLDHi,  M5WriteZ4>;
 567 def : SchedAlias<WriteLDIdx, M5WriteLX>;
 568
 569 // Store instructions.
 570 def : SchedAlias<WriteST,    M5WriteS1>;
 571 def : SchedAlias<WriteSTP,   M5WriteS1>;
 572 def : SchedAlias<WriteSTX,   M5WriteS1>;
 573 def : SchedAlias<WriteSTIdx, M5WriteSX>;
 574
 575 // Atomic load and store instructions.
 576 def : SchedAlias<WriteAtomic, M5WriteLGW>;
 577
 578 // FP data instructions.
 579 def : SchedAlias<WriteF,    M5WriteFADD2>;
 580 def : SchedAlias<WriteFCmp, M5WriteNMSC2>;
 581 def : SchedAlias<WriteFDiv, M5WriteFDIV12>;
 582 def : SchedAlias<WriteFMul, M5WriteFMAC3>;
 583
 584 // FP miscellaneous instructions.
 585 def : SchedAlias<WriteFCvt,  M5WriteFCVT2>;
 586 def : SchedAlias<WriteFImm,  M5WriteNALU1>;
 587 def : SchedAlias<WriteFCopy, M5WriteNALU2>;
 588
 589 // FP load instructions.
 590 def : SchedAlias<WriteVLD, M5WriteL6>;
 591
 592 // FP store instructions.
 593 def : SchedAlias<WriteVST, M5WriteVST1>;
 594
 595 // ASIMD FP instructions.
 596 def : SchedAlias<WriteVd, M5WriteNALU1>;
 597 def : SchedAlias<WriteVq, M5WriteNALU1>;
 598
 599 // Other miscellaneous instructions.
 600 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
 601 def : WriteRes<WriteHint,    []> { let Latency = 1; }
 602 def : WriteRes<WriteSys,     []> { let Latency = 1; }
 603
 604 //===----------------------------------------------------------------------===//
 605 // Generic fast forwarding.
 606
 607 // TODO: Add FP register forwarding rules.
 608
 609 def : ReadAdvance<ReadI,       0>;
 610 def : ReadAdvance<ReadISReg,   0>;
 611 def : ReadAdvance<ReadIEReg,   0>;
 612 def : ReadAdvance<ReadIM,      0>;
 613 // TODO: The forwarding for 32 bits actually saves 2 cycles.
 614 def : ReadAdvance<ReadIMA,     3, [WriteIM32, WriteIM64]>;
 615 def : ReadAdvance<ReadID,      0>;
 616 def : ReadAdvance<ReadExtrHi,  0>;
 617 def : ReadAdvance<ReadAdrBase, 0>;
 618 def : ReadAdvance<ReadVLD,     0>;
 619 def : ReadAdvance<ReadST,      0>;
 620
 621 //===----------------------------------------------------------------------===//
 622 // Finer scheduling model.
 623
 624 // Branch instructions
 625 def : InstRW<[M5WriteB1],  (instrs Bcc)>;
 626 def : InstRW<[M5WriteAFX], (instrs BL)>;
 627 def : InstRW<[M5WriteBX],  (instrs BLR)>;
 628 def : InstRW<[M5WriteC1],  (instregex "^CBN?Z[WX]")>;
 629 def : InstRW<[M5WriteAD],  (instregex "^TBN?ZW")>;
 630 def : InstRW<[M5WriteAB],  (instregex "^TBN?ZX")>;
 631
 632 // Arithmetic and logical integer instructions.
 633 def : InstRW<[M5WriteA1W], (instregex "^(ADC|SBC)S?Wr$")>;
 634 def : InstRW<[M5WriteA1X], (instregex "^(ADC|SBC)S?Xr$")>;
 635 def : InstRW<[M5WriteAXW], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)Wrs$")>;
 636 def : InstRW<[M5WriteAXX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)Xrs$")>;
 637 def : InstRW<[M5WriteAUW], (instrs ORRWrs)>;
 638 def : InstRW<[M5WriteAUX], (instrs ORRXrs)>;
 639 def : InstRW<[M5WriteAXW], (instregex "^(ADD|AND|BIC|SUB)SWrs$")>;
 640 def : InstRW<[M5WriteAXX], (instregex "^(ADD|AND|BIC|SUB)SXrs$")>;
 641 def : InstRW<[M5WriteAXW], (instregex "^(ADD|SUB)S?Wrx(64)?$")>;
 642 def : InstRW<[M5WriteAXX], (instregex "^(ADD|SUB)S?Xrx(64)?$")>;
 643 def : InstRW<[M5WriteAVW], (instrs ADDWri, ORRWri)>;
 644 def : InstRW<[M5WriteAVX], (instrs ADDXri, ORRXri)>;
 645 def : InstRW<[M5WriteA1W], (instregex "^CCM[NP]W[ir]$")>;
 646 def : InstRW<[M5WriteA1X], (instregex "^CCM[NP]X[ir]$")>;
 647 def : InstRW<[M5WriteA1W], (instrs CSELWr, CSINCWr, CSINVWr, CSNEGWr)>;
 648 def : InstRW<[M5WriteA1X], (instrs CSELXr, CSINCXr, CSINVXr, CSNEGXr)>;
 649
 650 // Move instructions.
 651 def : InstRW<[M5WriteCOPY], (instrs COPY)>;
 652 def : InstRW<[M5WriteZ0],   (instrs ADR, ADRP)>;
 653 def : InstRW<[M5WriteZ0],   (instregex "^MOV[NZ][WX]i$")>;
 654
 655 // Shift instructions.
 656 def : InstRW<[M5WriteA1W], (instrs ASRVWr, LSLVWr, LSRVWr, RORVWr)>;
 657 def : InstRW<[M5WriteA1X], (instrs ASRVXr, LSLVXr, LSRVXr, RORVXr)>;
 658
 659 // Miscellaneous instructions.
 660 def : InstRW<[M5WriteAYW], (instrs EXTRWrri)>;
 661 def : InstRW<[M5WriteAYX], (instrs EXTRXrri)>;
 662 def : InstRW<[M5WriteA1W], (instrs BFMWri, SBFMWri, UBFMWri)>;
 663 def : InstRW<[M5WriteA1X], (instrs BFMXri, SBFMXri, UBFMXri)>;
 664 def : InstRW<[M5WriteA1W], (instrs CLSWr, CLZWr)>;
 665 def : InstRW<[M5WriteA1X], (instrs CLSXr, CLZXr)>;
 666 def : InstRW<[M5WriteA1W], (instrs RBITWr, REVWr, REV16Wr)>;
 667 def : InstRW<[M5WriteA1X], (instrs RBITXr, REVXr, REV16Xr, REV32Xr)>;
 668
 669 // Load instructions.
 670 def : InstRW<[M5WriteLD,
 671               WriteLDHi,
 672               WriteAdr],    (instregex "^LDP(SW|W|X)(post|pre)")>;
 673 def : InstRW<[M5WriteL5,
 674               ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>;
 675 def : InstRW<[WriteLDIdx,
 676               ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>;
 677 def : InstRW<[M5WriteL5,
 678               ReadAdrBase], (instrs PRFMroW)>;
 679 def : InstRW<[WriteLDIdx,
 680               ReadAdrBase], (instrs PRFMroX)>;
 681
 682 // Store instructions.
 683 def : InstRW<[M5WriteSB,
 684               ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>;
 685 def : InstRW<[WriteST,
 686               ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>;
 687
 688 // Atomic load and store instructions.
 689 def : InstRW<[M5WriteLGW], (instregex "^CAS(A|AL|L)?[BHW]$")>;
 690 def : InstRW<[M5WriteLGX], (instregex "^CAS(A|AL|L)?X$")>;
 691 def : InstRW<[M5WriteLFW], (instregex "^CASP(A|AL|L)?W$")>;
 692 def : InstRW<[M5WriteLFX], (instregex "^CASP(A|AL|L)?X$")>;
 693 def : InstRW<[M5WriteLGW], (instregex "^LD(ADD|CLR|EOR|SET|[SU]MAX|[SU]MIN)(A|AL|L)?[BHW]$")>;
 694 def : InstRW<[M5WriteLGX], (instregex "^LD(ADD|CLR|EOR|SET|[SU]MAX|[SU]MIN)(A|AL|L)?X$")>;
 695 def : InstRW<[M5WriteLGW], (instregex "^SWP(A|AL|L)?[BHW]$")>;
 696 def : InstRW<[M5WriteLGX], (instregex "^SWP(A|AL|L)?X$")>;
 697
 698 // FP data instructions.
 699 def : InstRW<[M5WriteNSHF1],  (instrs FABSHr, FABSSr,FABSDr)>;
 700 def : InstRW<[M5WriteFADD2],  (instregex "^F(ADD|SUB)[HSD]rr")>;
 701 def : InstRW<[M5WriteFADD2],  (instregex "^FADDPv.i(16|32|64)")>;
 702 def : InstRW<[M5WriteNEONQ],  (instregex "^FCCMPE?[HSD]rr")>;
 703 def : InstRW<[M5WriteNMSC2],  (instregex "^FCMPE?[HSD]r[ir]")>;
 704 def : InstRW<[M5WriteNMSC1],  (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)(16|32|64|v1)")>;
 705 def : InstRW<[M5WriteFDIV5],  (instrs FDIVHrr)>;
 706 def : InstRW<[M5WriteFDIV7],  (instrs FDIVSrr)>;
 707 def : InstRW<[M5WriteFDIV12], (instrs FDIVDrr)>;
 708 def : InstRW<[M5WriteNMSC1],  (instregex "^F(MAX|MIN)(NM)?[HSD]rr")>;
 709 def : InstRW<[M5WriteFMAC3],  (instregex "^FN?MUL[HSD]rr")>;
 710 def : InstRW<[M5WriteFMAC3],  (instrs FMULX16, FMULX32, FMULX64)>;
 711 def : InstRW<[M5WriteFMAC4,
 712               M5ReadFMACM1],  (instregex "^FN?M(ADD|SUB)[HSD]rrr")>;
 713 def : InstRW<[M5WriteNALU2],  (instrs FNEGHr, FNEGSr, FNEGDr)>;
 714 def : InstRW<[M5WriteFCVT3A], (instregex "^FRINT.+r")>;
 715 def : InstRW<[M5WriteNEONH],  (instregex "^FCSEL[HSD]rrr")>;
 716 def : InstRW<[M5WriteFSQR5],  (instrs FSQRTHr)>;
 717 def : InstRW<[M5WriteFSQR8],  (instrs FSQRTSr)>;
 718 def : InstRW<[M5WriteFSQR12], (instrs FSQRTDr)>;
 719
 720 // FP miscellaneous instructions.
 721 def : InstRW<[M5WriteFCVT2],  (instregex "^FCVT[HSD][HSD]r")>;
 722 def : InstRW<[M5WriteFCVTC],  (instregex "^[SU]CVTF[SU][XW][HSD]ri")>;
 723 def : InstRW<[M5WriteFCVTB],  (instregex "^FCVT[AMNPZ][SU][SU][XW][HSD]r")>;
 724 def : InstRW<[M5WriteNALU1],  (instregex "^FMOV[HSD]i")>;
 725 def : InstRW<[M5WriteNALU2],  (instregex "^FMOV[HSD]r")>;
 726 def : InstRW<[M5WriteSA],     (instregex "^FMOV[WX][HSD]r")>;
 727 def : InstRW<[M5WriteFCVTA],  (instregex "^FMOV[HSD][WX]r")>;
 728 def : InstRW<[M5WriteNEONI],  (instregex "^FMOVXDHighr")>;
 729 def : InstRW<[M5WriteNEONK],  (instregex "^FMOVDXHighr")>;
 730 def : InstRW<[M5WriteFCVT3],  (instregex "^F(RECP|RSQRT)Ev1(f16|i32|i64)")>;
 731 def : InstRW<[M5WriteNMSC1],  (instregex "^FRECPXv1")>;
 732 def : InstRW<[M5WriteFMAC4],  (instregex "^F(RECP|RSQRT)S(16|32|64)")>;
 733
 734 // FP load instructions.
 735 def : InstRW<[WriteVLD],    (instregex "^LDR[SDQ]l")>;
 736 def : InstRW<[WriteVLD],    (instregex "^LDUR[BHSDQ]i")>;
 737 def : InstRW<[WriteVLD,
 738               WriteAdr],    (instregex "^LDR[BHSDQ](post|pre)")>;
 739 def : InstRW<[WriteVLD],    (instregex "^LDR[BHSDQ]ui")>;
 740 def : InstRW<[M5WriteLE,
 741               ReadAdrBase], (instregex "^LDR[BHSDQ]roW")>;
 742 def : InstRW<[WriteVLD,
 743               ReadAdrBase], (instregex "^LDR[BHSD]roX")>;
 744 def : InstRW<[M5WriteLY,
 745               ReadAdrBase], (instrs LDRQroX)>;
 746 def : InstRW<[WriteVLD,
 747               M5WriteLH],   (instregex "^LDN?P[SD]i")>;
 748 def : InstRW<[M5WriteLA,
 749               M5WriteLH],   (instregex "^LDN?PQi")>;
 750 def : InstRW<[M5WriteLB,
 751               M5WriteLH,
 752               WriteAdr],    (instregex "^LDP[SD](post|pre)")>;
 753 def : InstRW<[M5WriteLC,
 754               M5WriteLH,
 755               WriteAdr],    (instregex "^LDPQ(post|pre)")>;
 756
 757 // FP store instructions.
 758 def : InstRW<[WriteVST],    (instregex "^STUR[BHSDQ]i")>;
 759 def : InstRW<[WriteVST,
 760               WriteAdr],    (instregex "^STR[BHSDQ](post|pre)")>;
 761 def : InstRW<[WriteVST],    (instregex "^STR[BHSDQ]ui")>;
 762 def : InstRW<[WriteVST,
 763               ReadAdrBase], (instregex "^STR[BHSD]ro[WX]")>;
 764 def : InstRW<[M5WriteVSTK,
 765               ReadAdrBase], (instregex "^STRQroW")>;
 766 def : InstRW<[M5WriteVSTY,
 767               ReadAdrBase], (instregex "^STRQroX")>;
 768 def : InstRW<[WriteVST],    (instregex "^STN?P[SD]i")>;
 769 def : InstRW<[M5WriteVSTH], (instregex "^STN?PQi")>;
 770 def : InstRW<[WriteVST,
 771               WriteAdr],    (instregex "^STP[SD](post|pre)")>;
 772 def : InstRW<[M5WriteVSTJ,
 773               WriteAdr],    (instregex "^STPQ(post|pre)")>;
 774
 775 // ASIMD instructions.
 776 def : InstRW<[M5WriteNHAD1],  (instregex "^[SU]ABDL?v")>;
 777 def : InstRW<[M5WriteNHAD3],  (instregex "^[SU]ABAL?v")>;
 778 def : InstRW<[M5WriteNMSC1],  (instregex "^ABSv")>;
 779 def : InstRW<[M5WriteNALU2],  (instregex "^(ADD|NEG|SUB)v")>;
 780 def : InstRW<[M5WriteNHAD3],  (instregex "^[SU]?ADDL?Pv")>;
 781 def : InstRW<[M5WriteNHAD3],  (instregex "^[SU]H(ADD|SUB)v")>;
 782 def : InstRW<[M5WriteNHAD3],  (instregex "^[SU](ADD|SUB)[LW]v")>;
 783 def : InstRW<[M5WriteNHAD3],  (instregex "^R?(ADD|SUB)HN2?v")>;
 784 def : InstRW<[M5WriteNHAD3],  (instregex "^[SU]Q(ADD|SUB)v")>;
 785 def : InstRW<[M5WriteNHAD3],  (instregex "^(SU|US)QADDv")>;
 786 def : InstRW<[M5WriteNHAD3],  (instregex "^[SU]RHADDv")>;
 787 def : InstRW<[M5WriteNMSC1],  (instregex "^SQ(ABS|NEG)v")>;
 788 def : InstRW<[M5WriteNHAD3],  (instregex "^[SU]?ADDL?Vv")>;
 789 def : InstRW<[M5WriteNMSC1],  (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>;
 790 def : InstRW<[M5WriteNALU2],  (instregex "^CMTSTv")>;
 791 def : InstRW<[M5WriteNALU2],  (instregex "^(AND|BIC|EOR|NOT|ORN|ORR)v")>;
 792 def : InstRW<[M5WriteNMSC1],  (instregex "^[SU](MIN|MAX)v")>;
 793 def : InstRW<[M5WriteNMSC2],  (instregex "^[SU](MIN|MAX)Pv")>;
 794 def : InstRW<[M5WriteNHAD3],  (instregex "^[SU](MIN|MAX)Vv")>;
 795 def : InstRW<[M5WriteNMUL3],  (instregex "^(SQR?D)?MULH?v")>;
 796 def : InstRW<[M5WriteNMUL3,
 797               M5ReadNMULM1],  (instregex "^ML[AS]v")>;
 798 def : InstRW<[M5WriteNMUL3,
 799               M5ReadNMULM1],  (instregex "^SQRDML[AS]H")>;
 800 def : InstRW<[M5WriteNMUL3],  (instregex "^(S|U|SQD)ML[AS]L(v1(i32|i64)|v2i32|v4i16|v8i8)")>;
 801 def : InstRW<[M5WriteNMUL3,
 802               M5ReadNMULM1],  (instregex "^(S|U|SQD)ML[AS]L(v4i32|v8i16|v16i8)")>;
 803 def : InstRW<[M5WriteNMUL3,
 804               M5ReadNMULM1],  (instregex "^(S|U|SQD)MULL(v1(i32|i64)|v2i32|v4i16|v8i8)")>;
 805 def : InstRW<[M5WriteNMUL3,
 806               M5ReadNMULM1],  (instregex "^(S|U|SQD)MULL(v4i32|v8i16|v16i8)")>;
 807 def : InstRW<[M5WriteNDOT2],  (instregex "^[SU]DOT(lane)?v")>;
 808 def : InstRW<[M5WriteNHAD3],  (instregex "^[SU]ADALPv")>;
 809 def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]R?SRA[dv]")>;
 810 def : InstRW<[M5WriteNSHT2],  (instregex "^SHL[dv]")>;
 811 def : InstRW<[M5WriteNSHT2],  (instregex "^S[LR]I[dv]")>;
 812 def : InstRW<[M5WriteNSHT2],  (instregex "^[SU]SH[LR][dv]")>;
 813 def : InstRW<[M5WriteNSHT2],  (instregex "^[SU]?SHLLv")>;
 814 def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]?Q?R?SHRU?N[bhsv]")>;
 815 def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]RSH[LR][dv]")>;
 816 def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]QR?SHLU?[bhsdv]")>;
 817
 818 // ASIMD FP instructions.
 819 def : InstRW<[M5WriteNSHF2],  (instregex "^FABSv.f(16|32|64)")>;
 820 def : InstRW<[M5WriteFADD2],  (instregex "^F(ABD|ADD|SUB)v.f(16|32|64)")>;
 821 def : InstRW<[M5WriteFADD2],  (instregex "^FADDPv.f(16|32|64)")>;
 822 def : InstRW<[M5WriteNMSC1],  (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>;
 823 def : InstRW<[M5WriteFCVT2],  (instregex "^FCVT(L|N|XN)v")>;
 824 def : InstRW<[M5WriteFCVT2A], (instregex "^FCVT[AMNPZ][SU]v")>;
 825 def : InstRW<[M5WriteFCVT2],  (instregex "^[SU]CVTFv.[fi](16|32|64)")>;
 826 def : InstRW<[M5WriteFDIV7],  (instrs FDIVv4f16)>;
 827 def : InstRW<[M5WriteNEONV],  (instrs FDIVv8f16)>;
 828 def : InstRW<[M5WriteFDIV7],  (instrs FDIVv2f32)>;
 829 def : InstRW<[M5WriteNEONV],  (instrs FDIVv4f32)>;
 830 def : InstRW<[M5WriteNEONW],  (instrs FDIVv2f64)>;
 831 def : InstRW<[M5WriteNMSC1],  (instregex "^F(MAX|MIN)(NM)?v")>;
 832 def : InstRW<[M5WriteNMSC2],  (instregex "^F(MAX|MIN)(NM)?Pv")>;
 833 def : InstRW<[M5WriteNEONZ],  (instregex "^F(MAX|MIN)(NM)?Vv")>;
 834 def : InstRW<[M5WriteFMAC3],  (instregex "^FMULX?v.[fi](16|32|64)")>;
 835 def : InstRW<[M5WriteFMAC4,
 836               M5ReadFMACM1],  (instregex "^FML[AS]v.[fi](16|32|64)")>;
 837 def : InstRW<[M5WriteNALU2],  (instregex "^FNEGv.f(16|32|64)")>;
 838 def : InstRW<[M5WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
 839 def : InstRW<[M5WriteFSQR7],  (instrs FSQRTv4f16)>;
 840 def : InstRW<[M5WriteNEONU],  (instrs FSQRTv8f16)>;
 841 def : InstRW<[M5WriteFSQR8],  (instrs FSQRTv2f32)>;
 842 def : InstRW<[M5WriteNEONX],  (instrs FSQRTv4f32)>;
 843 def : InstRW<[M5WriteNEONY],  (instrs FSQRTv2f64)>;
 844
 845 // ASIMD miscellaneous instructions.
 846 def : InstRW<[M5WriteNALU2],  (instregex "^RBITv")>;
 847 def : InstRW<[M5WriteNALU2],  (instregex "^(BIF|BIT|BSL|BSP)v")>;
 848 def : InstRW<[M5WriteNALU2],  (instregex "^CL[STZ]v")>;
 849 def : InstRW<[M5WriteNEONB],  (instregex "^DUPv.+gpr")>;
 850 def : InstRW<[M5WriteNSHF2],  (instregex "^DUP(i8|i16|i32|i64)$")>;
 851 def : InstRW<[M5WriteNSHF2],  (instregex "^DUPv.+lane")>;
 852 def : InstRW<[M5WriteNSHF2],  (instregex "^EXTv")>;
 853 def : InstRW<[M5WriteNSHT4A], (instregex "^XTNv")>;
 854 def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]?QXTU?Nv")>;
 855 def : InstRW<[M5WriteNEONB],  (instregex "^INSv.+gpr")>;
 856 def : InstRW<[M5WriteNSHF2],  (instregex "^INSv.+lane")>;
 857 def : InstRW<[M5WriteMOVI],   (instregex "^(MOV|MVN)I")>;
 858 def : InstRW<[M5WriteNALU1],  (instregex "^FMOVv.f(16|32|64)")>;
 859 def : InstRW<[M5WriteFCVT3],  (instregex "^F(RECP|RSQRT)Ev[248]f(16|32|64)")>;
 860 def : InstRW<[M5WriteFCVT3],  (instregex "^U(RECP|RSQRT)Ev[24]i32")>;
 861 def : InstRW<[M5WriteFMAC4],  (instregex "^F(RECP|RSQRT)Sv.f(16|32|64)")>;
 862 def : InstRW<[M5WriteNSHF2],  (instregex "^REV(16|32|64)v")>;
 863 def : InstRW<[M5WriteNSHFA],  (instregex "^TB[LX]v(8|16)i8One")>;
 864 def : InstRW<[M5WriteNSHFB],  (instregex "^TB[LX]v(8|16)i8Two")>;
 865 def : InstRW<[M5WriteNSHFC],  (instregex "^TB[LX]v(8|16)i8Three")>;
 866 def : InstRW<[M5WriteNSHFD],  (instregex "^TB[LX]v(8|16)i8Four")>;
 867 def : InstRW<[M5WriteNEONP],  (instregex "^[SU]MOVv")>;
 868 def : InstRW<[M5WriteNSHF2],  (instregex "^(TRN|UZP|ZIP)[12]v")>;
 869
 870 // ASIMD load instructions.
 871 def : InstRW<[WriteVLD],    (instregex "LD1Onev(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
 872 def : InstRW<[WriteVLD,
 873               M5WriteA1X,
 874               WriteAdr],    (instregex "LD1Onev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
 875 def : InstRW<[M5WriteVLDA], (instregex "LD1Twov(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
 876 def : InstRW<[M5WriteVLDA,
 877               M5WriteA1X,
 878               WriteAdr],    (instregex "LD1Twov(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
 879 def : InstRW<[M5WriteVLDB], (instregex "LD1Threev(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
 880 def : InstRW<[M5WriteVLDB,
 881               M5WriteA1X,
 882               WriteAdr],    (instregex "LD1Threev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
 883 def : InstRW<[M5WriteVLDC], (instregex "LD1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
 884 def : InstRW<[M5WriteVLDC,
 885               M5WriteA1X,
 886               WriteAdr],    (instregex "LD1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
 887 def : InstRW<[M5WriteVLDD], (instregex "LD1i(8|16|32|64)$")>;
 888 def : InstRW<[M5WriteVLDD,
 889               M5WriteA1X,
 890               WriteAdr],    (instregex "LD1i(8|16|32|64)_POST$")>;
 891 def : InstRW<[WriteVLD],    (instregex "LD1Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
 892 def : InstRW<[WriteVLD,
 893               M5WriteA1X,
 894               WriteAdr],    (instregex "LD1Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
 895 def : InstRW<[M5WriteVLDF], (instregex "LD2Twov(8b|16b|4h|8h|2s|4s|2d)$")>;
 896 def : InstRW<[M5WriteVLDF,
 897               M5WriteA1X,
 898               WriteAdr],    (instregex "LD2Twov(8b|16b|4h|8h|2s|4s|2d)_POST$")>;
 899 def : InstRW<[M5WriteVLDG], (instregex "LD2i(8|16|32|64)$")>;
 900 def : InstRW<[M5WriteVLDG,
 901               M5WriteA1X,
 902               WriteAdr],    (instregex "LD2i(8|16|32|64)_POST$")>;
 903 def : InstRW<[M5WriteVLDA], (instregex "LD2Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
 904 def : InstRW<[M5WriteVLDA,
 905               M5WriteA1X,
 906               WriteAdr],    (instregex "LD2Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
 907 def : InstRW<[M5WriteVLDI], (instregex "LD3Threev(8b|16b|4h|8h|2s|4s|2d)$")>;
 908 def : InstRW<[M5WriteVLDI,
 909               M5WriteA1X,
 910               WriteAdr],    (instregex "LD3Threev(8b|16b|4h|8h|2s|4s|2d)_POST$")>;
 911 def : InstRW<[M5WriteVLDJ], (instregex "LD3i(8|16|32)$")>;
 912 def : InstRW<[M5WriteVLDJ,
 913               M5WriteA1X,
 914               WriteAdr],    (instregex "LD3i(8|16|32)_POST$")>;
 915 def : InstRW<[M5WriteVLDL], (instregex "LD3i64$")>;
 916 def : InstRW<[M5WriteVLDL,
 917               M5WriteA1X,
 918               WriteAdr],    (instregex "LD3i64_POST$")>;
 919 def : InstRW<[M5WriteVLDB], (instregex "LD3Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
 920 def : InstRW<[M5WriteVLDB,
 921               M5WriteA1X],  (instregex "LD3Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
 922 def : InstRW<[M5WriteVLDN], (instregex "LD4Fourv(8b|16b|4h|8h|2s|4s|2d)$")>;
 923 def : InstRW<[M5WriteVLDN,
 924               M5WriteA1X,
 925               WriteAdr],    (instregex "LD4Fourv(8b|16b|4h|8h|2s|4s|2d)_POST$")>;
 926 def : InstRW<[M5WriteVLDK], (instregex "LD4i(8|16|32)$")>;
 927 def : InstRW<[M5WriteVLDK,
 928               M5WriteA1X,
 929               WriteAdr],    (instregex "LD4i(8|16|32)_POST$")>;
 930 def : InstRW<[M5WriteVLDM], (instregex "LD4i64$")>;
 931 def : InstRW<[M5WriteVLDM,
 932               M5WriteA1X,
 933               WriteAdr],    (instregex "LD4i64_POST$")>;
 934 def : InstRW<[M5WriteVLDC], (instregex "LD4Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
 935 def : InstRW<[M5WriteVLDC,
 936               M5WriteA1X,
 937               WriteAdr],    (instregex "LD4Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
 938
 939 // ASIMD store instructions.
 940 def : InstRW<[WriteVST],    (instregex "ST1Onev(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
 941 def : InstRW<[WriteVST,
 942               M5WriteA1X,
 943               WriteAdr],    (instregex "ST1Onev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
 944 def : InstRW<[M5WriteVSTA], (instregex "ST1Twov(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
 945 def : InstRW<[M5WriteVSTA,
 946               M5WriteA1X,
 947               WriteAdr],    (instregex "ST1Twov(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
 948
 949 def : InstRW<[M5WriteVSTB], (instregex "ST1Threev(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
 950 def : InstRW<[M5WriteVSTB,
 951               M5WriteA1X,
 952               WriteAdr],    (instregex "ST1Threev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
 953 def : InstRW<[M5WriteVSTC], (instregex "ST1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
 954 def : InstRW<[M5WriteVSTC,
 955               M5WriteA1X,
 956               WriteAdr],    (instregex "ST1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
 957 def : InstRW<[WriteVST],    (instregex "ST1i(8|16|32|64)$")>;
 958 def : InstRW<[WriteVST,
 959               M5WriteA1X,
 960               WriteAdr],    (instregex "ST1i(8|16|32|64)_POST$")>;
 961 def : InstRW<[M5WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>;
 962 def : InstRW<[M5WriteVSTD,
 963               M5WriteA1X,
 964               WriteAdr],    (instregex "ST2Twov(8b|4h|2s)_POST$")>;
 965 def : InstRW<[M5WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
 966 def : InstRW<[M5WriteVSTE,
 967               M5WriteA1X,
 968               WriteAdr],    (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
 969 def : InstRW<[M5WriteVSTD], (instregex "ST2i(8|16|32|64)$")>;
 970 def : InstRW<[M5WriteVSTD,
 971               M5WriteA1X,
 972               WriteAdr],    (instregex "ST2i(8|16|32|64)_POST$")>;
 973 def : InstRW<[M5WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>;
 974 def : InstRW<[M5WriteVSTF,
 975               M5WriteA1X,
 976               WriteAdr],    (instregex "ST3Threev(8b|4h|2s)_POST$")>;
 977 def : InstRW<[M5WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>;
 978 def : InstRW<[M5WriteVSTG,
 979               M5WriteA1X,
 980               WriteAdr],    (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>;
 981 def : InstRW<[M5WriteVSTA], (instregex "ST3i(8|16|32|64)$")>;
 982 def : InstRW<[M5WriteVSTA,
 983               M5WriteA1X,
 984               WriteAdr],    (instregex "ST3i(8|16|32|64)_POST$")>;
 985 def : InstRW<[M5WriteVSTL], (instregex "ST4Fourv(8b|4h|2s)$")>;
 986 def : InstRW<[M5WriteVSTL,
 987               M5WriteA1X,
 988               WriteAdr],    (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
 989 def : InstRW<[M5WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>;
 990 def : InstRW<[M5WriteVSTI,
 991               M5WriteA1X,
 992               WriteAdr],    (instregex "ST4Fourv(16b|8h|4s|2d)_POST$")>;
 993 def : InstRW<[M5WriteVSTA], (instregex "ST4i(8|16|32|64)$")>;
 994 def : InstRW<[M5WriteVSTA,
 995               M5WriteA1X,
 996               WriteAdr],    (instregex "ST4i(8|16|32|64)_POST$")>;
 997
 998 // Cryptography instructions.
 999 def : InstRW<[M5WriteNCRY2],  (instregex "^AES[DE]")>;
1000 def : InstRW<[M5WriteNCRY2,
1001               M5ReadAESM2],   (instregex "^AESI?MC")>;
1002 def : InstRW<[M5WriteNCRY2A], (instregex "^PMULv")>;
1003 def : InstRW<[M5WriteNCRY1A], (instregex "^PMULLv(1|8)i")>;
1004 def : InstRW<[M5WriteNCRY3A], (instregex "^PMULLv(2|16)i")>;
1005 def : InstRW<[M5WriteNCRY2A], (instregex "^SHA1(H|SU[01])")>;
1006 def : InstRW<[M5WriteNCRY5A], (instregex "^SHA1[CMP]")>;
1007 def : InstRW<[M5WriteNCRY2A], (instrs SHA256SU0rr)>;
1008 def : InstRW<[M5WriteNCRY5A], (instrs SHA256SU1rrr)>;
1009 def : InstRW<[M5WriteNCRY5A], (instregex "^SHA256H2?")>;
1010
1011 // CRC instructions.
1012 def : InstRW<[M5WriteF2,
1013               M5ReadFM1], (instregex "^CRC32C?[BHWX]")>;
1014
1015 } // SchedModel = ExynosM5Model