llvm/lib/Target/AArch64/AArch64SchedPredExynos.td

   1 //===- AArch64SchedPredExynos.td - AArch64 Sched Preds -----*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines scheduling predicate definitions that are used by the
  10 // AArch64 Exynos processors.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // Auxiliary predicates.
  15
  16 // Check the shift in arithmetic and logic instructions.
  17 def ExynosCheckShift : CheckAny<[CheckShiftBy0,
  18                                  CheckAll<
  19                                    [CheckShiftLSL,
  20                                     CheckAny<
  21                                       [CheckShiftBy1,
  22                                        CheckShiftBy2,
  23                                        CheckShiftBy3]>]>]>;
  24
  25 // Exynos predicates.
  26
  27 // Identify BLR specifying the LR register as the indirect target register.
  28 def ExynosBranchLinkLRPred : MCSchedPredicate<
  29                                CheckAll<[CheckOpcode<[BLR]>,
  30                                          CheckRegOperand<0, LR>]>>;
  31
  32 // Identify arithmetic instructions without or with limited extension or shift.
  33 def ExynosArithFn   : TIIPredicate<
  34                         "isExynosArithFast",
  35                         MCOpcodeSwitchStatement<
  36                           [MCOpcodeSwitchCase<
  37                              IsArithExtOp.ValidOpcodes,
  38                              MCReturnStatement<
  39                                CheckAny<[CheckExtBy0,
  40                                          CheckAll<
  41                                            [CheckAny<
  42                                              [CheckExtUXTW,
  43                                               CheckExtUXTX]>,
  44                                             CheckAny<
  45                                               [CheckExtBy1,
  46                                                CheckExtBy2,
  47                                                CheckExtBy3]>]>]>>>,
  48                            MCOpcodeSwitchCase<
  49                              IsArithShiftOp.ValidOpcodes,
  50                              MCReturnStatement<ExynosCheckShift>>,
  51                            MCOpcodeSwitchCase<
  52                              IsArithUnshiftOp.ValidOpcodes,
  53                              MCReturnStatement<TruePred>>,
  54                            MCOpcodeSwitchCase<
  55                              IsArithImmOp.ValidOpcodes,
  56                              MCReturnStatement<TruePred>>],
  57                           MCReturnStatement<FalsePred>>>;
  58 def ExynosArithPred : MCSchedPredicate<ExynosArithFn>;
  59
  60 // Identify logic instructions with limited shift.
  61 def ExynosLogicFn   : TIIPredicate<
  62                         "isExynosLogicFast",
  63                         MCOpcodeSwitchStatement<
  64                           [MCOpcodeSwitchCase<
  65                              IsLogicShiftOp.ValidOpcodes,
  66                              MCReturnStatement<ExynosCheckShift>>,
  67                            MCOpcodeSwitchCase<
  68                              IsLogicUnshiftOp.ValidOpcodes,
  69                              MCReturnStatement<TruePred>>,
  70                            MCOpcodeSwitchCase<
  71                              IsLogicImmOp.ValidOpcodes,
  72                              MCReturnStatement<TruePred>>],
  73                           MCReturnStatement<FalsePred>>>;
  74 def ExynosLogicPred : MCSchedPredicate<ExynosLogicFn>;
  75
  76 // Identify more logic instructions with limited shift.
  77 def ExynosLogicExFn   : TIIPredicate<
  78                           "isExynosLogicExFast",
  79                           MCOpcodeSwitchStatement<
  80                             [MCOpcodeSwitchCase<
  81                                IsLogicShiftOp.ValidOpcodes,
  82                                MCReturnStatement<
  83                                  CheckAny<
  84                                    [ExynosCheckShift,
  85                                     CheckAll<
  86                                      [CheckShiftLSL,
  87                                       CheckShiftBy8]>]>>>,
  88                              MCOpcodeSwitchCase<
  89                                IsLogicUnshiftOp.ValidOpcodes,
  90                                MCReturnStatement<TruePred>>,
  91                              MCOpcodeSwitchCase<
  92                                IsLogicImmOp.ValidOpcodes,
  93                                MCReturnStatement<TruePred>>],
  94                             MCReturnStatement<FalsePred>>>;
  95 def ExynosLogicExPred : MCSchedPredicate<ExynosLogicExFn>;
  96
  97 // Identify a load or store using the register offset addressing mode
  98 // with a scaled non-extended register.
  99 def ExynosScaledIdxFn   : TIIPredicate<"isExynosScaledAddr",
 100                                        MCOpcodeSwitchStatement<
 101                                          [MCOpcodeSwitchCase<
 102                                             IsLoadStoreRegOffsetOp.ValidOpcodes,
 103                                             MCReturnStatement<
 104                                               CheckAny<
 105                                                 [CheckMemExtSXTW,
 106                                                  CheckMemExtUXTW,
 107                                                  CheckMemScaled]>>>],
 108                                          MCReturnStatement<FalsePred>>>;
 109 def ExynosScaledIdxPred : MCSchedPredicate<ExynosScaledIdxFn>;
 110
 111 // Identify FP instructions.
 112 def ExynosFPPred : MCSchedPredicate<CheckFpOrNEON>;
 113
 114 // Identify 128-bit NEON instructions.
 115 def ExynosQFormPred : MCSchedPredicate<CheckQForm>;
 116
 117 // Identify instructions that reset a register efficiently.
 118 def ExynosResetFn   : TIIPredicate<
 119                         "isExynosResetFast",
 120                         MCOpcodeSwitchStatement<
 121                           [MCOpcodeSwitchCase<
 122                              [ADR, ADRP,
 123                               MOVNWi, MOVNXi,
 124                               MOVZWi, MOVZXi],
 125                              MCReturnStatement<TruePred>>,
 126                            MCOpcodeSwitchCase<
 127                              [ORRWri, ORRXri],
 128                              MCReturnStatement<CheckIsReg1Zero>>],
 129                           MCReturnStatement<
 130                             CheckAny<
 131                               [IsCopyIdiomFn,
 132                                IsZeroFPIdiomFn]>>>>;
 133 def ExynosResetPred : MCSchedPredicate<ExynosResetFn>;
 134
 135 // Identify cheap arithmetic and logic immediate instructions.
 136 def ExynosCheapFn : TIIPredicate<
 137                       "isExynosCheapAsMove",
 138                       MCOpcodeSwitchStatement<
 139                         [MCOpcodeSwitchCase<
 140                            IsArithLogicImmOp.ValidOpcodes,
 141                            MCReturnStatement<TruePred>>],
 142                         MCReturnStatement<
 143                           CheckAny<
 144                             [ExynosArithFn, ExynosResetFn, ExynosLogicFn]>>>>;