llvm/lib/Target/AArch64/AArch64SchedTSV110.td

   1 //==- AArch64SchedTSV110.td - Huawei TSV110 Scheduling Definitions -*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the machine model for Huawei TSV110 to support
  10 // instruction scheduling and other instruction cost heuristics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // ===---------------------------------------------------------------------===//
  15 // The following definitions describe the simpler per-operand machine model.
  16 // This works with MachineScheduler. See llvm/MC/MCSchedule.h for details.
  17
  18 // Huawei TSV110 scheduling machine model.
  19 def TSV110Model : SchedMachineModel {
  20   let IssueWidth            =   4; // 4 micro-ops dispatched  per cycle.
  21   let MicroOpBufferSize     = 128; // 128 micro-op re-order buffer
  22   let LoopMicroOpBufferSize =  16;
  23   let LoadLatency           =   4; // Optimistic load latency.
  24   let MispredictPenalty     =  14; // Fetch + Decode/Rename/Dispatch + Branch
  25   let CompleteModel         =   1;
  26
  27   list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
  28                                                     PAUnsupported.F,
  29                                                     SMEUnsupported.F,
  30                                                     [HasMTE, HasCSSC]);
  31 }
  32
  33 // Define each kind of processor resource and number available on the TSV110,
  34 // which has 8 pipelines, each with its own queue where micro-ops wait for
  35 // their operands and issue out-of-order to one of eight execution pipelines.
  36 let SchedModel = TSV110Model in {
  37   def TSV110UnitALU   : ProcResource<1>; // Int ALU
  38   def TSV110UnitAB    : ProcResource<2>; // Int ALU/BRU
  39   def TSV110UnitMDU   : ProcResource<1>; // Multi-Cycle
  40   def TSV110UnitFSU1  : ProcResource<1>; // FP/ASIMD
  41   def TSV110UnitFSU2  : ProcResource<1>; // FP/ASIMD
  42   def TSV110UnitLd0St : ProcResource<1>; // Load/Store
  43   def TSV110UnitLd1   : ProcResource<1>; // Load
  44
  45   def TSV110UnitLd    : ProcResGroup<[TSV110UnitLd0St, TSV110UnitLd1]>;  // Any load
  46   def TSV110UnitF     : ProcResGroup<[TSV110UnitFSU1, TSV110UnitFSU2]>;
  47   def TSV110UnitALUAB : ProcResGroup<[TSV110UnitALU, TSV110UnitAB]>;
  48 }
  49
  50 let SchedModel = TSV110Model in {
  51
  52 //===----------------------------------------------------------------------===//
  53 // Map the target-defined scheduler read/write resources and latency for TSV110
  54
  55 // Integer ALU
  56 // TODO: Use SchedVariant to select BRU for ALU ops that sets NZCV flags
  57 // (including ops that shift and/or extend):
  58 // 1cyc_1BRU: ADDS, ADCS, ANDS, BICS, SUBS, SBCS, CCMN, CCMP
  59 // 2cyc_1BRU: ADDSshfr, SUBSshfr, ANDSshfr, ADDSextr, SUBSextr
  60 def : WriteRes<WriteImm,   [TSV110UnitALUAB]> { let Latency = 1; }
  61 def : WriteRes<WriteI,     [TSV110UnitALUAB]> { let Latency = 1; }
  62 def : WriteRes<WriteISReg, [TSV110UnitMDU]>   { let Latency = 2; }
  63 def : WriteRes<WriteIEReg, [TSV110UnitMDU]>   { let Latency = 2; }
  64 def : WriteRes<WriteExtr,  [TSV110UnitALUAB]> { let Latency = 1; }
  65 def : WriteRes<WriteIS,    [TSV110UnitALUAB]> { let Latency = 1; }
  66
  67 // Integer Mul/MAC/Div
  68 def : WriteRes<WriteID32,  [TSV110UnitMDU]> { let Latency = 12;
  69                                               let ReleaseAtCycles = [12]; }
  70 def : WriteRes<WriteID64,  [TSV110UnitMDU]> { let Latency = 20;
  71                                               let ReleaseAtCycles = [20]; }
  72 def : WriteRes<WriteIM32,  [TSV110UnitMDU]> { let Latency = 3; }
  73 def : WriteRes<WriteIM64,  [TSV110UnitMDU]> { let Latency = 4; }
  74
  75 // Load
  76 def : WriteRes<WriteLD,    [TSV110UnitLd]>  { let Latency = 4; }
  77 def : WriteRes<WriteLDIdx, [TSV110UnitLd]>  { let Latency = 4; }
  78 def : WriteRes<WriteLDHi,  []> { let Latency = 4; }
  79
  80 // Pre/Post Indexing
  81 def : WriteRes<WriteAdr,   [TSV110UnitALUAB]> { let Latency = 1; }
  82
  83 // Store
  84 def : WriteRes<WriteST,    [TSV110UnitLd0St]> { let Latency = 1; }
  85 def : WriteRes<WriteSTP,   [TSV110UnitLd0St]> { let Latency = 1; }
  86 def : WriteRes<WriteSTIdx, [TSV110UnitLd0St]> { let Latency = 1; }
  87
  88 // FP
  89 def : WriteRes<WriteF,     [TSV110UnitF]> { let Latency = 2; }
  90 def : WriteRes<WriteFCmp,  [TSV110UnitF]> { let Latency = 3; }
  91 def : WriteRes<WriteFCvt,  [TSV110UnitF]> { let Latency = 3; }
  92 def : WriteRes<WriteFCopy, [TSV110UnitF]> { let Latency = 2; }
  93 def : WriteRes<WriteFImm,  [TSV110UnitF]> { let Latency = 2; }
  94 def : WriteRes<WriteFMul,  [TSV110UnitF]> { let Latency = 5; }
  95
  96 // FP Div, Sqrt
  97 def : WriteRes<WriteFDiv,  [TSV110UnitFSU1]> { let Latency = 18; let ReleaseAtCycles = [18]; }
  98
  99 def : WriteRes<WriteVd,    [TSV110UnitF]>     { let Latency = 4; }
 100 def : WriteRes<WriteVq,    [TSV110UnitF]>     { let Latency = 4; }
 101 def : WriteRes<WriteVST,   [TSV110UnitF]>     { let Latency = 1; }
 102
 103 // Branch
 104 def : WriteRes<WriteBr,    [TSV110UnitAB]> { let Latency = 1; }
 105 def : WriteRes<WriteBrReg, [TSV110UnitAB]> { let Latency = 1; }
 106 def : WriteRes<WriteSys,     []> { let Latency = 1; }
 107 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
 108 def : WriteRes<WriteHint,    []> { let Latency = 1; }
 109
 110 def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
 111
 112 // Forwarding logic is modeled only for multiply and accumulate.
 113 def : ReadAdvance<ReadI,       0>;
 114 def : ReadAdvance<ReadISReg,   0>;
 115 def : ReadAdvance<ReadIEReg,   0>;
 116 def : ReadAdvance<ReadIM,      0>;
 117 def : ReadAdvance<ReadIMA,     2, [WriteIM32, WriteIM64]>;
 118 def : ReadAdvance<ReadID,      0>;
 119 def : ReadAdvance<ReadExtrHi,  0>;
 120 def : ReadAdvance<ReadAdrBase, 0>;
 121 def : ReadAdvance<ReadVLD,     0>;
 122 def : ReadAdvance<ReadST,      0>;
 123
 124 def : InstRW<[WriteI], (instrs COPY)>;
 125
 126 // Detailed Refinements
 127 //===----------------------------------------------------------------------===//
 128
 129 // Contains all of the TSV110 specific SchedWriteRes types. The approach
 130 // below is to define a generic SchedWriteRes for every combination of
 131 // latency and microOps. The naming conventions is to use a prefix, one field
 132 // for latency, and one or more microOp count/type designators.
 133 //   Prefix: TSV110Wr
 134 //       Latency: #cyc
 135 //   MicroOp Count/Types: #(ALU|AB|MDU|FSU1|FSU2|LdSt|ALUAB|F|FLdSt)
 136 //
 137 // e.g. TSV110Wr_6cyc_1ALU_6MDU_4LdSt means the total latency is 6 and there are
 138 //      1 micro-ops to be issued down one ALU pipe, six MDU pipes and four LdSt pipes.
 139 //
 140
 141 //===----------------------------------------------------------------------===//
 142 // Define Generic 1 micro-op types
 143
 144 def TSV110Wr_1cyc_1AB    : SchedWriteRes<[TSV110UnitAB]>    { let Latency = 1; }
 145 def TSV110Wr_1cyc_1ALU   : SchedWriteRes<[TSV110UnitALU]>   { let Latency = 1; }
 146 def TSV110Wr_1cyc_1ALUAB : SchedWriteRes<[TSV110UnitALUAB]> { let Latency = 1; }
 147 def TSV110Wr_1cyc_1LdSt  : SchedWriteRes<[TSV110UnitLd0St]> { let Latency = 1; }
 148
 149 def TSV110Wr_2cyc_1AB    : SchedWriteRes<[TSV110UnitAB]>    { let Latency = 2; let ReleaseAtCycles = [2]; }
 150 def TSV110Wr_2cyc_1ALU   : SchedWriteRes<[TSV110UnitALU]>   { let Latency = 2; }
 151 def TSV110Wr_2cyc_1MDU   : SchedWriteRes<[TSV110UnitMDU]>   { let Latency = 2; }
 152 def TSV110Wr_2cyc_1FSU1  : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 2; }
 153 def TSV110Wr_2cyc_1F     : SchedWriteRes<[TSV110UnitF]>     { let Latency = 2; }
 154
 155 def TSV110Wr_3cyc_1F     : SchedWriteRes<[TSV110UnitF]>     { let Latency = 3; }
 156 def TSV110Wr_3cyc_1FSU1  : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 3; }
 157 def TSV110Wr_3cyc_1MDU   : SchedWriteRes<[TSV110UnitMDU]>   { let Latency = 3; }
 158
 159 def TSV110Wr_4cyc_1FSU1  : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 4; }
 160 def TSV110Wr_4cyc_1F     : SchedWriteRes<[TSV110UnitF]>     { let Latency = 4; }
 161 def TSV110Wr_4cyc_1LdSt  : SchedWriteRes<[TSV110UnitLd]>    { let Latency = 4; }
 162 def TSV110Wr_4cyc_1MDU   : SchedWriteRes<[TSV110UnitMDU]>   { let Latency = 4; }
 163
 164 def TSV110Wr_5cyc_1F     : SchedWriteRes<[TSV110UnitF]>     { let Latency = 5; }
 165 def TSV110Wr_5cyc_1FSU1  : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 5; }
 166 def TSV110Wr_5cyc_1FSU2  : SchedWriteRes<[TSV110UnitFSU2]>  { let Latency = 5; }
 167 def TSV110Wr_5cyc_1LdSt  : SchedWriteRes<[TSV110UnitLd]>    { let Latency = 5; }
 168
 169 def TSV110Wr_6cyc_1F     : SchedWriteRes<[TSV110UnitF]>     { let Latency = 6; }
 170
 171 def TSV110Wr_7cyc_1F     : SchedWriteRes<[TSV110UnitF]>     { let Latency = 7; }
 172
 173 def TSV110Wr_8cyc_1F     : SchedWriteRes<[TSV110UnitF]>     { let Latency = 8; }
 174
 175 def TSV110Wr_11cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 11; let ReleaseAtCycles = [11]; }
 176
 177 def TSV110Wr_12cyc_1MDU  : SchedWriteRes<[TSV110UnitMDU]>   { let Latency = 12; let ReleaseAtCycles = [12]; }
 178
 179 def TSV110Wr_17cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]>  { let Latency = 17; let ReleaseAtCycles = [17]; }
 180
 181 def TSV110Wr_18cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 18; let ReleaseAtCycles = [18]; }
 182
 183 def TSV110Wr_20cyc_1MDU  : SchedWriteRes<[TSV110UnitMDU]>   { let Latency = 20; let ReleaseAtCycles = [20]; }
 184
 185 def TSV110Wr_24cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 24; let ReleaseAtCycles = [24]; }
 186
 187 def TSV110Wr_31cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]>  { let Latency = 31; let ReleaseAtCycles = [31]; }
 188
 189 def TSV110Wr_36cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]>  { let Latency = 36; let ReleaseAtCycles = [36]; }
 190
 191 def TSV110Wr_38cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 38; let ReleaseAtCycles = [38]; }
 192
 193 def TSV110Wr_64cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]>  { let Latency = 64; let ReleaseAtCycles = [64]; }
 194
 195 //===----------------------------------------------------------------------===//
 196 // Define Generic 2 micro-op types
 197
 198 def TSV110Wr_1cyc_1LdSt_1ALUAB : SchedWriteRes<[TSV110UnitLd0St,
 199                                                 TSV110UnitALUAB]> {
 200   let Latency = 1;
 201   let NumMicroOps = 2;
 202 }
 203
 204 def TSV110Wr_2cyc_1LdSt_1ALUAB : SchedWriteRes<[TSV110UnitLd0St,
 205                                                 TSV110UnitALUAB]> {
 206   let Latency = 2;
 207   let NumMicroOps = 2;
 208 }
 209
 210 def TSV110Wr_2cyc_2LdSt        : SchedWriteRes<[TSV110UnitLd0St,
 211                                                 TSV110UnitLd0St]> {
 212   let Latency = 2;
 213   let NumMicroOps = 2;
 214 }
 215
 216 def TSV110Wr_2cyc_2F           : SchedWriteRes<[TSV110UnitF,
 217                                                 TSV110UnitF]> {
 218   let Latency = 2;
 219   let NumMicroOps = 2;
 220 }
 221
 222 def TSV110Wr_2cyc_1FSU1_1FSU2  : SchedWriteRes<[TSV110UnitFSU1,
 223                                                 TSV110UnitFSU2]> {
 224   let Latency = 2;
 225   let NumMicroOps = 2;
 226 }
 227
 228 def TSV110Wr_4cyc_2F           : SchedWriteRes<[TSV110UnitF,
 229                                                 TSV110UnitF]> {
 230   let Latency = 4;
 231   let NumMicroOps = 2;
 232 }
 233
 234 def TSV110Wr_4cyc_1FSU1_1FSU2  : SchedWriteRes<[TSV110UnitFSU1,
 235                                                 TSV110UnitFSU2]> {
 236   let Latency = 4;
 237   let NumMicroOps = 2;
 238 }
 239
 240 def TSV110Wr_4cyc_1LdSt_1ALUAB : SchedWriteRes<[TSV110UnitLd,
 241                                                 TSV110UnitALUAB]> {
 242   let Latency = 4;
 243   let NumMicroOps = 2;
 244 }
 245
 246 def TSV110Wr_5cyc_1ALU_1F      : SchedWriteRes<[TSV110UnitALU,
 247                                                 TSV110UnitF]> {
 248   let Latency     = 5;
 249   let NumMicroOps = 2;
 250 }
 251
 252 def TSV110Wr_6cyc_2LdSt        : SchedWriteRes<[TSV110UnitLd,
 253                                                 TSV110UnitLd]> {
 254   let Latency = 6;
 255   let NumMicroOps = 2;
 256 }
 257
 258 def TSV110Wr_6cyc_1LdSt_1ALUAB : SchedWriteRes<[TSV110UnitLd,
 259                                                 TSV110UnitALUAB]> {
 260   let Latency = 6;
 261   let NumMicroOps = 2;
 262 }
 263
 264 def TSV110Wr_7cyc_1F_1LdSt     : SchedWriteRes<[TSV110UnitF,
 265                                                 TSV110UnitLd]> {
 266   let Latency = 7;
 267   let NumMicroOps = 2;
 268 }
 269
 270 def TSV110Wr_8cyc_2FSU1        : SchedWriteRes<[TSV110UnitFSU1,
 271                                                 TSV110UnitFSU1]> {
 272   let Latency = 8;
 273   let NumMicroOps = 2;
 274 }
 275
 276
 277 def TSV110Wr_8cyc_1FSU1_1FSU2  : SchedWriteRes<[TSV110UnitFSU1,
 278                                                 TSV110UnitFSU2]> {
 279   let Latency = 8;
 280   let NumMicroOps = 2;
 281 }
 282
 283 //===----------------------------------------------------------------------===//
 284 // Define Generic 3 micro-op types
 285
 286 def TSV110Wr_6cyc_3F       : SchedWriteRes<[TSV110UnitF, TSV110UnitF,
 287                                             TSV110UnitF]> {
 288   let Latency     = 6;
 289   let NumMicroOps = 3;
 290 }
 291
 292 def TSV110Wr_6cyc_3LdSt    : SchedWriteRes<[TSV110UnitLd, TSV110UnitLd,
 293                                             TSV110UnitLd]> {
 294   let Latency = 6;
 295   let NumMicroOps = 3;
 296 }
 297
 298 def TSV110Wr_7cyc_2F_1LdSt : SchedWriteRes<[TSV110UnitF, TSV110UnitF,
 299                                                          TSV110UnitLd]> {
 300   let Latency = 7;
 301   let NumMicroOps = 3;
 302 }
 303
 304 //===----------------------------------------------------------------------===//
 305 // Define Generic 4 micro-op types
 306
 307 def TSV110Wr_8cyc_4F          : SchedWriteRes<[TSV110UnitF, TSV110UnitF,
 308                                                TSV110UnitF, TSV110UnitF]> {
 309   let Latency = 8;
 310   let NumMicroOps = 4;
 311 }
 312
 313 def TSV110Wr_8cyc_3F_1LdSt    : SchedWriteRes<[TSV110UnitF, TSV110UnitF,
 314                                                TSV110UnitF, TSV110UnitLd]> {
 315   let Latency = 8;
 316   let NumMicroOps = 4;
 317 }
 318
 319 //===----------------------------------------------------------------------===//
 320 // Define Generic 5 micro-op types
 321
 322 def TSV110Wr_8cyc_3F_2LdSt : SchedWriteRes<[TSV110UnitF, TSV110UnitF, TSV110UnitF,
 323                                             TSV110UnitLd, TSV110UnitLd]> {
 324   let Latency = 8;
 325   let NumMicroOps = 5;
 326 }
 327
 328 //===----------------------------------------------------------------------===//
 329 // Define Generic 8 micro-op types
 330
 331 def TSV110Wr_10cyc_4F_4LdSt : SchedWriteRes<[TSV110UnitF, TSV110UnitF,
 332                                              TSV110UnitF, TSV110UnitF,
 333                                              TSV110UnitLd, TSV110UnitLd,
 334                                              TSV110UnitLd, TSV110UnitLd]> {
 335   let Latency = 10;
 336   let NumMicroOps = 8;
 337 }
 338
 339
 340 // Branch Instructions
 341 // -----------------------------------------------------------------------------
 342
 343 def : InstRW<[TSV110Wr_1cyc_1AB], (instrs B)>;
 344 def : InstRW<[TSV110Wr_1cyc_1AB], (instrs BL)>;
 345 def : InstRW<[TSV110Wr_1cyc_1AB], (instrs BLR)>;
 346 def : InstRW<[TSV110Wr_1cyc_1AB], (instregex "^(BR|RET|(CBZ|CBNZ|TBZ|TBNZ))$")>;
 347
 348
 349 // Cryptography Extensions
 350 // -----------------------------------------------------------------------------
 351
 352 def : InstRW<[TSV110Wr_3cyc_1FSU1], (instregex "^AES[DE]")>;
 353 def : InstRW<[TSV110Wr_3cyc_1FSU1], (instregex "^AESI?MC")>;
 354 def : InstRW<[TSV110Wr_2cyc_1FSU1], (instregex "^SHA1SU1")>;
 355 def : InstRW<[TSV110Wr_2cyc_2F],    (instregex "^SHA1(H|SU0)")>;
 356 def : InstRW<[TSV110Wr_5cyc_1FSU1], (instregex "^SHA1[CMP]")>;
 357 def : InstRW<[TSV110Wr_2cyc_1FSU1], (instregex "^SHA256SU0")>;
 358 def : InstRW<[TSV110Wr_3cyc_1FSU1], (instregex "^SHA256SU1")>;
 359 def : InstRW<[TSV110Wr_5cyc_1FSU1], (instregex "^SHA256(H|H2)")>;
 360 def TSV110ReadCRC: SchedReadAdvance<1, [TSV110Wr_2cyc_1MDU]>;
 361 def : InstRW<[TSV110Wr_2cyc_1MDU, TSV110ReadCRC],  (instregex "^CRC32.*$")>;
 362
 363
 364 // Arithmetic and Logical Instructions
 365 // -----------------------------------------------------------------------------
 366
 367 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "(BIC|EON|ORN)[WX]rr")>;
 368 def : InstRW<[TSV110Wr_1cyc_1AB],    (instregex "(BIC)S[WX]rr")>;
 369
 370 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "(ADD|AND|EOR|ORR|SUB)[WX]r(r|i)")>;
 371 def : InstRW<[TSV110Wr_1cyc_1AB],    (instregex "(ADD|AND|EOR|ORR|SUB)S[WX]r(r|i)")>;
 372
 373 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(ADC|SBC|BIC)[WX]r$")>;
 374 def : InstRW<[TSV110Wr_1cyc_1AB],    (instregex "^(ADC|SBC)S[WX]r$")>;
 375
 376
 377 // Shifted Register with Shift == 0
 378 // ----------------------------------------------------------------------------
 379
 380 def TSV110WrISReg : SchedWriteVariant<[
 381        SchedVar<RegShiftedPred, [WriteISReg]>,
 382        SchedVar<NoSchedPred, [WriteI]>]>;
 383 def : InstRW<[TSV110WrISReg], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|ORR|SUB)[WX]rs$")>;
 384
 385 def TSV110WrISRegBr : SchedWriteVariant<[
 386        SchedVar<RegShiftedPred, [TSV110Wr_2cyc_1AB]>,
 387        SchedVar<NoSchedPred, [WriteBr]>]>;
 388 def : InstRW<[TSV110WrISRegBr], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|ORR|SUB)S[WX]rs$")>;
 389
 390 // Extended Register with Extend == 0
 391 // ----------------------------------------------------------------------------
 392
 393 def TSV110WrIEReg : SchedWriteVariant<[
 394        SchedVar<RegExtendedPred, [WriteISReg]>,
 395        SchedVar<NoSchedPred, [WriteI]>]>;
 396 def : InstRW<[TSV110WrIEReg], (instregex "^(ADD|SUB)[WX]r(x|x64)$")>;
 397
 398 def TSV110WrIERegBr : SchedWriteVariant<[
 399        SchedVar<RegExtendedPred, [TSV110Wr_2cyc_1AB]>,
 400        SchedVar<NoSchedPred, [WriteBr]>]>;
 401 def : InstRW<[TSV110WrIERegBr], (instregex "^(ADD|SUB)S[WX]r(x|x64)$")>;
 402
 403 def : InstRW<[TSV110Wr_1cyc_1AB],    (instregex "^(CCMN|CCMP)(W|X)(r|i)$")>;
 404 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
 405
 406
 407 // Move and Shift Instructions
 408 // -----------------------------------------------------------------------------
 409
 410 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instrs ADR, ADRP)>;
 411 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^MOV[NZK][WX]i")>;
 412 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "(LSLV|LSRV|ASRV|RORV)(W|X)r")>;
 413
 414
 415 // Divide and Multiply Instructions
 416 // -----------------------------------------------------------------------------
 417
 418 def : InstRW<[TSV110Wr_12cyc_1MDU],  (instregex "^(S|U)DIVWr$")>;
 419 def : InstRW<[TSV110Wr_20cyc_1MDU],  (instregex "^(S|U)DIVXr$")>;
 420
 421 def TSV110ReadMAW : SchedReadAdvance<2, [TSV110Wr_3cyc_1MDU]>;
 422 def : InstRW<[TSV110Wr_3cyc_1MDU, ReadIM, ReadIM, TSV110ReadMAW], (instrs MADDWrrr, MSUBWrrr)>;
 423 def TSV110ReadMAQ : SchedReadAdvance<3, [TSV110Wr_4cyc_1MDU]>;
 424 def : InstRW<[TSV110Wr_4cyc_1MDU, ReadIM, ReadIM, TSV110ReadMAQ], (instrs MADDXrrr, MSUBXrrr)>;
 425 def : InstRW<[TSV110Wr_3cyc_1MDU, ReadIM, ReadIM, TSV110ReadMAW], (instregex "(S|U)(MADDL|MSUBL)rrr")>;
 426 def : InstRW<[TSV110Wr_4cyc_1MDU], (instregex "^(S|U)MULHrr$")>;
 427
 428
 429 // Miscellaneous Data-Processing Instructions
 430 // -----------------------------------------------------------------------------
 431
 432 def : InstRW<[TSV110Wr_1cyc_1ALUAB],    (instregex "^EXTR(W|X)rri$")>;
 433 def : InstRW<[TSV110Wr_1cyc_1ALUAB],    (instregex "^(S|U)?BFM(W|X)ri$")>;
 434 def : InstRW<[TSV110Wr_1cyc_1ALUAB],    (instregex "^(CLS|CLZ|RBIT|REV(16|32)?)(W|X)r$")>;
 435
 436
 437 // Load Instructions
 438 // -----------------------------------------------------------------------------
 439
 440 def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instregex "^LDR(W|X)l$")>;
 441 def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instrs LDRSWl)>;
 442
 443 def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instregex "^LDR(BB|HH|W|X)ui$")>;
 444 def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instregex "^LDRS(BW|BX|HW|HX|W)ui$")>;
 445
 446 def : InstRW<[WriteAdr, TSV110Wr_4cyc_1LdSt],     (instregex "^LDR(BB|HH|W|X)(post|pre)$")>;
 447 def : InstRW<[WriteAdr, TSV110Wr_4cyc_1LdSt],     (instregex "^LDRS(BW|BX|HW|HX|W)(post|pre)$")>;
 448
 449 def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instregex "^LDTR(B|H|W|X)i$")>;
 450 def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instregex "^LDUR(BB|HH|W|X)i$")>;
 451 def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instregex "^LDTRS(BW|BX|HW|HX|W)i$")>;
 452 def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instregex "^LDURS(BW|BX|HW|HX|W)i$")>;
 453
 454 def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteLDHi],     (instregex "^LDNP(W|X)i$")>;
 455 def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteLDHi],     (instregex "^LDP(W|X)i$")>;
 456 def : InstRW<[WriteAdr, TSV110Wr_4cyc_1LdSt_1ALUAB, WriteLDHi],(instregex "^LDP(W|X)(post|pre)$")>;
 457
 458 def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteLDHi],           (instrs LDPSWi)>;
 459 def : InstRW<[WriteAdr, TSV110Wr_4cyc_1LdSt, WriteLDHi], (instrs LDPSWpost)>;
 460 def : InstRW<[WriteAdr, TSV110Wr_4cyc_1LdSt, WriteLDHi], (instrs LDPSWpre)>;
 461
 462 def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instrs PRFMl)>;
 463 def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instrs PRFUMi)>;
 464 def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instregex "^PRFMui$")>;
 465 def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instregex "^PRFMro(W|X)$")>;
 466
 467
 468 // Store Instructions
 469 // -----------------------------------------------------------------------------
 470
 471 def : InstRW<[TSV110Wr_1cyc_1LdSt],            (instregex "^STN?P(W|X)i$")>;
 472 def : InstRW<[WriteAdr, TSV110Wr_1cyc_1LdSt],  (instregex "^STP(W|X)(post|pre)$")>;
 473 def : InstRW<[TSV110Wr_1cyc_1LdSt],            (instregex "^STUR(BB|HH|W|X)i$")>;
 474 def : InstRW<[TSV110Wr_1cyc_1LdSt],            (instregex "^STTR(B|H|W|X)i$")>;
 475 def : InstRW<[TSV110Wr_1cyc_1LdSt],            (instregex "^STR(BB|HH|W|X)ui$")>;
 476
 477 def : InstRW<[WriteAdr, TSV110Wr_1cyc_1LdSt],  (instregex "^STR(BB|HH|W|X)(post|pre)$")>;
 478 def : InstRW<[WriteAdr, TSV110Wr_1cyc_1LdSt],  (instregex "^STR(BB|HH|W|X)ro(W|X)$")>;
 479
 480
 481 // FP Data Processing Instructions
 482 // -----------------------------------------------------------------------------
 483
 484 def : InstRW<[TSV110Wr_2cyc_1F], (instregex "F(ABS|NEG)(D|S)r")>;
 485 def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FCCMP(E)?(S|D)rr$")>;
 486 def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FCMP(E)?(S|D)r(r|i)$")>;
 487 def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FCSEL(S|D)rrr$")>;
 488
 489 def : InstRW<[TSV110Wr_11cyc_1FSU1], (instrs FDIVSrr)>;
 490 def : InstRW<[TSV110Wr_18cyc_1FSU1], (instrs FDIVDrr)>;
 491 def : InstRW<[TSV110Wr_17cyc_1FSU2], (instrs FSQRTSr)>;
 492 def : InstRW<[TSV110Wr_31cyc_1FSU2], (instrs FSQRTDr)>;
 493
 494 def : InstRW<[TSV110Wr_2cyc_1F], (instregex "^F(MAX|MIN).+rr")>;
 495
 496 def : InstRW<[TSV110Wr_4cyc_1F], (instregex "^FN?M(ADD|SUB)Hrrr")>;
 497 def : InstRW<[TSV110Wr_5cyc_1F], (instregex "^FN?M(ADD|SUB)Srrr")>;
 498 def : InstRW<[TSV110Wr_7cyc_1F], (instregex "^FN?M(ADD|SUB)Drrr")>;
 499
 500 def : InstRW<[TSV110Wr_4cyc_1F], (instregex "^F(ADD|SUB)Hrr")>;
 501 def : InstRW<[TSV110Wr_5cyc_1F], (instregex "^F(ADD|SUB)Srr")>;
 502 def : InstRW<[TSV110Wr_4cyc_1F], (instregex "^F(ADD|SUB)Drr")>;
 503
 504 def : InstRW<[TSV110Wr_4cyc_1F], (instregex "^F(N)?MULHrr$")>;
 505 def : InstRW<[TSV110Wr_5cyc_1F], (instregex "^F(N)?MULSrr$")>;
 506 def : InstRW<[TSV110Wr_5cyc_1F], (instregex "^F(N)?MULDrr$")>;
 507
 508 def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FRINT.+r")>;
 509
 510
 511 // FP Miscellaneous Instructions
 512 // -----------------------------------------------------------------------------
 513
 514 def : InstRW<[TSV110Wr_5cyc_1ALU_1F], (instregex "^[SU]CVTF[SU][WX][SD]ri")>;
 515 def : InstRW<[TSV110Wr_4cyc_1FSU1],   (instregex "^FCVT(A|M|N|P|Z)(S|U)U(W|X)(S|D)r$")>;
 516 def : InstRW<[TSV110Wr_3cyc_1F],      (instregex "^FCVT[HSD][HSD]r")>;
 517
 518 def : InstRW<[TSV110Wr_2cyc_1FSU1],   (instregex "^FMOV(DX|WS|XD|SW|DXHigh|XDHigh)r$")>;
 519 def : InstRW<[TSV110Wr_2cyc_1F],      (instregex "^FMOV[SD][ir]$")>;
 520
 521
 522 // FP Load Instructions
 523 // -----------------------------------------------------------------------------
 524
 525 def : InstRW<[TSV110Wr_5cyc_1LdSt],                      (instregex "^LDR[DSQ]l")>;
 526 def : InstRW<[TSV110Wr_5cyc_1LdSt],                      (instregex "^LDUR[BDHSQ]i")>;
 527 def : InstRW<[WriteAdr, TSV110Wr_5cyc_1LdSt],            (instregex "^LDR[BDHSQ](post|pre)")>;
 528 def : InstRW<[TSV110Wr_5cyc_1LdSt],                      (instregex "^LDR[BDHSQ]ui")>;
 529 def : InstRW<[TSV110Wr_6cyc_1LdSt_1ALUAB, ReadAdrBase],  (instregex "^LDR(Q|D|H|S|B)ro(W|X)$")>;
 530 def : InstRW<[TSV110Wr_5cyc_1LdSt, WriteLDHi],           (instregex "^LDN?P[DQS]i")>;
 531 def : InstRW<[WriteAdr, TSV110Wr_5cyc_1LdSt, WriteLDHi], (instregex "^LDP[DQS](post|pre)")>;
 532
 533
 534 // FP Store Instructions
 535 // -----------------------------------------------------------------------------
 536
 537 def : InstRW<[TSV110Wr_1cyc_1LdSt],                     (instregex "^STUR[BHSDQ]i")>;
 538 def : InstRW<[TSV110Wr_1cyc_1LdSt_1ALUAB, ReadAdrBase], (instregex "^STR[BHSDQ](post|pre)")>;
 539 def : InstRW<[TSV110Wr_1cyc_1LdSt],                     (instregex "^STR[BHSDQ]ui")>;
 540 def : InstRW<[TSV110Wr_2cyc_1LdSt_1ALUAB, ReadAdrBase], (instregex "^STR[BHSDQ]ro[WX]")>;
 541 def : InstRW<[TSV110Wr_2cyc_2LdSt],                     (instregex "^STN?P[SDQ]i")>;
 542 def : InstRW<[WriteAdr, TSV110Wr_2cyc_2LdSt],           (instregex "^STP[SDQ](post|pre)")>;
 543
 544
 545 // ASIMD Integer Instructions
 546 // -----------------------------------------------------------------------------
 547
 548 // Reference for forms in this group
 549 //   D form - v8i8, v4i16, v2i32
 550 //   Q form - v16i8, v8i16, v4i32
 551 //   D form - v1i8, v1i16, v1i32, v1i64
 552 //   Q form - v16i8, v8i16, v4i32, v2i64
 553 //   D form - v8i8_v8i16, v4i16_v4i32, v2i32_v2i64
 554 //   Q form - v16i8_v8i16, v8i16_v4i32, v4i32_v2i64
 555
 556 // ASIMD simple arithmetic
 557 def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(ABS|ADD(P)?|NEG|SUB)v")>;
 558 def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^[SU](ADD(L|LP|W)|SUB(L|W))v")>;
 559
 560 // ASIMD complex arithmetic
 561 def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]H(ADD|SUB)v")>;
 562 def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^R?(ADD|SUB)HN2?v")>;
 563 def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]Q(ADD|SUB)v")>;
 564 def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^(SU|US)QADDv")>;
 565 def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]RHADDv")>;
 566 def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]ABAL?v")>;
 567 def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]ABDL?v")>;
 568 def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]ADALPv")>;
 569 def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^((SQ)(ABS|NEG))v")>;
 570
 571 // ASIMD compare
 572 def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT|TST)v")>;
 573
 574 // ASIMD max/min
 575 def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^[SU](MIN|MAX)P?v")>;
 576
 577 // ASIMD logical
 578 def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(AND|BIC|BIF|BIT|BSL|EOR|MVN|NOT|ORN|ORR)v")>;
 579
 580 // ASIMD multiply accumulate, D-form
 581 def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^(MUL|ML[AS]|SQR?D(MULH))(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)")>;
 582 // ASIMD multiply accumulate, Q-form
 583 def : InstRW<[TSV110Wr_8cyc_2FSU1], (instregex "^(MUL|ML[AS]|SQR?D(MULH))(v16i8|v8i16|v4i32)")>;
 584
 585 // ASIMD multiply accumulate long
 586 def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "(S|U|SQD)(MLAL|MLSL|MULL)v.*")>;
 587 def : InstRW<[TSV110Wr_2cyc_1FSU1], (instregex "^PMULL(v8i8|v16i8)")>;
 588 def : InstRW<[TSV110Wr_2cyc_1FSU1], (instregex "^PMULL(v1i64|v2i64)")>;
 589
 590 // ASIMD shift
 591 // ASIMD shift accumulate
 592 def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^(S|SR|U|UR)SRA")>;
 593 // ASIMD shift by immed, basic
 594 def : InstRW<[TSV110Wr_4cyc_1FSU1],
 595             (instregex "SHLv","SLIv","SRIv","SHRNv","SQXTNv","SQXTUNv","UQXTNv")>;
 596 // ASIMD shift by immed, complex
 597 def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^[SU]?(Q|R){1,2}SHR")>;
 598 def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^SQSHLU")>;
 599 // ASIMD shift by register, basic, Q-form
 600 def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^[SU]SHL(v16i8|v8i16|v4i32|v2i64)")>;
 601 // ASIMD shift by register, complex, D-form
 602 def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
 603 // ASIMD shift by register, complex, Q-form
 604 def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^[SU][QR]{1,2}SHL(v16i8|v8i16|v4i32|v2i64)")>;
 605
 606 // ASIMD reduction
 607 // ASIMD arith, reduce, 4H/4S
 608 def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>;
 609 // ASIMD arith, reduce, 8B/8H
 610 def : InstRW<[TSV110Wr_8cyc_1FSU1_1FSU2], (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>;
 611 // ASIMD arith, reduce, 16B
 612 def : InstRW<[TSV110Wr_8cyc_1FSU1_1FSU2], (instregex "^[SU]?ADDL?Vv16i8v$")>;
 613
 614 // ASIMD max/min, reduce, 4H/4S
 615 def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU](MIN|MAX)V(v4i16|v4i32)v$")>;
 616 // ASIMD max/min, reduce, 8B/8H
 617 def : InstRW<[TSV110Wr_8cyc_1FSU1_1FSU2], (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>;
 618 // ASIMD max/min, reduce, 16B
 619 def : InstRW<[TSV110Wr_8cyc_1FSU1_1FSU2], (instregex "^[SU](MIN|MAX)Vv16i8v$")>;
 620
 621
 622 // Vector - Floating Point
 623 // -----------------------------------------------------------------------------
 624
 625 // Reference for forms in this group
 626 //   D form - v2f32
 627 //   Q form - v4f32, v2f64
 628 //   D form - 32, 64
 629 //   D form - v1i32, v1i64
 630 //   D form - v2i32
 631 //   Q form - v4i32, v2i64
 632
 633 // ASIMD FP sign manipulation
 634 def : InstRW<[TSV110Wr_2cyc_1F],  (instregex "^FABSv")>;
 635 def : InstRW<[TSV110Wr_2cyc_1F],  (instregex "^FNEGv")>;
 636
 637 // ASIMD FP compare
 638 def : InstRW<[TSV110Wr_2cyc_1F],  (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v")>;
 639
 640 // ASIMD FP convert
 641 def : InstRW<[TSV110Wr_2cyc_1F],  (instregex "^FCVT[AMNPZ][SU]v")>;
 642 def : InstRW<[TSV110Wr_3cyc_1F],  (instregex "^FCVT(L)v")>;
 643 def : InstRW<[TSV110Wr_5cyc_1F],  (instregex "^FCVT(N|XN)v")>;
 644
 645 // ASIMD FP divide, D-form, F32
 646 def : InstRW<[TSV110Wr_11cyc_1FSU1], (instregex "FDIVv2f32")>;
 647 // ASIMD FP divide, Q-form, F32
 648 def : InstRW<[TSV110Wr_24cyc_1FSU1], (instregex "FDIVv4f32")>;
 649 // ASIMD FP divide, Q-form, F64
 650 def : InstRW<[TSV110Wr_38cyc_1FSU1], (instregex "FDIVv2f64")>;
 651
 652 // ASIMD FP SQRT
 653 def : InstRW<[TSV110Wr_17cyc_1FSU2], (instrs FSQRTv2f32)>;
 654 def : InstRW<[TSV110Wr_36cyc_1FSU2], (instrs FSQRTv4f32)>;
 655 def : InstRW<[TSV110Wr_64cyc_1FSU2], (instrs FSQRTv2f64)>;
 656
 657 // ASIMD FP max,min
 658 def : InstRW<[TSV110Wr_2cyc_1F],  (instregex "^F(MAX|MIN)(NM)?v")>;
 659 def : InstRW<[TSV110Wr_2cyc_1F],  (instregex "^F(MAX|MIN)(NM)?Pv")>;
 660 def : InstRW<[TSV110Wr_4cyc_1F],  (instregex "^F(MAX|MIN)(NM)?Vv")>;
 661
 662 // ASIMD FP add
 663 def : InstRW<[TSV110Wr_5cyc_1F],  (instregex "^F(ADD|ADDP|SUB)v")>;
 664
 665 // ASIMD FP multiply
 666 def : InstRW<[TSV110Wr_5cyc_1F],  (instregex "^FMULX?v")>;
 667
 668
 669 // ASIMD Miscellaneous Instructions
 670 // -----------------------------------------------------------------------------
 671
 672 def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(CLS|CLZ|CNT)v")>;
 673 def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(DUP|INS)v.+lane")>;
 674 def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^REV(16|32|64)v")>;
 675 def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(UZP|ZIP)[12]v")>;
 676
 677 def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^EXTv")>;
 678 def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^XTNv")>;
 679 def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^RBITv")>;
 680
 681 def : InstRW<[TSV110Wr_4cyc_1F], (instregex "^(INS|DUP)v.+gpr")>;
 682
 683 def : InstRW<[TSV110Wr_3cyc_1FSU1], (instregex "^[SU]MOVv")>;
 684
 685 // ASIMD table lookup, D-form
 686 def : InstRW<[TSV110Wr_2cyc_1F], (instregex "^TB[LX]v8i8One")>;
 687 def : InstRW<[TSV110Wr_4cyc_2F], (instregex "^TB[LX]v8i8Two")>;
 688 def : InstRW<[TSV110Wr_6cyc_3F], (instregex "^TB[LX]v8i8Three")>;
 689 def : InstRW<[TSV110Wr_8cyc_4F], (instregex "^TB[LX]v8i8Four")>;
 690 // ASIMD table lookup, Q-form
 691 def : InstRW<[TSV110Wr_2cyc_1F], (instregex "^TB[LX]v16i8One")>;
 692 def : InstRW<[TSV110Wr_4cyc_2F], (instregex "^TB[LX]v16i8Two")>;
 693 def : InstRW<[TSV110Wr_6cyc_3F], (instregex "^TB[LX]v16i8Three")>;
 694 def : InstRW<[TSV110Wr_8cyc_4F], (instregex "^TB[LX]v16i8Four")>;
 695
 696 def : InstRW<[TSV110Wr_2cyc_1F], (instregex "^FMOVv")>;
 697
 698 def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FRINT[AIMNPXZ]v")>;
 699 def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^[SU]CVTFv")>;
 700 def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^[FU](RECP|RSQRT)(E|X)v")>;
 701
 702
 703 // ASIMD Load Instructions
 704 // -----------------------------------------------------------------------------
 705
 706 def : InstRW<[TSV110Wr_7cyc_1F_1LdSt],            (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 707 def : InstRW<[WriteAdr, TSV110Wr_7cyc_1F_1LdSt],  (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 708 def : InstRW<[TSV110Wr_7cyc_2F_1LdSt],            (instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 709 def : InstRW<[WriteAdr, TSV110Wr_7cyc_2F_1LdSt],  (instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 710 def : InstRW<[TSV110Wr_8cyc_3F_1LdSt],            (instregex "^LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 711 def : InstRW<[WriteAdr, TSV110Wr_8cyc_3F_1LdSt],  (instregex "^LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 712 def : InstRW<[TSV110Wr_8cyc_3F_2LdSt],            (instregex "^LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 713 def : InstRW<[WriteAdr, TSV110Wr_8cyc_3F_2LdSt],  (instregex "^LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 714
 715 def  : InstRW<[TSV110Wr_7cyc_1F_1LdSt],           (instregex "LD1i(8|16|32|64)$")>;
 716 def  : InstRW<[WriteAdr, TSV110Wr_7cyc_1F_1LdSt], (instregex "LD1i(8|16|32|64)_POST$")>;
 717 def  : InstRW<[TSV110Wr_7cyc_2F_1LdSt],           (instregex "LD2i(8|16|32|64)$")>;
 718 def  : InstRW<[WriteAdr, TSV110Wr_7cyc_2F_1LdSt], (instregex "LD2i(8|16|32|64)_POST$")>;
 719 def  : InstRW<[TSV110Wr_8cyc_3F_1LdSt],           (instregex "LD3i(8|16|32|64)$")>;
 720 def  : InstRW<[WriteAdr, TSV110Wr_8cyc_3F_1LdSt], (instregex "LD3i(8|16|32|64)_POST$")>;
 721 def  : InstRW<[TSV110Wr_8cyc_3F_2LdSt],           (instregex "LD4i(8|16|32|64)$")>;
 722 def  : InstRW<[WriteAdr, TSV110Wr_8cyc_3F_2LdSt], (instregex "LD4i(8|16|32|64)_POST$")>;
 723
 724 def : InstRW<[TSV110Wr_5cyc_1LdSt],               (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 725 def : InstRW<[WriteAdr, TSV110Wr_5cyc_1LdSt],     (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 726 def : InstRW<[TSV110Wr_5cyc_1LdSt],               (instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 727 def : InstRW<[WriteAdr, TSV110Wr_5cyc_1LdSt],     (instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 728 def : InstRW<[TSV110Wr_6cyc_3LdSt],               (instregex "^LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 729 def : InstRW<[WriteAdr, TSV110Wr_6cyc_3LdSt],     (instregex "^LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 730 def : InstRW<[TSV110Wr_6cyc_2LdSt],               (instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 731 def : InstRW<[WriteAdr, TSV110Wr_6cyc_2LdSt],     (instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 732
 733 def : InstRW<[TSV110Wr_7cyc_2F_1LdSt],            (instregex "^LD2Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 734 def : InstRW<[WriteAdr, TSV110Wr_7cyc_2F_1LdSt],  (instregex "^LD2Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 735
 736 def : InstRW<[TSV110Wr_8cyc_3F_1LdSt],            (instregex "^LD3Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 737 def : InstRW<[WriteAdr, TSV110Wr_8cyc_3F_1LdSt],  (instregex "^LD3Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 738
 739 def : InstRW<[TSV110Wr_10cyc_4F_4LdSt],           (instregex "^LD4Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 740 def : InstRW<[WriteAdr, TSV110Wr_10cyc_4F_4LdSt], (instregex "^LD4Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 741
 742
 743 // ASIMD Store Instructions
 744 // -----------------------------------------------------------------------------
 745
 746 def  : InstRW<[TSV110Wr_3cyc_1F],             (instregex "ST1i(8|16|32|64)$")>;
 747 def  : InstRW<[WriteAdr, TSV110Wr_3cyc_1F],   (instregex "ST1i(8|16|32|64)_POST$")>;
 748 def  : InstRW<[TSV110Wr_4cyc_1F],             (instregex "ST2i(8|16|32|64)$")>;
 749 def  : InstRW<[WriteAdr, TSV110Wr_4cyc_1F],   (instregex "ST2i(8|16|32|64)_POST$")>;
 750 def  : InstRW<[TSV110Wr_5cyc_1F],             (instregex "ST3i(8|16|32|64)$")>;
 751 def  : InstRW<[WriteAdr, TSV110Wr_5cyc_1F],   (instregex "ST3i(8|16|32|64)_POST$")>;
 752 def  : InstRW<[TSV110Wr_6cyc_1F],             (instregex "ST4i(8|16|32|64)$")>;
 753 def  : InstRW<[WriteAdr, TSV110Wr_6cyc_1F],   (instregex "ST4i(8|16|32|64)_POST$")>;
 754
 755 def : InstRW<[TSV110Wr_3cyc_1F],              (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 756 def : InstRW<[WriteAdr, TSV110Wr_3cyc_1F],    (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 757 def : InstRW<[TSV110Wr_4cyc_1F],              (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 758 def : InstRW<[WriteAdr, TSV110Wr_4cyc_1F],    (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 759 def : InstRW<[TSV110Wr_5cyc_1F],              (instregex "^ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 760 def : InstRW<[WriteAdr, TSV110Wr_5cyc_1F],    (instregex "^ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 761 def : InstRW<[TSV110Wr_6cyc_1F],              (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 762 def : InstRW<[WriteAdr, TSV110Wr_6cyc_1F],    (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 763
 764 def : InstRW<[TSV110Wr_4cyc_1F],              (instregex "^ST2Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 765 def : InstRW<[WriteAdr, TSV110Wr_4cyc_1F],    (instregex "^ST2Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 766
 767 def : InstRW<[TSV110Wr_5cyc_1F],              (instregex "^ST3Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 768 def : InstRW<[WriteAdr, TSV110Wr_5cyc_1F],    (instregex "^ST3Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 769
 770 def : InstRW<[TSV110Wr_8cyc_1F],              (instregex "^ST4Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 771 def : InstRW<[WriteAdr, TSV110Wr_8cyc_1F],    (instregex "^ST4Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 772
 773 } // SchedModel = TSV110Model