clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
   2 // REQUIRES: aarch64-registered-target
   3 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1\
   4 // RUN:   -S -Werror -emit-llvm -disable-O0-optnone -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
   5 // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2p1\
   6 // RUN:   -S -Werror -emit-llvm -disable-O0-optnone -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
   7 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1\
   8 // RUN:   -S -Werror -emit-llvm -disable-O0-optnone -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
   9 // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2p1\
  10 // RUN:   -S -Werror -emit-llvm -disable-O0-optnone -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
  11 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1\
  12 // RUN:   -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
  13
  14
  15 #include <arm_sve.h>
  16
  17 #ifdef SVE_OVERLOADED_FORMS
  18 // A simple used,unused... macro, long enough to represent any SVE builtin.
  19 #define SVE_ACLE_FUNC(A1, A2_UNUSED, A3) A1##A3
  20 #else
  21 #define SVE_ACLE_FUNC(A1, A2, A3) A1##A2##A3
  22 #endif
  23
  24 // _m
  25
  26 // CHECK-LABEL: define dso_local <vscale x 8 x i16> @test_svpmov_lane_u16_m
  27 // CHECK-SAME: (<vscale x 8 x i16> [[ZN:%.*]], <vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0:[0-9]+]] {
  28 // CHECK-NEXT:  entry:
  29 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PN]])
  30 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16(<vscale x 8 x i16> [[ZN]], <vscale x 8 x i1> [[TMP0]], i32 1)
  31 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
  32 //
  33 // CPP-CHECK-LABEL: define dso_local <vscale x 8 x i16> @_Z22test_svpmov_lane_u16_mu12__SVUint16_tu10__SVBool_t
  34 // CPP-CHECK-SAME: (<vscale x 8 x i16> [[ZN:%.*]], <vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0:[0-9]+]] {
  35 // CPP-CHECK-NEXT:  entry:
  36 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PN]])
  37 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16(<vscale x 8 x i16> [[ZN]], <vscale x 8 x i1> [[TMP0]], i32 1)
  38 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
  39 //
  40 svuint16_t test_svpmov_lane_u16_m(svuint16_t zn, svbool_t pn) {
  41   return SVE_ACLE_FUNC(svpmov_lane, _u16, _m)(zn, pn, 1);
  42 }
  43
  44 // CHECK-LABEL: define dso_local <vscale x 8 x i16> @test_svpmov_lane_s16_m
  45 // CHECK-SAME: (<vscale x 8 x i16> [[ZN:%.*]], <vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0]] {
  46 // CHECK-NEXT:  entry:
  47 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PN]])
  48 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16(<vscale x 8 x i16> [[ZN]], <vscale x 8 x i1> [[TMP0]], i32 1)
  49 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
  50 //
  51 // CPP-CHECK-LABEL: define dso_local <vscale x 8 x i16> @_Z22test_svpmov_lane_s16_mu11__SVInt16_tu10__SVBool_t
  52 // CPP-CHECK-SAME: (<vscale x 8 x i16> [[ZN:%.*]], <vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0]] {
  53 // CPP-CHECK-NEXT:  entry:
  54 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PN]])
  55 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16(<vscale x 8 x i16> [[ZN]], <vscale x 8 x i1> [[TMP0]], i32 1)
  56 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
  57 //
  58 svint16_t test_svpmov_lane_s16_m(svint16_t zn, svbool_t pn) {
  59   return SVE_ACLE_FUNC(svpmov_lane, _s16, _m)(zn, pn, 1);
  60 }
  61
  62 // CHECK-LABEL: define dso_local <vscale x 4 x i32> @test_svpmov_lane_u32_m
  63 // CHECK-SAME: (<vscale x 4 x i32> [[ZN:%.*]], <vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0]] {
  64 // CHECK-NEXT:  entry:
  65 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PN]])
  66 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32(<vscale x 4 x i32> [[ZN]], <vscale x 4 x i1> [[TMP0]], i32 1)
  67 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
  68 //
  69 // CPP-CHECK-LABEL: define dso_local <vscale x 4 x i32> @_Z22test_svpmov_lane_u32_mu12__SVUint32_tu10__SVBool_t
  70 // CPP-CHECK-SAME: (<vscale x 4 x i32> [[ZN:%.*]], <vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0]] {
  71 // CPP-CHECK-NEXT:  entry:
  72 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PN]])
  73 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32(<vscale x 4 x i32> [[ZN]], <vscale x 4 x i1> [[TMP0]], i32 1)
  74 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
  75 //
  76 svuint32_t test_svpmov_lane_u32_m(svuint32_t zn, svbool_t pn) {
  77   return SVE_ACLE_FUNC(svpmov_lane, _u32, _m)(zn, pn, 1);
  78 }
  79
  80 // CHECK-LABEL: define dso_local <vscale x 4 x i32> @test_svpmov_lane_s32_m
  81 // CHECK-SAME: (<vscale x 4 x i32> [[ZN:%.*]], <vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0]] {
  82 // CHECK-NEXT:  entry:
  83 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PN]])
  84 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32(<vscale x 4 x i32> [[ZN]], <vscale x 4 x i1> [[TMP0]], i32 3)
  85 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
  86 //
  87 // CPP-CHECK-LABEL: define dso_local <vscale x 4 x i32> @_Z22test_svpmov_lane_s32_mu11__SVInt32_tu10__SVBool_t
  88 // CPP-CHECK-SAME: (<vscale x 4 x i32> [[ZN:%.*]], <vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0]] {
  89 // CPP-CHECK-NEXT:  entry:
  90 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PN]])
  91 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32(<vscale x 4 x i32> [[ZN]], <vscale x 4 x i1> [[TMP0]], i32 3)
  92 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
  93 //
  94 svint32_t test_svpmov_lane_s32_m(svint32_t zn, svbool_t pn) {
  95   return SVE_ACLE_FUNC(svpmov_lane, _s32, _m)(zn, pn, 3);
  96 }
  97
  98 // CHECK-LABEL: define dso_local <vscale x 2 x i64> @test_svpmov_lane_u64_m
  99 // CHECK-SAME: (<vscale x 2 x i64> [[ZN:%.*]], <vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0]] {
 100 // CHECK-NEXT:  entry:
 101 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PN]])
 102 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64(<vscale x 2 x i64> [[ZN]], <vscale x 2 x i1> [[TMP0]], i32 1)
 103 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 104 //
 105 // CPP-CHECK-LABEL: define dso_local <vscale x 2 x i64> @_Z22test_svpmov_lane_u64_mu12__SVUint64_tu10__SVBool_t
 106 // CPP-CHECK-SAME: (<vscale x 2 x i64> [[ZN:%.*]], <vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0]] {
 107 // CPP-CHECK-NEXT:  entry:
 108 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PN]])
 109 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64(<vscale x 2 x i64> [[ZN]], <vscale x 2 x i1> [[TMP0]], i32 1)
 110 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 111 //
 112 svuint64_t test_svpmov_lane_u64_m(svuint64_t zn, svbool_t pn) {
 113   return SVE_ACLE_FUNC(svpmov_lane, _u64, _m)(zn, pn, 1);
 114 }
 115
 116 // CHECK-LABEL: define dso_local <vscale x 2 x i64> @test_svpmov_lane_s64_m
 117 // CHECK-SAME: (<vscale x 2 x i64> [[ZN:%.*]], <vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0]] {
 118 // CHECK-NEXT:  entry:
 119 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PN]])
 120 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64(<vscale x 2 x i64> [[ZN]], <vscale x 2 x i1> [[TMP0]], i32 7)
 121 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 122 //
 123 // CPP-CHECK-LABEL: define dso_local <vscale x 2 x i64> @_Z22test_svpmov_lane_s64_mu11__SVInt64_tu10__SVBool_t
 124 // CPP-CHECK-SAME: (<vscale x 2 x i64> [[ZN:%.*]], <vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0]] {
 125 // CPP-CHECK-NEXT:  entry:
 126 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PN]])
 127 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64(<vscale x 2 x i64> [[ZN]], <vscale x 2 x i1> [[TMP0]], i32 7)
 128 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 129 //
 130 svint64_t test_svpmov_lane_s64_m(svint64_t zn, svbool_t pn) {
 131   return SVE_ACLE_FUNC(svpmov_lane, _s64, _m)(zn, pn, 7);
 132 }
 133
 134
 135 // _z
 136
 137 // CHECK-LABEL: define dso_local <vscale x 16 x i8> @test_svpmov_lane_u8_z
 138 // CHECK-SAME: (<vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0]] {
 139 // CHECK-NEXT:  entry:
 140 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8(<vscale x 16 x i1> [[PN]])
 141 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 142 //
 143 // CPP-CHECK-LABEL: define dso_local <vscale x 16 x i8> @_Z21test_svpmov_lane_u8_zu10__SVBool_t
 144 // CPP-CHECK-SAME: (<vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0]] {
 145 // CPP-CHECK-NEXT:  entry:
 146 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8(<vscale x 16 x i1> [[PN]])
 147 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 148 //
 149 svuint8_t test_svpmov_lane_u8_z(svbool_t pn) {
 150   return SVE_ACLE_FUNC(svpmov_u8, , _z)(pn);
 151 }
 152
 153 // CHECK-LABEL: define dso_local <vscale x 16 x i8> @test_svpmov_lane_s8_z
 154 // CHECK-SAME: (<vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0]] {
 155 // CHECK-NEXT:  entry:
 156 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8(<vscale x 16 x i1> [[PN]])
 157 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 158 //
 159 // CPP-CHECK-LABEL: define dso_local <vscale x 16 x i8> @_Z21test_svpmov_lane_s8_zu10__SVBool_t
 160 // CPP-CHECK-SAME: (<vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0]] {
 161 // CPP-CHECK-NEXT:  entry:
 162 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8(<vscale x 16 x i1> [[PN]])
 163 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 164 //
 165 svint8_t test_svpmov_lane_s8_z(svbool_t pn) {
 166   return SVE_ACLE_FUNC(svpmov_s8, , _z)(pn);
 167 }
 168
 169 // CHECK-LABEL: define dso_local <vscale x 8 x i16> @test_svpmov_lane_u16_z
 170 // CHECK-SAME: (<vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0]] {
 171 // CHECK-NEXT:  entry:
 172 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PN]])
 173 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16(<vscale x 8 x i1> [[TMP0]])
 174 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 175 //
 176 // CPP-CHECK-LABEL: define dso_local <vscale x 8 x i16> @_Z22test_svpmov_lane_u16_zu10__SVBool_t
 177 // CPP-CHECK-SAME: (<vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0]] {
 178 // CPP-CHECK-NEXT:  entry:
 179 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PN]])
 180 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16(<vscale x 8 x i1> [[TMP0]])
 181 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 182 //
 183 svuint16_t test_svpmov_lane_u16_z(svbool_t pn) {
 184   return SVE_ACLE_FUNC(svpmov_u16, , _z)(pn);
 185 }
 186
 187 // CHECK-LABEL: define dso_local <vscale x 8 x i16> @test_svpmov_lane_s16_z
 188 // CHECK-SAME: (<vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0]] {
 189 // CHECK-NEXT:  entry:
 190 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PN]])
 191 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16(<vscale x 8 x i1> [[TMP0]])
 192 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 193 //
 194 // CPP-CHECK-LABEL: define dso_local <vscale x 8 x i16> @_Z22test_svpmov_lane_s16_zu10__SVBool_t
 195 // CPP-CHECK-SAME: (<vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0]] {
 196 // CPP-CHECK-NEXT:  entry:
 197 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PN]])
 198 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16(<vscale x 8 x i1> [[TMP0]])
 199 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 200 //
 201 svint16_t test_svpmov_lane_s16_z(svbool_t pn) {
 202   return SVE_ACLE_FUNC(svpmov_s16, , _z)(pn);
 203 }
 204
 205 // CHECK-LABEL: define dso_local <vscale x 4 x i32> @test_svpmov_lane_u32_z
 206 // CHECK-SAME: (<vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0]] {
 207 // CHECK-NEXT:  entry:
 208 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PN]])
 209 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32(<vscale x 4 x i1> [[TMP0]])
 210 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 211 //
 212 // CPP-CHECK-LABEL: define dso_local <vscale x 4 x i32> @_Z22test_svpmov_lane_u32_zu10__SVBool_t
 213 // CPP-CHECK-SAME: (<vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0]] {
 214 // CPP-CHECK-NEXT:  entry:
 215 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PN]])
 216 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32(<vscale x 4 x i1> [[TMP0]])
 217 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 218 //
 219 svuint32_t test_svpmov_lane_u32_z(svbool_t pn) {
 220   return SVE_ACLE_FUNC(svpmov_u32, , _z)(pn);
 221 }
 222
 223 // CHECK-LABEL: define dso_local <vscale x 4 x i32> @test_svpmov_lane_s32_z
 224 // CHECK-SAME: (<vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0]] {
 225 // CHECK-NEXT:  entry:
 226 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PN]])
 227 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32(<vscale x 4 x i1> [[TMP0]])
 228 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 229 //
 230 // CPP-CHECK-LABEL: define dso_local <vscale x 4 x i32> @_Z22test_svpmov_lane_s32_zu10__SVBool_t
 231 // CPP-CHECK-SAME: (<vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0]] {
 232 // CPP-CHECK-NEXT:  entry:
 233 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PN]])
 234 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32(<vscale x 4 x i1> [[TMP0]])
 235 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 236 //
 237 svint32_t test_svpmov_lane_s32_z(svbool_t pn) {
 238   return SVE_ACLE_FUNC(svpmov_s32, , _z)(pn);
 239 }
 240
 241 // CHECK-LABEL: define dso_local <vscale x 2 x i64> @test_svpmov_lane_u64_z
 242 // CHECK-SAME: (<vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0]] {
 243 // CHECK-NEXT:  entry:
 244 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PN]])
 245 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv2i64(<vscale x 2 x i1> [[TMP0]])
 246 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 247 //
 248 // CPP-CHECK-LABEL: define dso_local <vscale x 2 x i64> @_Z22test_svpmov_lane_u64_zu10__SVBool_t
 249 // CPP-CHECK-SAME: (<vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0]] {
 250 // CPP-CHECK-NEXT:  entry:
 251 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PN]])
 252 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv2i64(<vscale x 2 x i1> [[TMP0]])
 253 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 254 //
 255 svuint64_t test_svpmov_lane_u64_z(svbool_t pn) {
 256   return SVE_ACLE_FUNC(svpmov_u64, , _z)(pn);
 257 }
 258
 259 // CHECK-LABEL: define dso_local <vscale x 2 x i64> @test_svpmov_lane_s64_z
 260 // CHECK-SAME: (<vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0]] {
 261 // CHECK-NEXT:  entry:
 262 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PN]])
 263 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv2i64(<vscale x 2 x i1> [[TMP0]])
 264 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 265 //
 266 // CPP-CHECK-LABEL: define dso_local <vscale x 2 x i64> @_Z22test_svpmov_lane_s64_zu10__SVBool_t
 267 // CPP-CHECK-SAME: (<vscale x 16 x i1> [[PN:%.*]]) #[[ATTR0]] {
 268 // CPP-CHECK-NEXT:  entry:
 269 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PN]])
 270 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv2i64(<vscale x 2 x i1> [[TMP0]])
 271 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 272 //
 273 svint64_t test_svpmov_lane_s64_z(svbool_t pn) {
 274   return SVE_ACLE_FUNC(svpmov_s64, , _z)(pn);
 275 }
 276