| blob | 8a787ee578990ef0ca7d18c662efd5fd7ffba29d |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs < %s \
3 ; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
4 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs < %s \
5 ; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
6 ; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs < %s \
7 ; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=CHECKIZHINX,RV32IZHINX %s
8 ; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs < %s \
9 ; RUN: -target-abi=lp64 | FileCheck -check-prefixes=CHECKIZHINX,RV64IZHINX %s
10 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs < %s \
11 ; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIZFHMIN,RV32IZFHMIN %s
12 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs < %s \
13 ; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECKIZFHMIN,RV64IZFHMIN %s
14 ; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs < %s \
15 ; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=CHECKIZHINXMIN,RV32IZHINXMIN %s
16 ; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs < %s \
17 ; RUN: -target-abi=lp64 | FileCheck -check-prefixes=CHECKIZHINXMIN,RV64IZHINXMIN %s
19 define signext i8 @test_floor_si8(half %x) {
20 ; RV32IZFH-LABEL: test_floor_si8:
21 ; RV32IZFH: # %bb.0:
22 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rdn
23 ; RV32IZFH-NEXT: ret
24 ;
25 ; RV64IZFH-LABEL: test_floor_si8:
26 ; RV64IZFH: # %bb.0:
27 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rdn
28 ; RV64IZFH-NEXT: ret
29 ;
30 ; RV32IZHINX-LABEL: test_floor_si8:
31 ; RV32IZHINX: # %bb.0:
32 ; RV32IZHINX-NEXT: li a1, 25
33 ; RV32IZHINX-NEXT: slli a1, a1, 10
34 ; RV32IZHINX-NEXT: fabs.h a2, a0
35 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
36 ; RV32IZHINX-NEXT: beqz a1, .LBB0_2
37 ; RV32IZHINX-NEXT: # %bb.1:
38 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rdn
39 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rdn
40 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
41 ; RV32IZHINX-NEXT: .LBB0_2:
42 ; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
43 ; RV32IZHINX-NEXT: ret
44 ;
45 ; RV64IZHINX-LABEL: test_floor_si8:
46 ; RV64IZHINX: # %bb.0:
47 ; RV64IZHINX-NEXT: li a1, 25
48 ; RV64IZHINX-NEXT: slli a1, a1, 10
49 ; RV64IZHINX-NEXT: fabs.h a2, a0
50 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
51 ; RV64IZHINX-NEXT: beqz a1, .LBB0_2
52 ; RV64IZHINX-NEXT: # %bb.1:
53 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rdn
54 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rdn
55 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
56 ; RV64IZHINX-NEXT: .LBB0_2:
57 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
58 ; RV64IZHINX-NEXT: ret
59 ;
60 ; RV32IZFHMIN-LABEL: test_floor_si8:
61 ; RV32IZFHMIN: # %bb.0:
62 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
63 ; RV32IZFHMIN-NEXT: lui a0, 307200
64 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
65 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
66 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
67 ; RV32IZFHMIN-NEXT: beqz a0, .LBB0_2
68 ; RV32IZFHMIN-NEXT: # %bb.1:
69 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
70 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
71 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
72 ; RV32IZFHMIN-NEXT: .LBB0_2:
73 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
74 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
75 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
76 ; RV32IZFHMIN-NEXT: ret
77 ;
78 ; RV64IZFHMIN-LABEL: test_floor_si8:
79 ; RV64IZFHMIN: # %bb.0:
80 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
81 ; RV64IZFHMIN-NEXT: lui a0, 307200
82 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
83 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
84 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
85 ; RV64IZFHMIN-NEXT: beqz a0, .LBB0_2
86 ; RV64IZFHMIN-NEXT: # %bb.1:
87 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
88 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
89 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
90 ; RV64IZFHMIN-NEXT: .LBB0_2:
91 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
92 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
93 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
94 ; RV64IZFHMIN-NEXT: ret
95 ;
96 ; RV32IZHINXMIN-LABEL: test_floor_si8:
97 ; RV32IZHINXMIN: # %bb.0:
98 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
99 ; RV32IZHINXMIN-NEXT: lui a1, 307200
100 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
101 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
102 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB0_2
103 ; RV32IZHINXMIN-NEXT: # %bb.1:
104 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
105 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
106 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
107 ; RV32IZHINXMIN-NEXT: .LBB0_2:
108 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
109 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
110 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
111 ; RV32IZHINXMIN-NEXT: ret
112 ;
113 ; RV64IZHINXMIN-LABEL: test_floor_si8:
114 ; RV64IZHINXMIN: # %bb.0:
115 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
116 ; RV64IZHINXMIN-NEXT: lui a1, 307200
117 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
118 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
119 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB0_2
120 ; RV64IZHINXMIN-NEXT: # %bb.1:
121 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
122 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
123 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
124 ; RV64IZHINXMIN-NEXT: .LBB0_2:
125 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
126 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
127 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
128 ; RV64IZHINXMIN-NEXT: ret
129 %a = call half @llvm.floor.f16(half %x)
130 %b = fptosi half %a to i8
131 ret i8 %b
132 }
134 define signext i16 @test_floor_si16(half %x) {
135 ; RV32IZFH-LABEL: test_floor_si16:
136 ; RV32IZFH: # %bb.0:
137 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rdn
138 ; RV32IZFH-NEXT: ret
139 ;
140 ; RV64IZFH-LABEL: test_floor_si16:
141 ; RV64IZFH: # %bb.0:
142 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rdn
143 ; RV64IZFH-NEXT: ret
144 ;
145 ; RV32IZHINX-LABEL: test_floor_si16:
146 ; RV32IZHINX: # %bb.0:
147 ; RV32IZHINX-NEXT: li a1, 25
148 ; RV32IZHINX-NEXT: slli a1, a1, 10
149 ; RV32IZHINX-NEXT: fabs.h a2, a0
150 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
151 ; RV32IZHINX-NEXT: beqz a1, .LBB1_2
152 ; RV32IZHINX-NEXT: # %bb.1:
153 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rdn
154 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rdn
155 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
156 ; RV32IZHINX-NEXT: .LBB1_2:
157 ; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
158 ; RV32IZHINX-NEXT: ret
159 ;
160 ; RV64IZHINX-LABEL: test_floor_si16:
161 ; RV64IZHINX: # %bb.0:
162 ; RV64IZHINX-NEXT: li a1, 25
163 ; RV64IZHINX-NEXT: slli a1, a1, 10
164 ; RV64IZHINX-NEXT: fabs.h a2, a0
165 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
166 ; RV64IZHINX-NEXT: beqz a1, .LBB1_2
167 ; RV64IZHINX-NEXT: # %bb.1:
168 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rdn
169 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rdn
170 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
171 ; RV64IZHINX-NEXT: .LBB1_2:
172 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
173 ; RV64IZHINX-NEXT: ret
174 ;
175 ; RV32IZFHMIN-LABEL: test_floor_si16:
176 ; RV32IZFHMIN: # %bb.0:
177 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
178 ; RV32IZFHMIN-NEXT: lui a0, 307200
179 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
180 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
181 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
182 ; RV32IZFHMIN-NEXT: beqz a0, .LBB1_2
183 ; RV32IZFHMIN-NEXT: # %bb.1:
184 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
185 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
186 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
187 ; RV32IZFHMIN-NEXT: .LBB1_2:
188 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
189 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
190 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
191 ; RV32IZFHMIN-NEXT: ret
192 ;
193 ; RV64IZFHMIN-LABEL: test_floor_si16:
194 ; RV64IZFHMIN: # %bb.0:
195 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
196 ; RV64IZFHMIN-NEXT: lui a0, 307200
197 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
198 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
199 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
200 ; RV64IZFHMIN-NEXT: beqz a0, .LBB1_2
201 ; RV64IZFHMIN-NEXT: # %bb.1:
202 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
203 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
204 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
205 ; RV64IZFHMIN-NEXT: .LBB1_2:
206 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
207 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
208 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
209 ; RV64IZFHMIN-NEXT: ret
210 ;
211 ; RV32IZHINXMIN-LABEL: test_floor_si16:
212 ; RV32IZHINXMIN: # %bb.0:
213 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
214 ; RV32IZHINXMIN-NEXT: lui a1, 307200
215 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
216 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
217 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB1_2
218 ; RV32IZHINXMIN-NEXT: # %bb.1:
219 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
220 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
221 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
222 ; RV32IZHINXMIN-NEXT: .LBB1_2:
223 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
224 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
225 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
226 ; RV32IZHINXMIN-NEXT: ret
227 ;
228 ; RV64IZHINXMIN-LABEL: test_floor_si16:
229 ; RV64IZHINXMIN: # %bb.0:
230 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
231 ; RV64IZHINXMIN-NEXT: lui a1, 307200
232 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
233 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
234 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB1_2
235 ; RV64IZHINXMIN-NEXT: # %bb.1:
236 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
237 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
238 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
239 ; RV64IZHINXMIN-NEXT: .LBB1_2:
240 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
241 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
242 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
243 ; RV64IZHINXMIN-NEXT: ret
244 %a = call half @llvm.floor.f16(half %x)
245 %b = fptosi half %a to i16
246 ret i16 %b
247 }
249 define signext i32 @test_floor_si32(half %x) {
250 ; CHECKIZFH-LABEL: test_floor_si32:
251 ; CHECKIZFH: # %bb.0:
252 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rdn
253 ; CHECKIZFH-NEXT: ret
254 ;
255 ; CHECKIZHINX-LABEL: test_floor_si32:
256 ; CHECKIZHINX: # %bb.0:
257 ; CHECKIZHINX-NEXT: li a1, 25
258 ; CHECKIZHINX-NEXT: slli a1, a1, 10
259 ; CHECKIZHINX-NEXT: fabs.h a2, a0
260 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
261 ; CHECKIZHINX-NEXT: beqz a1, .LBB2_2
262 ; CHECKIZHINX-NEXT: # %bb.1:
263 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rdn
264 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rdn
265 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
266 ; CHECKIZHINX-NEXT: .LBB2_2:
267 ; CHECKIZHINX-NEXT: fcvt.w.h a0, a0, rtz
268 ; CHECKIZHINX-NEXT: ret
269 ;
270 ; CHECKIZFHMIN-LABEL: test_floor_si32:
271 ; CHECKIZFHMIN: # %bb.0:
272 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
273 ; CHECKIZFHMIN-NEXT: lui a0, 307200
274 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
275 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
276 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
277 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB2_2
278 ; CHECKIZFHMIN-NEXT: # %bb.1:
279 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
280 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
281 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
282 ; CHECKIZFHMIN-NEXT: .LBB2_2:
283 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5
284 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5
285 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
286 ; CHECKIZFHMIN-NEXT: ret
287 ;
288 ; CHECKIZHINXMIN-LABEL: test_floor_si32:
289 ; CHECKIZHINXMIN: # %bb.0:
290 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
291 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
292 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
293 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
294 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB2_2
295 ; CHECKIZHINXMIN-NEXT: # %bb.1:
296 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
297 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
298 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
299 ; CHECKIZHINXMIN-NEXT: .LBB2_2:
300 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
301 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
302 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
303 ; CHECKIZHINXMIN-NEXT: ret
304 %a = call half @llvm.floor.f16(half %x)
305 %b = fptosi half %a to i32
306 ret i32 %b
307 }
309 define i64 @test_floor_si64(half %x) {
310 ; RV32IZFH-LABEL: test_floor_si64:
311 ; RV32IZFH: # %bb.0:
312 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI3_0)
313 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI3_0)(a0)
314 ; RV32IZFH-NEXT: fabs.h fa4, fa0
315 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
316 ; RV32IZFH-NEXT: beqz a0, .LBB3_2
317 ; RV32IZFH-NEXT: # %bb.1:
318 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rdn
319 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rdn
320 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
321 ; RV32IZFH-NEXT: .LBB3_2:
322 ; RV32IZFH-NEXT: addi sp, sp, -16
323 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
324 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
325 ; RV32IZFH-NEXT: .cfi_offset ra, -4
326 ; RV32IZFH-NEXT: call __fixhfdi
327 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
328 ; RV32IZFH-NEXT: .cfi_restore ra
329 ; RV32IZFH-NEXT: addi sp, sp, 16
330 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
331 ; RV32IZFH-NEXT: ret
332 ;
333 ; RV64IZFH-LABEL: test_floor_si64:
334 ; RV64IZFH: # %bb.0:
335 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rdn
336 ; RV64IZFH-NEXT: ret
337 ;
338 ; RV32IZHINX-LABEL: test_floor_si64:
339 ; RV32IZHINX: # %bb.0:
340 ; RV32IZHINX-NEXT: li a1, 25
341 ; RV32IZHINX-NEXT: slli a1, a1, 10
342 ; RV32IZHINX-NEXT: fabs.h a2, a0
343 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
344 ; RV32IZHINX-NEXT: beqz a1, .LBB3_2
345 ; RV32IZHINX-NEXT: # %bb.1:
346 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rdn
347 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rdn
348 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
349 ; RV32IZHINX-NEXT: .LBB3_2:
350 ; RV32IZHINX-NEXT: addi sp, sp, -16
351 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
352 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
353 ; RV32IZHINX-NEXT: .cfi_offset ra, -4
354 ; RV32IZHINX-NEXT: call __fixhfdi
355 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
356 ; RV32IZHINX-NEXT: .cfi_restore ra
357 ; RV32IZHINX-NEXT: addi sp, sp, 16
358 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
359 ; RV32IZHINX-NEXT: ret
360 ;
361 ; RV64IZHINX-LABEL: test_floor_si64:
362 ; RV64IZHINX: # %bb.0:
363 ; RV64IZHINX-NEXT: li a1, 25
364 ; RV64IZHINX-NEXT: slli a1, a1, 10
365 ; RV64IZHINX-NEXT: fabs.h a2, a0
366 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
367 ; RV64IZHINX-NEXT: beqz a1, .LBB3_2
368 ; RV64IZHINX-NEXT: # %bb.1:
369 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rdn
370 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rdn
371 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
372 ; RV64IZHINX-NEXT: .LBB3_2:
373 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
374 ; RV64IZHINX-NEXT: ret
375 ;
376 ; RV32IZFHMIN-LABEL: test_floor_si64:
377 ; RV32IZFHMIN: # %bb.0:
378 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
379 ; RV32IZFHMIN-NEXT: lui a0, 307200
380 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
381 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
382 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
383 ; RV32IZFHMIN-NEXT: beqz a0, .LBB3_2
384 ; RV32IZFHMIN-NEXT: # %bb.1:
385 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
386 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
387 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
388 ; RV32IZFHMIN-NEXT: .LBB3_2:
389 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
390 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
391 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
392 ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
393 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
394 ; RV32IZFHMIN-NEXT: call __fixhfdi
395 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
396 ; RV32IZFHMIN-NEXT: .cfi_restore ra
397 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
398 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
399 ; RV32IZFHMIN-NEXT: ret
400 ;
401 ; RV64IZFHMIN-LABEL: test_floor_si64:
402 ; RV64IZFHMIN: # %bb.0:
403 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
404 ; RV64IZFHMIN-NEXT: lui a0, 307200
405 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
406 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
407 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
408 ; RV64IZFHMIN-NEXT: beqz a0, .LBB3_2
409 ; RV64IZFHMIN-NEXT: # %bb.1:
410 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
411 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
412 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
413 ; RV64IZFHMIN-NEXT: .LBB3_2:
414 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
415 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
416 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
417 ; RV64IZFHMIN-NEXT: ret
418 ;
419 ; RV32IZHINXMIN-LABEL: test_floor_si64:
420 ; RV32IZHINXMIN: # %bb.0:
421 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
422 ; RV32IZHINXMIN-NEXT: lui a1, 307200
423 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
424 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
425 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB3_2
426 ; RV32IZHINXMIN-NEXT: # %bb.1:
427 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
428 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
429 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
430 ; RV32IZHINXMIN-NEXT: .LBB3_2:
431 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
432 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
433 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
434 ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
435 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
436 ; RV32IZHINXMIN-NEXT: call __fixhfdi
437 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
438 ; RV32IZHINXMIN-NEXT: .cfi_restore ra
439 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
440 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
441 ; RV32IZHINXMIN-NEXT: ret
442 ;
443 ; RV64IZHINXMIN-LABEL: test_floor_si64:
444 ; RV64IZHINXMIN: # %bb.0:
445 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
446 ; RV64IZHINXMIN-NEXT: lui a1, 307200
447 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
448 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
449 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB3_2
450 ; RV64IZHINXMIN-NEXT: # %bb.1:
451 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
452 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
453 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
454 ; RV64IZHINXMIN-NEXT: .LBB3_2:
455 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
456 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
457 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
458 ; RV64IZHINXMIN-NEXT: ret
459 %a = call half @llvm.floor.f16(half %x)
460 %b = fptosi half %a to i64
461 ret i64 %b
462 }
464 define zeroext i8 @test_floor_ui8(half %x) {
465 ; RV32IZFH-LABEL: test_floor_ui8:
466 ; RV32IZFH: # %bb.0:
467 ; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rdn
468 ; RV32IZFH-NEXT: ret
469 ;
470 ; RV64IZFH-LABEL: test_floor_ui8:
471 ; RV64IZFH: # %bb.0:
472 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rdn
473 ; RV64IZFH-NEXT: ret
474 ;
475 ; RV32IZHINX-LABEL: test_floor_ui8:
476 ; RV32IZHINX: # %bb.0:
477 ; RV32IZHINX-NEXT: li a1, 25
478 ; RV32IZHINX-NEXT: slli a1, a1, 10
479 ; RV32IZHINX-NEXT: fabs.h a2, a0
480 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
481 ; RV32IZHINX-NEXT: beqz a1, .LBB4_2
482 ; RV32IZHINX-NEXT: # %bb.1:
483 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rdn
484 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rdn
485 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
486 ; RV32IZHINX-NEXT: .LBB4_2:
487 ; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
488 ; RV32IZHINX-NEXT: ret
489 ;
490 ; RV64IZHINX-LABEL: test_floor_ui8:
491 ; RV64IZHINX: # %bb.0:
492 ; RV64IZHINX-NEXT: li a1, 25
493 ; RV64IZHINX-NEXT: slli a1, a1, 10
494 ; RV64IZHINX-NEXT: fabs.h a2, a0
495 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
496 ; RV64IZHINX-NEXT: beqz a1, .LBB4_2
497 ; RV64IZHINX-NEXT: # %bb.1:
498 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rdn
499 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rdn
500 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
501 ; RV64IZHINX-NEXT: .LBB4_2:
502 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
503 ; RV64IZHINX-NEXT: ret
504 ;
505 ; RV32IZFHMIN-LABEL: test_floor_ui8:
506 ; RV32IZFHMIN: # %bb.0:
507 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
508 ; RV32IZFHMIN-NEXT: lui a0, 307200
509 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
510 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
511 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
512 ; RV32IZFHMIN-NEXT: beqz a0, .LBB4_2
513 ; RV32IZFHMIN-NEXT: # %bb.1:
514 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
515 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
516 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
517 ; RV32IZFHMIN-NEXT: .LBB4_2:
518 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
519 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
520 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
521 ; RV32IZFHMIN-NEXT: ret
522 ;
523 ; RV64IZFHMIN-LABEL: test_floor_ui8:
524 ; RV64IZFHMIN: # %bb.0:
525 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
526 ; RV64IZFHMIN-NEXT: lui a0, 307200
527 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
528 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
529 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
530 ; RV64IZFHMIN-NEXT: beqz a0, .LBB4_2
531 ; RV64IZFHMIN-NEXT: # %bb.1:
532 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
533 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
534 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
535 ; RV64IZFHMIN-NEXT: .LBB4_2:
536 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
537 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
538 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
539 ; RV64IZFHMIN-NEXT: ret
540 ;
541 ; RV32IZHINXMIN-LABEL: test_floor_ui8:
542 ; RV32IZHINXMIN: # %bb.0:
543 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
544 ; RV32IZHINXMIN-NEXT: lui a1, 307200
545 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
546 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
547 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB4_2
548 ; RV32IZHINXMIN-NEXT: # %bb.1:
549 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
550 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
551 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
552 ; RV32IZHINXMIN-NEXT: .LBB4_2:
553 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
554 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
555 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
556 ; RV32IZHINXMIN-NEXT: ret
557 ;
558 ; RV64IZHINXMIN-LABEL: test_floor_ui8:
559 ; RV64IZHINXMIN: # %bb.0:
560 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
561 ; RV64IZHINXMIN-NEXT: lui a1, 307200
562 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
563 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
564 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB4_2
565 ; RV64IZHINXMIN-NEXT: # %bb.1:
566 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
567 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
568 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
569 ; RV64IZHINXMIN-NEXT: .LBB4_2:
570 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
571 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
572 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
573 ; RV64IZHINXMIN-NEXT: ret
574 %a = call half @llvm.floor.f16(half %x)
575 %b = fptoui half %a to i8
576 ret i8 %b
577 }
579 define zeroext i16 @test_floor_ui16(half %x) {
580 ; RV32IZFH-LABEL: test_floor_ui16:
581 ; RV32IZFH: # %bb.0:
582 ; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rdn
583 ; RV32IZFH-NEXT: ret
584 ;
585 ; RV64IZFH-LABEL: test_floor_ui16:
586 ; RV64IZFH: # %bb.0:
587 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rdn
588 ; RV64IZFH-NEXT: ret
589 ;
590 ; RV32IZHINX-LABEL: test_floor_ui16:
591 ; RV32IZHINX: # %bb.0:
592 ; RV32IZHINX-NEXT: li a1, 25
593 ; RV32IZHINX-NEXT: slli a1, a1, 10
594 ; RV32IZHINX-NEXT: fabs.h a2, a0
595 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
596 ; RV32IZHINX-NEXT: beqz a1, .LBB5_2
597 ; RV32IZHINX-NEXT: # %bb.1:
598 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rdn
599 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rdn
600 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
601 ; RV32IZHINX-NEXT: .LBB5_2:
602 ; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
603 ; RV32IZHINX-NEXT: ret
604 ;
605 ; RV64IZHINX-LABEL: test_floor_ui16:
606 ; RV64IZHINX: # %bb.0:
607 ; RV64IZHINX-NEXT: li a1, 25
608 ; RV64IZHINX-NEXT: slli a1, a1, 10
609 ; RV64IZHINX-NEXT: fabs.h a2, a0
610 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
611 ; RV64IZHINX-NEXT: beqz a1, .LBB5_2
612 ; RV64IZHINX-NEXT: # %bb.1:
613 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rdn
614 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rdn
615 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
616 ; RV64IZHINX-NEXT: .LBB5_2:
617 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
618 ; RV64IZHINX-NEXT: ret
619 ;
620 ; RV32IZFHMIN-LABEL: test_floor_ui16:
621 ; RV32IZFHMIN: # %bb.0:
622 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
623 ; RV32IZFHMIN-NEXT: lui a0, 307200
624 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
625 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
626 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
627 ; RV32IZFHMIN-NEXT: beqz a0, .LBB5_2
628 ; RV32IZFHMIN-NEXT: # %bb.1:
629 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
630 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
631 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
632 ; RV32IZFHMIN-NEXT: .LBB5_2:
633 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
634 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
635 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
636 ; RV32IZFHMIN-NEXT: ret
637 ;
638 ; RV64IZFHMIN-LABEL: test_floor_ui16:
639 ; RV64IZFHMIN: # %bb.0:
640 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
641 ; RV64IZFHMIN-NEXT: lui a0, 307200
642 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
643 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
644 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
645 ; RV64IZFHMIN-NEXT: beqz a0, .LBB5_2
646 ; RV64IZFHMIN-NEXT: # %bb.1:
647 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
648 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
649 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
650 ; RV64IZFHMIN-NEXT: .LBB5_2:
651 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
652 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
653 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
654 ; RV64IZFHMIN-NEXT: ret
655 ;
656 ; RV32IZHINXMIN-LABEL: test_floor_ui16:
657 ; RV32IZHINXMIN: # %bb.0:
658 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
659 ; RV32IZHINXMIN-NEXT: lui a1, 307200
660 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
661 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
662 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB5_2
663 ; RV32IZHINXMIN-NEXT: # %bb.1:
664 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
665 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
666 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
667 ; RV32IZHINXMIN-NEXT: .LBB5_2:
668 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
669 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
670 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
671 ; RV32IZHINXMIN-NEXT: ret
672 ;
673 ; RV64IZHINXMIN-LABEL: test_floor_ui16:
674 ; RV64IZHINXMIN: # %bb.0:
675 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
676 ; RV64IZHINXMIN-NEXT: lui a1, 307200
677 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
678 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
679 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB5_2
680 ; RV64IZHINXMIN-NEXT: # %bb.1:
681 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
682 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
683 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
684 ; RV64IZHINXMIN-NEXT: .LBB5_2:
685 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
686 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
687 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
688 ; RV64IZHINXMIN-NEXT: ret
689 %a = call half @llvm.floor.f16(half %x)
690 %b = fptoui half %a to i16
691 ret i16 %b
692 }
694 define signext i32 @test_floor_ui32(half %x) {
695 ; CHECKIZFH-LABEL: test_floor_ui32:
696 ; CHECKIZFH: # %bb.0:
697 ; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rdn
698 ; CHECKIZFH-NEXT: ret
699 ;
700 ; CHECKIZHINX-LABEL: test_floor_ui32:
701 ; CHECKIZHINX: # %bb.0:
702 ; CHECKIZHINX-NEXT: li a1, 25
703 ; CHECKIZHINX-NEXT: slli a1, a1, 10
704 ; CHECKIZHINX-NEXT: fabs.h a2, a0
705 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
706 ; CHECKIZHINX-NEXT: beqz a1, .LBB6_2
707 ; CHECKIZHINX-NEXT: # %bb.1:
708 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rdn
709 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rdn
710 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
711 ; CHECKIZHINX-NEXT: .LBB6_2:
712 ; CHECKIZHINX-NEXT: fcvt.wu.h a0, a0, rtz
713 ; CHECKIZHINX-NEXT: ret
714 ;
715 ; CHECKIZFHMIN-LABEL: test_floor_ui32:
716 ; CHECKIZFHMIN: # %bb.0:
717 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
718 ; CHECKIZFHMIN-NEXT: lui a0, 307200
719 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
720 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
721 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
722 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB6_2
723 ; CHECKIZFHMIN-NEXT: # %bb.1:
724 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
725 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
726 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
727 ; CHECKIZFHMIN-NEXT: .LBB6_2:
728 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5
729 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5
730 ; CHECKIZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
731 ; CHECKIZFHMIN-NEXT: ret
732 ;
733 ; CHECKIZHINXMIN-LABEL: test_floor_ui32:
734 ; CHECKIZHINXMIN: # %bb.0:
735 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
736 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
737 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
738 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
739 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB6_2
740 ; CHECKIZHINXMIN-NEXT: # %bb.1:
741 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
742 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
743 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
744 ; CHECKIZHINXMIN-NEXT: .LBB6_2:
745 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
746 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
747 ; CHECKIZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
748 ; CHECKIZHINXMIN-NEXT: ret
749 %a = call half @llvm.floor.f16(half %x)
750 %b = fptoui half %a to i32
751 ret i32 %b
752 }
754 define i64 @test_floor_ui64(half %x) {
755 ; RV32IZFH-LABEL: test_floor_ui64:
756 ; RV32IZFH: # %bb.0:
757 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI7_0)
758 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI7_0)(a0)
759 ; RV32IZFH-NEXT: fabs.h fa4, fa0
760 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
761 ; RV32IZFH-NEXT: beqz a0, .LBB7_2
762 ; RV32IZFH-NEXT: # %bb.1:
763 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rdn
764 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rdn
765 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
766 ; RV32IZFH-NEXT: .LBB7_2:
767 ; RV32IZFH-NEXT: addi sp, sp, -16
768 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
769 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
770 ; RV32IZFH-NEXT: .cfi_offset ra, -4
771 ; RV32IZFH-NEXT: call __fixunshfdi
772 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
773 ; RV32IZFH-NEXT: .cfi_restore ra
774 ; RV32IZFH-NEXT: addi sp, sp, 16
775 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
776 ; RV32IZFH-NEXT: ret
777 ;
778 ; RV64IZFH-LABEL: test_floor_ui64:
779 ; RV64IZFH: # %bb.0:
780 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rdn
781 ; RV64IZFH-NEXT: ret
782 ;
783 ; RV32IZHINX-LABEL: test_floor_ui64:
784 ; RV32IZHINX: # %bb.0:
785 ; RV32IZHINX-NEXT: li a1, 25
786 ; RV32IZHINX-NEXT: slli a1, a1, 10
787 ; RV32IZHINX-NEXT: fabs.h a2, a0
788 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
789 ; RV32IZHINX-NEXT: beqz a1, .LBB7_2
790 ; RV32IZHINX-NEXT: # %bb.1:
791 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rdn
792 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rdn
793 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
794 ; RV32IZHINX-NEXT: .LBB7_2:
795 ; RV32IZHINX-NEXT: addi sp, sp, -16
796 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
797 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
798 ; RV32IZHINX-NEXT: .cfi_offset ra, -4
799 ; RV32IZHINX-NEXT: call __fixunshfdi
800 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
801 ; RV32IZHINX-NEXT: .cfi_restore ra
802 ; RV32IZHINX-NEXT: addi sp, sp, 16
803 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
804 ; RV32IZHINX-NEXT: ret
805 ;
806 ; RV64IZHINX-LABEL: test_floor_ui64:
807 ; RV64IZHINX: # %bb.0:
808 ; RV64IZHINX-NEXT: li a1, 25
809 ; RV64IZHINX-NEXT: slli a1, a1, 10
810 ; RV64IZHINX-NEXT: fabs.h a2, a0
811 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
812 ; RV64IZHINX-NEXT: beqz a1, .LBB7_2
813 ; RV64IZHINX-NEXT: # %bb.1:
814 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rdn
815 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rdn
816 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
817 ; RV64IZHINX-NEXT: .LBB7_2:
818 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
819 ; RV64IZHINX-NEXT: ret
820 ;
821 ; RV32IZFHMIN-LABEL: test_floor_ui64:
822 ; RV32IZFHMIN: # %bb.0:
823 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
824 ; RV32IZFHMIN-NEXT: lui a0, 307200
825 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
826 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
827 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
828 ; RV32IZFHMIN-NEXT: beqz a0, .LBB7_2
829 ; RV32IZFHMIN-NEXT: # %bb.1:
830 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
831 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
832 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
833 ; RV32IZFHMIN-NEXT: .LBB7_2:
834 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
835 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
836 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
837 ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
838 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
839 ; RV32IZFHMIN-NEXT: call __fixunshfdi
840 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
841 ; RV32IZFHMIN-NEXT: .cfi_restore ra
842 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
843 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
844 ; RV32IZFHMIN-NEXT: ret
845 ;
846 ; RV64IZFHMIN-LABEL: test_floor_ui64:
847 ; RV64IZFHMIN: # %bb.0:
848 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
849 ; RV64IZFHMIN-NEXT: lui a0, 307200
850 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
851 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
852 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
853 ; RV64IZFHMIN-NEXT: beqz a0, .LBB7_2
854 ; RV64IZFHMIN-NEXT: # %bb.1:
855 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
856 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
857 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
858 ; RV64IZFHMIN-NEXT: .LBB7_2:
859 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
860 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
861 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
862 ; RV64IZFHMIN-NEXT: ret
863 ;
864 ; RV32IZHINXMIN-LABEL: test_floor_ui64:
865 ; RV32IZHINXMIN: # %bb.0:
866 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
867 ; RV32IZHINXMIN-NEXT: lui a1, 307200
868 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
869 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
870 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB7_2
871 ; RV32IZHINXMIN-NEXT: # %bb.1:
872 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
873 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
874 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
875 ; RV32IZHINXMIN-NEXT: .LBB7_2:
876 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
877 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
878 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
879 ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
880 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
881 ; RV32IZHINXMIN-NEXT: call __fixunshfdi
882 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
883 ; RV32IZHINXMIN-NEXT: .cfi_restore ra
884 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
885 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
886 ; RV32IZHINXMIN-NEXT: ret
887 ;
888 ; RV64IZHINXMIN-LABEL: test_floor_ui64:
889 ; RV64IZHINXMIN: # %bb.0:
890 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
891 ; RV64IZHINXMIN-NEXT: lui a1, 307200
892 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
893 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
894 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB7_2
895 ; RV64IZHINXMIN-NEXT: # %bb.1:
896 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
897 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
898 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
899 ; RV64IZHINXMIN-NEXT: .LBB7_2:
900 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
901 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
902 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
903 ; RV64IZHINXMIN-NEXT: ret
904 %a = call half @llvm.floor.f16(half %x)
905 %b = fptoui half %a to i64
906 ret i64 %b
907 }
909 define signext i8 @test_ceil_si8(half %x) {
910 ; RV32IZFH-LABEL: test_ceil_si8:
911 ; RV32IZFH: # %bb.0:
912 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rup
913 ; RV32IZFH-NEXT: ret
914 ;
915 ; RV64IZFH-LABEL: test_ceil_si8:
916 ; RV64IZFH: # %bb.0:
917 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rup
918 ; RV64IZFH-NEXT: ret
919 ;
920 ; RV32IZHINX-LABEL: test_ceil_si8:
921 ; RV32IZHINX: # %bb.0:
922 ; RV32IZHINX-NEXT: li a1, 25
923 ; RV32IZHINX-NEXT: slli a1, a1, 10
924 ; RV32IZHINX-NEXT: fabs.h a2, a0
925 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
926 ; RV32IZHINX-NEXT: beqz a1, .LBB8_2
927 ; RV32IZHINX-NEXT: # %bb.1:
928 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rup
929 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rup
930 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
931 ; RV32IZHINX-NEXT: .LBB8_2:
932 ; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
933 ; RV32IZHINX-NEXT: ret
934 ;
935 ; RV64IZHINX-LABEL: test_ceil_si8:
936 ; RV64IZHINX: # %bb.0:
937 ; RV64IZHINX-NEXT: li a1, 25
938 ; RV64IZHINX-NEXT: slli a1, a1, 10
939 ; RV64IZHINX-NEXT: fabs.h a2, a0
940 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
941 ; RV64IZHINX-NEXT: beqz a1, .LBB8_2
942 ; RV64IZHINX-NEXT: # %bb.1:
943 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rup
944 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rup
945 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
946 ; RV64IZHINX-NEXT: .LBB8_2:
947 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
948 ; RV64IZHINX-NEXT: ret
949 ;
950 ; RV32IZFHMIN-LABEL: test_ceil_si8:
951 ; RV32IZFHMIN: # %bb.0:
952 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
953 ; RV32IZFHMIN-NEXT: lui a0, 307200
954 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
955 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
956 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
957 ; RV32IZFHMIN-NEXT: beqz a0, .LBB8_2
958 ; RV32IZFHMIN-NEXT: # %bb.1:
959 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
960 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
961 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
962 ; RV32IZFHMIN-NEXT: .LBB8_2:
963 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
964 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
965 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
966 ; RV32IZFHMIN-NEXT: ret
967 ;
968 ; RV64IZFHMIN-LABEL: test_ceil_si8:
969 ; RV64IZFHMIN: # %bb.0:
970 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
971 ; RV64IZFHMIN-NEXT: lui a0, 307200
972 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
973 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
974 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
975 ; RV64IZFHMIN-NEXT: beqz a0, .LBB8_2
976 ; RV64IZFHMIN-NEXT: # %bb.1:
977 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
978 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
979 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
980 ; RV64IZFHMIN-NEXT: .LBB8_2:
981 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
982 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
983 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
984 ; RV64IZFHMIN-NEXT: ret
985 ;
986 ; RV32IZHINXMIN-LABEL: test_ceil_si8:
987 ; RV32IZHINXMIN: # %bb.0:
988 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
989 ; RV32IZHINXMIN-NEXT: lui a1, 307200
990 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
991 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
992 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB8_2
993 ; RV32IZHINXMIN-NEXT: # %bb.1:
994 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
995 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
996 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
997 ; RV32IZHINXMIN-NEXT: .LBB8_2:
998 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
999 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1000 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
1001 ; RV32IZHINXMIN-NEXT: ret
1002 ;
1003 ; RV64IZHINXMIN-LABEL: test_ceil_si8:
1004 ; RV64IZHINXMIN: # %bb.0:
1005 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1006 ; RV64IZHINXMIN-NEXT: lui a1, 307200
1007 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
1008 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
1009 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB8_2
1010 ; RV64IZHINXMIN-NEXT: # %bb.1:
1011 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1012 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1013 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1014 ; RV64IZHINXMIN-NEXT: .LBB8_2:
1015 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
1016 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1017 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
1018 ; RV64IZHINXMIN-NEXT: ret
1019 %a = call half @llvm.ceil.f16(half %x)
1020 %b = fptosi half %a to i8
1021 ret i8 %b
1022 }
1024 define signext i16 @test_ceil_si16(half %x) {
1025 ; RV32IZFH-LABEL: test_ceil_si16:
1026 ; RV32IZFH: # %bb.0:
1027 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rup
1028 ; RV32IZFH-NEXT: ret
1029 ;
1030 ; RV64IZFH-LABEL: test_ceil_si16:
1031 ; RV64IZFH: # %bb.0:
1032 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rup
1033 ; RV64IZFH-NEXT: ret
1034 ;
1035 ; RV32IZHINX-LABEL: test_ceil_si16:
1036 ; RV32IZHINX: # %bb.0:
1037 ; RV32IZHINX-NEXT: li a1, 25
1038 ; RV32IZHINX-NEXT: slli a1, a1, 10
1039 ; RV32IZHINX-NEXT: fabs.h a2, a0
1040 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
1041 ; RV32IZHINX-NEXT: beqz a1, .LBB9_2
1042 ; RV32IZHINX-NEXT: # %bb.1:
1043 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rup
1044 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rup
1045 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
1046 ; RV32IZHINX-NEXT: .LBB9_2:
1047 ; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
1048 ; RV32IZHINX-NEXT: ret
1049 ;
1050 ; RV64IZHINX-LABEL: test_ceil_si16:
1051 ; RV64IZHINX: # %bb.0:
1052 ; RV64IZHINX-NEXT: li a1, 25
1053 ; RV64IZHINX-NEXT: slli a1, a1, 10
1054 ; RV64IZHINX-NEXT: fabs.h a2, a0
1055 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
1056 ; RV64IZHINX-NEXT: beqz a1, .LBB9_2
1057 ; RV64IZHINX-NEXT: # %bb.1:
1058 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rup
1059 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rup
1060 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
1061 ; RV64IZHINX-NEXT: .LBB9_2:
1062 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
1063 ; RV64IZHINX-NEXT: ret
1064 ;
1065 ; RV32IZFHMIN-LABEL: test_ceil_si16:
1066 ; RV32IZFHMIN: # %bb.0:
1067 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1068 ; RV32IZFHMIN-NEXT: lui a0, 307200
1069 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
1070 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
1071 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
1072 ; RV32IZFHMIN-NEXT: beqz a0, .LBB9_2
1073 ; RV32IZFHMIN-NEXT: # %bb.1:
1074 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1075 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1076 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1077 ; RV32IZFHMIN-NEXT: .LBB9_2:
1078 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1079 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1080 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
1081 ; RV32IZFHMIN-NEXT: ret
1082 ;
1083 ; RV64IZFHMIN-LABEL: test_ceil_si16:
1084 ; RV64IZFHMIN: # %bb.0:
1085 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1086 ; RV64IZFHMIN-NEXT: lui a0, 307200
1087 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
1088 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
1089 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
1090 ; RV64IZFHMIN-NEXT: beqz a0, .LBB9_2
1091 ; RV64IZFHMIN-NEXT: # %bb.1:
1092 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1093 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1094 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1095 ; RV64IZFHMIN-NEXT: .LBB9_2:
1096 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1097 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1098 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
1099 ; RV64IZFHMIN-NEXT: ret
1100 ;
1101 ; RV32IZHINXMIN-LABEL: test_ceil_si16:
1102 ; RV32IZHINXMIN: # %bb.0:
1103 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1104 ; RV32IZHINXMIN-NEXT: lui a1, 307200
1105 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
1106 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
1107 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB9_2
1108 ; RV32IZHINXMIN-NEXT: # %bb.1:
1109 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1110 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1111 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1112 ; RV32IZHINXMIN-NEXT: .LBB9_2:
1113 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
1114 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1115 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
1116 ; RV32IZHINXMIN-NEXT: ret
1117 ;
1118 ; RV64IZHINXMIN-LABEL: test_ceil_si16:
1119 ; RV64IZHINXMIN: # %bb.0:
1120 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1121 ; RV64IZHINXMIN-NEXT: lui a1, 307200
1122 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
1123 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
1124 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB9_2
1125 ; RV64IZHINXMIN-NEXT: # %bb.1:
1126 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1127 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1128 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1129 ; RV64IZHINXMIN-NEXT: .LBB9_2:
1130 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
1131 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1132 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
1133 ; RV64IZHINXMIN-NEXT: ret
1134 %a = call half @llvm.ceil.f16(half %x)
1135 %b = fptosi half %a to i16
1136 ret i16 %b
1137 }
1139 define signext i32 @test_ceil_si32(half %x) {
1140 ; CHECKIZFH-LABEL: test_ceil_si32:
1141 ; CHECKIZFH: # %bb.0:
1142 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rup
1143 ; CHECKIZFH-NEXT: ret
1144 ;
1145 ; CHECKIZHINX-LABEL: test_ceil_si32:
1146 ; CHECKIZHINX: # %bb.0:
1147 ; CHECKIZHINX-NEXT: li a1, 25
1148 ; CHECKIZHINX-NEXT: slli a1, a1, 10
1149 ; CHECKIZHINX-NEXT: fabs.h a2, a0
1150 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
1151 ; CHECKIZHINX-NEXT: beqz a1, .LBB10_2
1152 ; CHECKIZHINX-NEXT: # %bb.1:
1153 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rup
1154 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rup
1155 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
1156 ; CHECKIZHINX-NEXT: .LBB10_2:
1157 ; CHECKIZHINX-NEXT: fcvt.w.h a0, a0, rtz
1158 ; CHECKIZHINX-NEXT: ret
1159 ;
1160 ; CHECKIZFHMIN-LABEL: test_ceil_si32:
1161 ; CHECKIZFHMIN: # %bb.0:
1162 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
1163 ; CHECKIZFHMIN-NEXT: lui a0, 307200
1164 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
1165 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
1166 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
1167 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB10_2
1168 ; CHECKIZFHMIN-NEXT: # %bb.1:
1169 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1170 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1171 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1172 ; CHECKIZFHMIN-NEXT: .LBB10_2:
1173 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5
1174 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5
1175 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
1176 ; CHECKIZFHMIN-NEXT: ret
1177 ;
1178 ; CHECKIZHINXMIN-LABEL: test_ceil_si32:
1179 ; CHECKIZHINXMIN: # %bb.0:
1180 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
1181 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
1182 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
1183 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
1184 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB10_2
1185 ; CHECKIZHINXMIN-NEXT: # %bb.1:
1186 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1187 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1188 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1189 ; CHECKIZHINXMIN-NEXT: .LBB10_2:
1190 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
1191 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
1192 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
1193 ; CHECKIZHINXMIN-NEXT: ret
1194 %a = call half @llvm.ceil.f16(half %x)
1195 %b = fptosi half %a to i32
1196 ret i32 %b
1197 }
1199 define i64 @test_ceil_si64(half %x) {
1200 ; RV32IZFH-LABEL: test_ceil_si64:
1201 ; RV32IZFH: # %bb.0:
1202 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI11_0)
1203 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI11_0)(a0)
1204 ; RV32IZFH-NEXT: fabs.h fa4, fa0
1205 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
1206 ; RV32IZFH-NEXT: beqz a0, .LBB11_2
1207 ; RV32IZFH-NEXT: # %bb.1:
1208 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rup
1209 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rup
1210 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
1211 ; RV32IZFH-NEXT: .LBB11_2:
1212 ; RV32IZFH-NEXT: addi sp, sp, -16
1213 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
1214 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1215 ; RV32IZFH-NEXT: .cfi_offset ra, -4
1216 ; RV32IZFH-NEXT: call __fixhfdi
1217 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1218 ; RV32IZFH-NEXT: .cfi_restore ra
1219 ; RV32IZFH-NEXT: addi sp, sp, 16
1220 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
1221 ; RV32IZFH-NEXT: ret
1222 ;
1223 ; RV64IZFH-LABEL: test_ceil_si64:
1224 ; RV64IZFH: # %bb.0:
1225 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rup
1226 ; RV64IZFH-NEXT: ret
1227 ;
1228 ; RV32IZHINX-LABEL: test_ceil_si64:
1229 ; RV32IZHINX: # %bb.0:
1230 ; RV32IZHINX-NEXT: li a1, 25
1231 ; RV32IZHINX-NEXT: slli a1, a1, 10
1232 ; RV32IZHINX-NEXT: fabs.h a2, a0
1233 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
1234 ; RV32IZHINX-NEXT: beqz a1, .LBB11_2
1235 ; RV32IZHINX-NEXT: # %bb.1:
1236 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rup
1237 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rup
1238 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
1239 ; RV32IZHINX-NEXT: .LBB11_2:
1240 ; RV32IZHINX-NEXT: addi sp, sp, -16
1241 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
1242 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1243 ; RV32IZHINX-NEXT: .cfi_offset ra, -4
1244 ; RV32IZHINX-NEXT: call __fixhfdi
1245 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1246 ; RV32IZHINX-NEXT: .cfi_restore ra
1247 ; RV32IZHINX-NEXT: addi sp, sp, 16
1248 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
1249 ; RV32IZHINX-NEXT: ret
1250 ;
1251 ; RV64IZHINX-LABEL: test_ceil_si64:
1252 ; RV64IZHINX: # %bb.0:
1253 ; RV64IZHINX-NEXT: li a1, 25
1254 ; RV64IZHINX-NEXT: slli a1, a1, 10
1255 ; RV64IZHINX-NEXT: fabs.h a2, a0
1256 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
1257 ; RV64IZHINX-NEXT: beqz a1, .LBB11_2
1258 ; RV64IZHINX-NEXT: # %bb.1:
1259 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rup
1260 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rup
1261 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
1262 ; RV64IZHINX-NEXT: .LBB11_2:
1263 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
1264 ; RV64IZHINX-NEXT: ret
1265 ;
1266 ; RV32IZFHMIN-LABEL: test_ceil_si64:
1267 ; RV32IZFHMIN: # %bb.0:
1268 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1269 ; RV32IZFHMIN-NEXT: lui a0, 307200
1270 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
1271 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
1272 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
1273 ; RV32IZFHMIN-NEXT: beqz a0, .LBB11_2
1274 ; RV32IZFHMIN-NEXT: # %bb.1:
1275 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1276 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1277 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1278 ; RV32IZFHMIN-NEXT: .LBB11_2:
1279 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
1280 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
1281 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1282 ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
1283 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
1284 ; RV32IZFHMIN-NEXT: call __fixhfdi
1285 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1286 ; RV32IZFHMIN-NEXT: .cfi_restore ra
1287 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
1288 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
1289 ; RV32IZFHMIN-NEXT: ret
1290 ;
1291 ; RV64IZFHMIN-LABEL: test_ceil_si64:
1292 ; RV64IZFHMIN: # %bb.0:
1293 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1294 ; RV64IZFHMIN-NEXT: lui a0, 307200
1295 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
1296 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
1297 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
1298 ; RV64IZFHMIN-NEXT: beqz a0, .LBB11_2
1299 ; RV64IZFHMIN-NEXT: # %bb.1:
1300 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1301 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1302 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1303 ; RV64IZFHMIN-NEXT: .LBB11_2:
1304 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1305 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1306 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
1307 ; RV64IZFHMIN-NEXT: ret
1308 ;
1309 ; RV32IZHINXMIN-LABEL: test_ceil_si64:
1310 ; RV32IZHINXMIN: # %bb.0:
1311 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1312 ; RV32IZHINXMIN-NEXT: lui a1, 307200
1313 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
1314 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
1315 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB11_2
1316 ; RV32IZHINXMIN-NEXT: # %bb.1:
1317 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1318 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1319 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1320 ; RV32IZHINXMIN-NEXT: .LBB11_2:
1321 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
1322 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
1323 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1324 ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
1325 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
1326 ; RV32IZHINXMIN-NEXT: call __fixhfdi
1327 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1328 ; RV32IZHINXMIN-NEXT: .cfi_restore ra
1329 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
1330 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
1331 ; RV32IZHINXMIN-NEXT: ret
1332 ;
1333 ; RV64IZHINXMIN-LABEL: test_ceil_si64:
1334 ; RV64IZHINXMIN: # %bb.0:
1335 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1336 ; RV64IZHINXMIN-NEXT: lui a1, 307200
1337 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
1338 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
1339 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB11_2
1340 ; RV64IZHINXMIN-NEXT: # %bb.1:
1341 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1342 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1343 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1344 ; RV64IZHINXMIN-NEXT: .LBB11_2:
1345 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
1346 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1347 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
1348 ; RV64IZHINXMIN-NEXT: ret
1349 %a = call half @llvm.ceil.f16(half %x)
1350 %b = fptosi half %a to i64
1351 ret i64 %b
1352 }
1354 define zeroext i8 @test_ceil_ui8(half %x) {
1355 ; RV32IZFH-LABEL: test_ceil_ui8:
1356 ; RV32IZFH: # %bb.0:
1357 ; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rup
1358 ; RV32IZFH-NEXT: ret
1359 ;
1360 ; RV64IZFH-LABEL: test_ceil_ui8:
1361 ; RV64IZFH: # %bb.0:
1362 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rup
1363 ; RV64IZFH-NEXT: ret
1364 ;
1365 ; RV32IZHINX-LABEL: test_ceil_ui8:
1366 ; RV32IZHINX: # %bb.0:
1367 ; RV32IZHINX-NEXT: li a1, 25
1368 ; RV32IZHINX-NEXT: slli a1, a1, 10
1369 ; RV32IZHINX-NEXT: fabs.h a2, a0
1370 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
1371 ; RV32IZHINX-NEXT: beqz a1, .LBB12_2
1372 ; RV32IZHINX-NEXT: # %bb.1:
1373 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rup
1374 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rup
1375 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
1376 ; RV32IZHINX-NEXT: .LBB12_2:
1377 ; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
1378 ; RV32IZHINX-NEXT: ret
1379 ;
1380 ; RV64IZHINX-LABEL: test_ceil_ui8:
1381 ; RV64IZHINX: # %bb.0:
1382 ; RV64IZHINX-NEXT: li a1, 25
1383 ; RV64IZHINX-NEXT: slli a1, a1, 10
1384 ; RV64IZHINX-NEXT: fabs.h a2, a0
1385 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
1386 ; RV64IZHINX-NEXT: beqz a1, .LBB12_2
1387 ; RV64IZHINX-NEXT: # %bb.1:
1388 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rup
1389 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rup
1390 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
1391 ; RV64IZHINX-NEXT: .LBB12_2:
1392 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
1393 ; RV64IZHINX-NEXT: ret
1394 ;
1395 ; RV32IZFHMIN-LABEL: test_ceil_ui8:
1396 ; RV32IZFHMIN: # %bb.0:
1397 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1398 ; RV32IZFHMIN-NEXT: lui a0, 307200
1399 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
1400 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
1401 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
1402 ; RV32IZFHMIN-NEXT: beqz a0, .LBB12_2
1403 ; RV32IZFHMIN-NEXT: # %bb.1:
1404 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1405 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1406 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1407 ; RV32IZFHMIN-NEXT: .LBB12_2:
1408 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1409 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1410 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
1411 ; RV32IZFHMIN-NEXT: ret
1412 ;
1413 ; RV64IZFHMIN-LABEL: test_ceil_ui8:
1414 ; RV64IZFHMIN: # %bb.0:
1415 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1416 ; RV64IZFHMIN-NEXT: lui a0, 307200
1417 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
1418 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
1419 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
1420 ; RV64IZFHMIN-NEXT: beqz a0, .LBB12_2
1421 ; RV64IZFHMIN-NEXT: # %bb.1:
1422 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1423 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1424 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1425 ; RV64IZFHMIN-NEXT: .LBB12_2:
1426 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1427 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1428 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
1429 ; RV64IZFHMIN-NEXT: ret
1430 ;
1431 ; RV32IZHINXMIN-LABEL: test_ceil_ui8:
1432 ; RV32IZHINXMIN: # %bb.0:
1433 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1434 ; RV32IZHINXMIN-NEXT: lui a1, 307200
1435 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
1436 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
1437 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB12_2
1438 ; RV32IZHINXMIN-NEXT: # %bb.1:
1439 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1440 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1441 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1442 ; RV32IZHINXMIN-NEXT: .LBB12_2:
1443 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
1444 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1445 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
1446 ; RV32IZHINXMIN-NEXT: ret
1447 ;
1448 ; RV64IZHINXMIN-LABEL: test_ceil_ui8:
1449 ; RV64IZHINXMIN: # %bb.0:
1450 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1451 ; RV64IZHINXMIN-NEXT: lui a1, 307200
1452 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
1453 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
1454 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB12_2
1455 ; RV64IZHINXMIN-NEXT: # %bb.1:
1456 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1457 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1458 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1459 ; RV64IZHINXMIN-NEXT: .LBB12_2:
1460 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
1461 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1462 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
1463 ; RV64IZHINXMIN-NEXT: ret
1464 %a = call half @llvm.ceil.f16(half %x)
1465 %b = fptoui half %a to i8
1466 ret i8 %b
1467 }
1469 define zeroext i16 @test_ceil_ui16(half %x) {
1470 ; RV32IZFH-LABEL: test_ceil_ui16:
1471 ; RV32IZFH: # %bb.0:
1472 ; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rup
1473 ; RV32IZFH-NEXT: ret
1474 ;
1475 ; RV64IZFH-LABEL: test_ceil_ui16:
1476 ; RV64IZFH: # %bb.0:
1477 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rup
1478 ; RV64IZFH-NEXT: ret
1479 ;
1480 ; RV32IZHINX-LABEL: test_ceil_ui16:
1481 ; RV32IZHINX: # %bb.0:
1482 ; RV32IZHINX-NEXT: li a1, 25
1483 ; RV32IZHINX-NEXT: slli a1, a1, 10
1484 ; RV32IZHINX-NEXT: fabs.h a2, a0
1485 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
1486 ; RV32IZHINX-NEXT: beqz a1, .LBB13_2
1487 ; RV32IZHINX-NEXT: # %bb.1:
1488 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rup
1489 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rup
1490 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
1491 ; RV32IZHINX-NEXT: .LBB13_2:
1492 ; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
1493 ; RV32IZHINX-NEXT: ret
1494 ;
1495 ; RV64IZHINX-LABEL: test_ceil_ui16:
1496 ; RV64IZHINX: # %bb.0:
1497 ; RV64IZHINX-NEXT: li a1, 25
1498 ; RV64IZHINX-NEXT: slli a1, a1, 10
1499 ; RV64IZHINX-NEXT: fabs.h a2, a0
1500 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
1501 ; RV64IZHINX-NEXT: beqz a1, .LBB13_2
1502 ; RV64IZHINX-NEXT: # %bb.1:
1503 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rup
1504 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rup
1505 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
1506 ; RV64IZHINX-NEXT: .LBB13_2:
1507 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
1508 ; RV64IZHINX-NEXT: ret
1509 ;
1510 ; RV32IZFHMIN-LABEL: test_ceil_ui16:
1511 ; RV32IZFHMIN: # %bb.0:
1512 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1513 ; RV32IZFHMIN-NEXT: lui a0, 307200
1514 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
1515 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
1516 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
1517 ; RV32IZFHMIN-NEXT: beqz a0, .LBB13_2
1518 ; RV32IZFHMIN-NEXT: # %bb.1:
1519 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1520 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1521 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1522 ; RV32IZFHMIN-NEXT: .LBB13_2:
1523 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1524 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1525 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
1526 ; RV32IZFHMIN-NEXT: ret
1527 ;
1528 ; RV64IZFHMIN-LABEL: test_ceil_ui16:
1529 ; RV64IZFHMIN: # %bb.0:
1530 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1531 ; RV64IZFHMIN-NEXT: lui a0, 307200
1532 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
1533 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
1534 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
1535 ; RV64IZFHMIN-NEXT: beqz a0, .LBB13_2
1536 ; RV64IZFHMIN-NEXT: # %bb.1:
1537 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1538 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1539 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1540 ; RV64IZFHMIN-NEXT: .LBB13_2:
1541 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1542 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1543 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
1544 ; RV64IZFHMIN-NEXT: ret
1545 ;
1546 ; RV32IZHINXMIN-LABEL: test_ceil_ui16:
1547 ; RV32IZHINXMIN: # %bb.0:
1548 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1549 ; RV32IZHINXMIN-NEXT: lui a1, 307200
1550 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
1551 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
1552 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB13_2
1553 ; RV32IZHINXMIN-NEXT: # %bb.1:
1554 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1555 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1556 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1557 ; RV32IZHINXMIN-NEXT: .LBB13_2:
1558 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
1559 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1560 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
1561 ; RV32IZHINXMIN-NEXT: ret
1562 ;
1563 ; RV64IZHINXMIN-LABEL: test_ceil_ui16:
1564 ; RV64IZHINXMIN: # %bb.0:
1565 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1566 ; RV64IZHINXMIN-NEXT: lui a1, 307200
1567 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
1568 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
1569 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB13_2
1570 ; RV64IZHINXMIN-NEXT: # %bb.1:
1571 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1572 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1573 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1574 ; RV64IZHINXMIN-NEXT: .LBB13_2:
1575 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
1576 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1577 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
1578 ; RV64IZHINXMIN-NEXT: ret
1579 %a = call half @llvm.ceil.f16(half %x)
1580 %b = fptoui half %a to i16
1581 ret i16 %b
1582 }
1584 define signext i32 @test_ceil_ui32(half %x) {
1585 ; CHECKIZFH-LABEL: test_ceil_ui32:
1586 ; CHECKIZFH: # %bb.0:
1587 ; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rup
1588 ; CHECKIZFH-NEXT: ret
1589 ;
1590 ; CHECKIZHINX-LABEL: test_ceil_ui32:
1591 ; CHECKIZHINX: # %bb.0:
1592 ; CHECKIZHINX-NEXT: li a1, 25
1593 ; CHECKIZHINX-NEXT: slli a1, a1, 10
1594 ; CHECKIZHINX-NEXT: fabs.h a2, a0
1595 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
1596 ; CHECKIZHINX-NEXT: beqz a1, .LBB14_2
1597 ; CHECKIZHINX-NEXT: # %bb.1:
1598 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rup
1599 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rup
1600 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
1601 ; CHECKIZHINX-NEXT: .LBB14_2:
1602 ; CHECKIZHINX-NEXT: fcvt.wu.h a0, a0, rtz
1603 ; CHECKIZHINX-NEXT: ret
1604 ;
1605 ; CHECKIZFHMIN-LABEL: test_ceil_ui32:
1606 ; CHECKIZFHMIN: # %bb.0:
1607 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
1608 ; CHECKIZFHMIN-NEXT: lui a0, 307200
1609 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
1610 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
1611 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
1612 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB14_2
1613 ; CHECKIZFHMIN-NEXT: # %bb.1:
1614 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1615 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1616 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1617 ; CHECKIZFHMIN-NEXT: .LBB14_2:
1618 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5
1619 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5
1620 ; CHECKIZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
1621 ; CHECKIZFHMIN-NEXT: ret
1622 ;
1623 ; CHECKIZHINXMIN-LABEL: test_ceil_ui32:
1624 ; CHECKIZHINXMIN: # %bb.0:
1625 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
1626 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
1627 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
1628 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
1629 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB14_2
1630 ; CHECKIZHINXMIN-NEXT: # %bb.1:
1631 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1632 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1633 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1634 ; CHECKIZHINXMIN-NEXT: .LBB14_2:
1635 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
1636 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
1637 ; CHECKIZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
1638 ; CHECKIZHINXMIN-NEXT: ret
1639 %a = call half @llvm.ceil.f16(half %x)
1640 %b = fptoui half %a to i32
1641 ret i32 %b
1642 }
1644 define i64 @test_ceil_ui64(half %x) {
1645 ; RV32IZFH-LABEL: test_ceil_ui64:
1646 ; RV32IZFH: # %bb.0:
1647 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI15_0)
1648 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI15_0)(a0)
1649 ; RV32IZFH-NEXT: fabs.h fa4, fa0
1650 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
1651 ; RV32IZFH-NEXT: beqz a0, .LBB15_2
1652 ; RV32IZFH-NEXT: # %bb.1:
1653 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rup
1654 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rup
1655 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
1656 ; RV32IZFH-NEXT: .LBB15_2:
1657 ; RV32IZFH-NEXT: addi sp, sp, -16
1658 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
1659 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1660 ; RV32IZFH-NEXT: .cfi_offset ra, -4
1661 ; RV32IZFH-NEXT: call __fixunshfdi
1662 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1663 ; RV32IZFH-NEXT: .cfi_restore ra
1664 ; RV32IZFH-NEXT: addi sp, sp, 16
1665 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
1666 ; RV32IZFH-NEXT: ret
1667 ;
1668 ; RV64IZFH-LABEL: test_ceil_ui64:
1669 ; RV64IZFH: # %bb.0:
1670 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rup
1671 ; RV64IZFH-NEXT: ret
1672 ;
1673 ; RV32IZHINX-LABEL: test_ceil_ui64:
1674 ; RV32IZHINX: # %bb.0:
1675 ; RV32IZHINX-NEXT: li a1, 25
1676 ; RV32IZHINX-NEXT: slli a1, a1, 10
1677 ; RV32IZHINX-NEXT: fabs.h a2, a0
1678 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
1679 ; RV32IZHINX-NEXT: beqz a1, .LBB15_2
1680 ; RV32IZHINX-NEXT: # %bb.1:
1681 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rup
1682 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rup
1683 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
1684 ; RV32IZHINX-NEXT: .LBB15_2:
1685 ; RV32IZHINX-NEXT: addi sp, sp, -16
1686 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
1687 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1688 ; RV32IZHINX-NEXT: .cfi_offset ra, -4
1689 ; RV32IZHINX-NEXT: call __fixunshfdi
1690 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1691 ; RV32IZHINX-NEXT: .cfi_restore ra
1692 ; RV32IZHINX-NEXT: addi sp, sp, 16
1693 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
1694 ; RV32IZHINX-NEXT: ret
1695 ;
1696 ; RV64IZHINX-LABEL: test_ceil_ui64:
1697 ; RV64IZHINX: # %bb.0:
1698 ; RV64IZHINX-NEXT: li a1, 25
1699 ; RV64IZHINX-NEXT: slli a1, a1, 10
1700 ; RV64IZHINX-NEXT: fabs.h a2, a0
1701 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
1702 ; RV64IZHINX-NEXT: beqz a1, .LBB15_2
1703 ; RV64IZHINX-NEXT: # %bb.1:
1704 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rup
1705 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rup
1706 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
1707 ; RV64IZHINX-NEXT: .LBB15_2:
1708 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
1709 ; RV64IZHINX-NEXT: ret
1710 ;
1711 ; RV32IZFHMIN-LABEL: test_ceil_ui64:
1712 ; RV32IZFHMIN: # %bb.0:
1713 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1714 ; RV32IZFHMIN-NEXT: lui a0, 307200
1715 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
1716 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
1717 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
1718 ; RV32IZFHMIN-NEXT: beqz a0, .LBB15_2
1719 ; RV32IZFHMIN-NEXT: # %bb.1:
1720 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1721 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1722 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1723 ; RV32IZFHMIN-NEXT: .LBB15_2:
1724 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
1725 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
1726 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1727 ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
1728 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
1729 ; RV32IZFHMIN-NEXT: call __fixunshfdi
1730 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1731 ; RV32IZFHMIN-NEXT: .cfi_restore ra
1732 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
1733 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
1734 ; RV32IZFHMIN-NEXT: ret
1735 ;
1736 ; RV64IZFHMIN-LABEL: test_ceil_ui64:
1737 ; RV64IZFHMIN: # %bb.0:
1738 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1739 ; RV64IZFHMIN-NEXT: lui a0, 307200
1740 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
1741 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
1742 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
1743 ; RV64IZFHMIN-NEXT: beqz a0, .LBB15_2
1744 ; RV64IZFHMIN-NEXT: # %bb.1:
1745 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1746 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1747 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1748 ; RV64IZFHMIN-NEXT: .LBB15_2:
1749 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1750 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1751 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
1752 ; RV64IZFHMIN-NEXT: ret
1753 ;
1754 ; RV32IZHINXMIN-LABEL: test_ceil_ui64:
1755 ; RV32IZHINXMIN: # %bb.0:
1756 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1757 ; RV32IZHINXMIN-NEXT: lui a1, 307200
1758 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
1759 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
1760 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB15_2
1761 ; RV32IZHINXMIN-NEXT: # %bb.1:
1762 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1763 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1764 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1765 ; RV32IZHINXMIN-NEXT: .LBB15_2:
1766 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
1767 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
1768 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1769 ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
1770 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
1771 ; RV32IZHINXMIN-NEXT: call __fixunshfdi
1772 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1773 ; RV32IZHINXMIN-NEXT: .cfi_restore ra
1774 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
1775 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
1776 ; RV32IZHINXMIN-NEXT: ret
1777 ;
1778 ; RV64IZHINXMIN-LABEL: test_ceil_ui64:
1779 ; RV64IZHINXMIN: # %bb.0:
1780 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1781 ; RV64IZHINXMIN-NEXT: lui a1, 307200
1782 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
1783 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
1784 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB15_2
1785 ; RV64IZHINXMIN-NEXT: # %bb.1:
1786 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1787 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1788 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1789 ; RV64IZHINXMIN-NEXT: .LBB15_2:
1790 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
1791 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1792 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
1793 ; RV64IZHINXMIN-NEXT: ret
1794 %a = call half @llvm.ceil.f16(half %x)
1795 %b = fptoui half %a to i64
1796 ret i64 %b
1797 }
1799 define signext i8 @test_trunc_si8(half %x) {
1800 ; RV32IZFH-LABEL: test_trunc_si8:
1801 ; RV32IZFH: # %bb.0:
1802 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
1803 ; RV32IZFH-NEXT: ret
1804 ;
1805 ; RV64IZFH-LABEL: test_trunc_si8:
1806 ; RV64IZFH: # %bb.0:
1807 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
1808 ; RV64IZFH-NEXT: ret
1809 ;
1810 ; RV32IZHINX-LABEL: test_trunc_si8:
1811 ; RV32IZHINX: # %bb.0:
1812 ; RV32IZHINX-NEXT: li a1, 25
1813 ; RV32IZHINX-NEXT: slli a1, a1, 10
1814 ; RV32IZHINX-NEXT: fabs.h a2, a0
1815 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
1816 ; RV32IZHINX-NEXT: beqz a1, .LBB16_2
1817 ; RV32IZHINX-NEXT: # %bb.1:
1818 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rtz
1819 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rtz
1820 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
1821 ; RV32IZHINX-NEXT: .LBB16_2:
1822 ; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
1823 ; RV32IZHINX-NEXT: ret
1824 ;
1825 ; RV64IZHINX-LABEL: test_trunc_si8:
1826 ; RV64IZHINX: # %bb.0:
1827 ; RV64IZHINX-NEXT: li a1, 25
1828 ; RV64IZHINX-NEXT: slli a1, a1, 10
1829 ; RV64IZHINX-NEXT: fabs.h a2, a0
1830 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
1831 ; RV64IZHINX-NEXT: beqz a1, .LBB16_2
1832 ; RV64IZHINX-NEXT: # %bb.1:
1833 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rtz
1834 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rtz
1835 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
1836 ; RV64IZHINX-NEXT: .LBB16_2:
1837 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
1838 ; RV64IZHINX-NEXT: ret
1839 ;
1840 ; RV32IZFHMIN-LABEL: test_trunc_si8:
1841 ; RV32IZFHMIN: # %bb.0:
1842 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1843 ; RV32IZFHMIN-NEXT: lui a0, 307200
1844 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
1845 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
1846 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
1847 ; RV32IZFHMIN-NEXT: beqz a0, .LBB16_2
1848 ; RV32IZFHMIN-NEXT: # %bb.1:
1849 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
1850 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
1851 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1852 ; RV32IZFHMIN-NEXT: .LBB16_2:
1853 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1854 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1855 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
1856 ; RV32IZFHMIN-NEXT: ret
1857 ;
1858 ; RV64IZFHMIN-LABEL: test_trunc_si8:
1859 ; RV64IZFHMIN: # %bb.0:
1860 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1861 ; RV64IZFHMIN-NEXT: lui a0, 307200
1862 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
1863 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
1864 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
1865 ; RV64IZFHMIN-NEXT: beqz a0, .LBB16_2
1866 ; RV64IZFHMIN-NEXT: # %bb.1:
1867 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
1868 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
1869 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1870 ; RV64IZFHMIN-NEXT: .LBB16_2:
1871 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1872 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1873 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
1874 ; RV64IZFHMIN-NEXT: ret
1875 ;
1876 ; RV32IZHINXMIN-LABEL: test_trunc_si8:
1877 ; RV32IZHINXMIN: # %bb.0:
1878 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1879 ; RV32IZHINXMIN-NEXT: lui a1, 307200
1880 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
1881 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
1882 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB16_2
1883 ; RV32IZHINXMIN-NEXT: # %bb.1:
1884 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
1885 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
1886 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1887 ; RV32IZHINXMIN-NEXT: .LBB16_2:
1888 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
1889 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1890 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
1891 ; RV32IZHINXMIN-NEXT: ret
1892 ;
1893 ; RV64IZHINXMIN-LABEL: test_trunc_si8:
1894 ; RV64IZHINXMIN: # %bb.0:
1895 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1896 ; RV64IZHINXMIN-NEXT: lui a1, 307200
1897 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
1898 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
1899 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB16_2
1900 ; RV64IZHINXMIN-NEXT: # %bb.1:
1901 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
1902 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
1903 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1904 ; RV64IZHINXMIN-NEXT: .LBB16_2:
1905 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
1906 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1907 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
1908 ; RV64IZHINXMIN-NEXT: ret
1909 %a = call half @llvm.trunc.f16(half %x)
1910 %b = fptosi half %a to i8
1911 ret i8 %b
1912 }
1914 define signext i16 @test_trunc_si16(half %x) {
1915 ; RV32IZFH-LABEL: test_trunc_si16:
1916 ; RV32IZFH: # %bb.0:
1917 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
1918 ; RV32IZFH-NEXT: ret
1919 ;
1920 ; RV64IZFH-LABEL: test_trunc_si16:
1921 ; RV64IZFH: # %bb.0:
1922 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
1923 ; RV64IZFH-NEXT: ret
1924 ;
1925 ; RV32IZHINX-LABEL: test_trunc_si16:
1926 ; RV32IZHINX: # %bb.0:
1927 ; RV32IZHINX-NEXT: li a1, 25
1928 ; RV32IZHINX-NEXT: slli a1, a1, 10
1929 ; RV32IZHINX-NEXT: fabs.h a2, a0
1930 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
1931 ; RV32IZHINX-NEXT: beqz a1, .LBB17_2
1932 ; RV32IZHINX-NEXT: # %bb.1:
1933 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rtz
1934 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rtz
1935 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
1936 ; RV32IZHINX-NEXT: .LBB17_2:
1937 ; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
1938 ; RV32IZHINX-NEXT: ret
1939 ;
1940 ; RV64IZHINX-LABEL: test_trunc_si16:
1941 ; RV64IZHINX: # %bb.0:
1942 ; RV64IZHINX-NEXT: li a1, 25
1943 ; RV64IZHINX-NEXT: slli a1, a1, 10
1944 ; RV64IZHINX-NEXT: fabs.h a2, a0
1945 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
1946 ; RV64IZHINX-NEXT: beqz a1, .LBB17_2
1947 ; RV64IZHINX-NEXT: # %bb.1:
1948 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rtz
1949 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rtz
1950 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
1951 ; RV64IZHINX-NEXT: .LBB17_2:
1952 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
1953 ; RV64IZHINX-NEXT: ret
1954 ;
1955 ; RV32IZFHMIN-LABEL: test_trunc_si16:
1956 ; RV32IZFHMIN: # %bb.0:
1957 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1958 ; RV32IZFHMIN-NEXT: lui a0, 307200
1959 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
1960 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
1961 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
1962 ; RV32IZFHMIN-NEXT: beqz a0, .LBB17_2
1963 ; RV32IZFHMIN-NEXT: # %bb.1:
1964 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
1965 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
1966 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1967 ; RV32IZFHMIN-NEXT: .LBB17_2:
1968 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1969 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1970 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
1971 ; RV32IZFHMIN-NEXT: ret
1972 ;
1973 ; RV64IZFHMIN-LABEL: test_trunc_si16:
1974 ; RV64IZFHMIN: # %bb.0:
1975 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1976 ; RV64IZFHMIN-NEXT: lui a0, 307200
1977 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
1978 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
1979 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
1980 ; RV64IZFHMIN-NEXT: beqz a0, .LBB17_2
1981 ; RV64IZFHMIN-NEXT: # %bb.1:
1982 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
1983 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
1984 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1985 ; RV64IZFHMIN-NEXT: .LBB17_2:
1986 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1987 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1988 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
1989 ; RV64IZFHMIN-NEXT: ret
1990 ;
1991 ; RV32IZHINXMIN-LABEL: test_trunc_si16:
1992 ; RV32IZHINXMIN: # %bb.0:
1993 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1994 ; RV32IZHINXMIN-NEXT: lui a1, 307200
1995 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
1996 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
1997 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB17_2
1998 ; RV32IZHINXMIN-NEXT: # %bb.1:
1999 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2000 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
2001 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2002 ; RV32IZHINXMIN-NEXT: .LBB17_2:
2003 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
2004 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2005 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
2006 ; RV32IZHINXMIN-NEXT: ret
2007 ;
2008 ; RV64IZHINXMIN-LABEL: test_trunc_si16:
2009 ; RV64IZHINXMIN: # %bb.0:
2010 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2011 ; RV64IZHINXMIN-NEXT: lui a1, 307200
2012 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
2013 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
2014 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB17_2
2015 ; RV64IZHINXMIN-NEXT: # %bb.1:
2016 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2017 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
2018 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2019 ; RV64IZHINXMIN-NEXT: .LBB17_2:
2020 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
2021 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2022 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
2023 ; RV64IZHINXMIN-NEXT: ret
2024 %a = call half @llvm.trunc.f16(half %x)
2025 %b = fptosi half %a to i16
2026 ret i16 %b
2027 }
2029 define signext i32 @test_trunc_si32(half %x) {
2030 ; CHECKIZFH-LABEL: test_trunc_si32:
2031 ; CHECKIZFH: # %bb.0:
2032 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rtz
2033 ; CHECKIZFH-NEXT: ret
2034 ;
2035 ; CHECKIZHINX-LABEL: test_trunc_si32:
2036 ; CHECKIZHINX: # %bb.0:
2037 ; CHECKIZHINX-NEXT: li a1, 25
2038 ; CHECKIZHINX-NEXT: slli a1, a1, 10
2039 ; CHECKIZHINX-NEXT: fabs.h a2, a0
2040 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
2041 ; CHECKIZHINX-NEXT: beqz a1, .LBB18_2
2042 ; CHECKIZHINX-NEXT: # %bb.1:
2043 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rtz
2044 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rtz
2045 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
2046 ; CHECKIZHINX-NEXT: .LBB18_2:
2047 ; CHECKIZHINX-NEXT: fcvt.w.h a0, a0, rtz
2048 ; CHECKIZHINX-NEXT: ret
2049 ;
2050 ; CHECKIZFHMIN-LABEL: test_trunc_si32:
2051 ; CHECKIZFHMIN: # %bb.0:
2052 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
2053 ; CHECKIZFHMIN-NEXT: lui a0, 307200
2054 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
2055 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
2056 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
2057 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB18_2
2058 ; CHECKIZFHMIN-NEXT: # %bb.1:
2059 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2060 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
2061 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2062 ; CHECKIZFHMIN-NEXT: .LBB18_2:
2063 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5
2064 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5
2065 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2066 ; CHECKIZFHMIN-NEXT: ret
2067 ;
2068 ; CHECKIZHINXMIN-LABEL: test_trunc_si32:
2069 ; CHECKIZHINXMIN: # %bb.0:
2070 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
2071 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
2072 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
2073 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
2074 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB18_2
2075 ; CHECKIZHINXMIN-NEXT: # %bb.1:
2076 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2077 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
2078 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2079 ; CHECKIZHINXMIN-NEXT: .LBB18_2:
2080 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
2081 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
2082 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
2083 ; CHECKIZHINXMIN-NEXT: ret
2084 %a = call half @llvm.trunc.f16(half %x)
2085 %b = fptosi half %a to i32
2086 ret i32 %b
2087 }
2089 define i64 @test_trunc_si64(half %x) {
2090 ; RV32IZFH-LABEL: test_trunc_si64:
2091 ; RV32IZFH: # %bb.0:
2092 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI19_0)
2093 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI19_0)(a0)
2094 ; RV32IZFH-NEXT: fabs.h fa4, fa0
2095 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
2096 ; RV32IZFH-NEXT: beqz a0, .LBB19_2
2097 ; RV32IZFH-NEXT: # %bb.1:
2098 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
2099 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rtz
2100 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
2101 ; RV32IZFH-NEXT: .LBB19_2:
2102 ; RV32IZFH-NEXT: addi sp, sp, -16
2103 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
2104 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2105 ; RV32IZFH-NEXT: .cfi_offset ra, -4
2106 ; RV32IZFH-NEXT: call __fixhfdi
2107 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2108 ; RV32IZFH-NEXT: .cfi_restore ra
2109 ; RV32IZFH-NEXT: addi sp, sp, 16
2110 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
2111 ; RV32IZFH-NEXT: ret
2112 ;
2113 ; RV64IZFH-LABEL: test_trunc_si64:
2114 ; RV64IZFH: # %bb.0:
2115 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
2116 ; RV64IZFH-NEXT: ret
2117 ;
2118 ; RV32IZHINX-LABEL: test_trunc_si64:
2119 ; RV32IZHINX: # %bb.0:
2120 ; RV32IZHINX-NEXT: li a1, 25
2121 ; RV32IZHINX-NEXT: slli a1, a1, 10
2122 ; RV32IZHINX-NEXT: fabs.h a2, a0
2123 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
2124 ; RV32IZHINX-NEXT: beqz a1, .LBB19_2
2125 ; RV32IZHINX-NEXT: # %bb.1:
2126 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rtz
2127 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rtz
2128 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
2129 ; RV32IZHINX-NEXT: .LBB19_2:
2130 ; RV32IZHINX-NEXT: addi sp, sp, -16
2131 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
2132 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2133 ; RV32IZHINX-NEXT: .cfi_offset ra, -4
2134 ; RV32IZHINX-NEXT: call __fixhfdi
2135 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2136 ; RV32IZHINX-NEXT: .cfi_restore ra
2137 ; RV32IZHINX-NEXT: addi sp, sp, 16
2138 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
2139 ; RV32IZHINX-NEXT: ret
2140 ;
2141 ; RV64IZHINX-LABEL: test_trunc_si64:
2142 ; RV64IZHINX: # %bb.0:
2143 ; RV64IZHINX-NEXT: li a1, 25
2144 ; RV64IZHINX-NEXT: slli a1, a1, 10
2145 ; RV64IZHINX-NEXT: fabs.h a2, a0
2146 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
2147 ; RV64IZHINX-NEXT: beqz a1, .LBB19_2
2148 ; RV64IZHINX-NEXT: # %bb.1:
2149 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rtz
2150 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rtz
2151 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
2152 ; RV64IZHINX-NEXT: .LBB19_2:
2153 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
2154 ; RV64IZHINX-NEXT: ret
2155 ;
2156 ; RV32IZFHMIN-LABEL: test_trunc_si64:
2157 ; RV32IZFHMIN: # %bb.0:
2158 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2159 ; RV32IZFHMIN-NEXT: lui a0, 307200
2160 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
2161 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
2162 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
2163 ; RV32IZFHMIN-NEXT: beqz a0, .LBB19_2
2164 ; RV32IZFHMIN-NEXT: # %bb.1:
2165 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2166 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
2167 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2168 ; RV32IZFHMIN-NEXT: .LBB19_2:
2169 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
2170 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
2171 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2172 ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
2173 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
2174 ; RV32IZFHMIN-NEXT: call __fixhfdi
2175 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2176 ; RV32IZFHMIN-NEXT: .cfi_restore ra
2177 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
2178 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
2179 ; RV32IZFHMIN-NEXT: ret
2180 ;
2181 ; RV64IZFHMIN-LABEL: test_trunc_si64:
2182 ; RV64IZFHMIN: # %bb.0:
2183 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2184 ; RV64IZFHMIN-NEXT: lui a0, 307200
2185 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
2186 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
2187 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
2188 ; RV64IZFHMIN-NEXT: beqz a0, .LBB19_2
2189 ; RV64IZFHMIN-NEXT: # %bb.1:
2190 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2191 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
2192 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2193 ; RV64IZFHMIN-NEXT: .LBB19_2:
2194 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2195 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
2196 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
2197 ; RV64IZFHMIN-NEXT: ret
2198 ;
2199 ; RV32IZHINXMIN-LABEL: test_trunc_si64:
2200 ; RV32IZHINXMIN: # %bb.0:
2201 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2202 ; RV32IZHINXMIN-NEXT: lui a1, 307200
2203 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
2204 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
2205 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB19_2
2206 ; RV32IZHINXMIN-NEXT: # %bb.1:
2207 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2208 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
2209 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2210 ; RV32IZHINXMIN-NEXT: .LBB19_2:
2211 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
2212 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
2213 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2214 ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
2215 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
2216 ; RV32IZHINXMIN-NEXT: call __fixhfdi
2217 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2218 ; RV32IZHINXMIN-NEXT: .cfi_restore ra
2219 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
2220 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
2221 ; RV32IZHINXMIN-NEXT: ret
2222 ;
2223 ; RV64IZHINXMIN-LABEL: test_trunc_si64:
2224 ; RV64IZHINXMIN: # %bb.0:
2225 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2226 ; RV64IZHINXMIN-NEXT: lui a1, 307200
2227 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
2228 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
2229 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB19_2
2230 ; RV64IZHINXMIN-NEXT: # %bb.1:
2231 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2232 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
2233 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2234 ; RV64IZHINXMIN-NEXT: .LBB19_2:
2235 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
2236 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2237 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
2238 ; RV64IZHINXMIN-NEXT: ret
2239 %a = call half @llvm.trunc.f16(half %x)
2240 %b = fptosi half %a to i64
2241 ret i64 %b
2242 }
2244 define zeroext i8 @test_trunc_ui8(half %x) {
2245 ; RV32IZFH-LABEL: test_trunc_ui8:
2246 ; RV32IZFH: # %bb.0:
2247 ; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
2248 ; RV32IZFH-NEXT: ret
2249 ;
2250 ; RV64IZFH-LABEL: test_trunc_ui8:
2251 ; RV64IZFH: # %bb.0:
2252 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
2253 ; RV64IZFH-NEXT: ret
2254 ;
2255 ; RV32IZHINX-LABEL: test_trunc_ui8:
2256 ; RV32IZHINX: # %bb.0:
2257 ; RV32IZHINX-NEXT: li a1, 25
2258 ; RV32IZHINX-NEXT: slli a1, a1, 10
2259 ; RV32IZHINX-NEXT: fabs.h a2, a0
2260 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
2261 ; RV32IZHINX-NEXT: beqz a1, .LBB20_2
2262 ; RV32IZHINX-NEXT: # %bb.1:
2263 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rtz
2264 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rtz
2265 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
2266 ; RV32IZHINX-NEXT: .LBB20_2:
2267 ; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
2268 ; RV32IZHINX-NEXT: ret
2269 ;
2270 ; RV64IZHINX-LABEL: test_trunc_ui8:
2271 ; RV64IZHINX: # %bb.0:
2272 ; RV64IZHINX-NEXT: li a1, 25
2273 ; RV64IZHINX-NEXT: slli a1, a1, 10
2274 ; RV64IZHINX-NEXT: fabs.h a2, a0
2275 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
2276 ; RV64IZHINX-NEXT: beqz a1, .LBB20_2
2277 ; RV64IZHINX-NEXT: # %bb.1:
2278 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rtz
2279 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rtz
2280 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
2281 ; RV64IZHINX-NEXT: .LBB20_2:
2282 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
2283 ; RV64IZHINX-NEXT: ret
2284 ;
2285 ; RV32IZFHMIN-LABEL: test_trunc_ui8:
2286 ; RV32IZFHMIN: # %bb.0:
2287 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2288 ; RV32IZFHMIN-NEXT: lui a0, 307200
2289 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
2290 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
2291 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
2292 ; RV32IZFHMIN-NEXT: beqz a0, .LBB20_2
2293 ; RV32IZFHMIN-NEXT: # %bb.1:
2294 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2295 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
2296 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2297 ; RV32IZFHMIN-NEXT: .LBB20_2:
2298 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2299 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
2300 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2301 ; RV32IZFHMIN-NEXT: ret
2302 ;
2303 ; RV64IZFHMIN-LABEL: test_trunc_ui8:
2304 ; RV64IZFHMIN: # %bb.0:
2305 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2306 ; RV64IZFHMIN-NEXT: lui a0, 307200
2307 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
2308 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
2309 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
2310 ; RV64IZFHMIN-NEXT: beqz a0, .LBB20_2
2311 ; RV64IZFHMIN-NEXT: # %bb.1:
2312 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2313 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
2314 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2315 ; RV64IZFHMIN-NEXT: .LBB20_2:
2316 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2317 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
2318 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
2319 ; RV64IZFHMIN-NEXT: ret
2320 ;
2321 ; RV32IZHINXMIN-LABEL: test_trunc_ui8:
2322 ; RV32IZHINXMIN: # %bb.0:
2323 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2324 ; RV32IZHINXMIN-NEXT: lui a1, 307200
2325 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
2326 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
2327 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB20_2
2328 ; RV32IZHINXMIN-NEXT: # %bb.1:
2329 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2330 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
2331 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2332 ; RV32IZHINXMIN-NEXT: .LBB20_2:
2333 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
2334 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2335 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
2336 ; RV32IZHINXMIN-NEXT: ret
2337 ;
2338 ; RV64IZHINXMIN-LABEL: test_trunc_ui8:
2339 ; RV64IZHINXMIN: # %bb.0:
2340 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2341 ; RV64IZHINXMIN-NEXT: lui a1, 307200
2342 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
2343 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
2344 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB20_2
2345 ; RV64IZHINXMIN-NEXT: # %bb.1:
2346 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2347 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
2348 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2349 ; RV64IZHINXMIN-NEXT: .LBB20_2:
2350 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
2351 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2352 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
2353 ; RV64IZHINXMIN-NEXT: ret
2354 %a = call half @llvm.trunc.f16(half %x)
2355 %b = fptoui half %a to i8
2356 ret i8 %b
2357 }
2359 define zeroext i16 @test_trunc_ui16(half %x) {
2360 ; RV32IZFH-LABEL: test_trunc_ui16:
2361 ; RV32IZFH: # %bb.0:
2362 ; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
2363 ; RV32IZFH-NEXT: ret
2364 ;
2365 ; RV64IZFH-LABEL: test_trunc_ui16:
2366 ; RV64IZFH: # %bb.0:
2367 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
2368 ; RV64IZFH-NEXT: ret
2369 ;
2370 ; RV32IZHINX-LABEL: test_trunc_ui16:
2371 ; RV32IZHINX: # %bb.0:
2372 ; RV32IZHINX-NEXT: li a1, 25
2373 ; RV32IZHINX-NEXT: slli a1, a1, 10
2374 ; RV32IZHINX-NEXT: fabs.h a2, a0
2375 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
2376 ; RV32IZHINX-NEXT: beqz a1, .LBB21_2
2377 ; RV32IZHINX-NEXT: # %bb.1:
2378 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rtz
2379 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rtz
2380 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
2381 ; RV32IZHINX-NEXT: .LBB21_2:
2382 ; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
2383 ; RV32IZHINX-NEXT: ret
2384 ;
2385 ; RV64IZHINX-LABEL: test_trunc_ui16:
2386 ; RV64IZHINX: # %bb.0:
2387 ; RV64IZHINX-NEXT: li a1, 25
2388 ; RV64IZHINX-NEXT: slli a1, a1, 10
2389 ; RV64IZHINX-NEXT: fabs.h a2, a0
2390 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
2391 ; RV64IZHINX-NEXT: beqz a1, .LBB21_2
2392 ; RV64IZHINX-NEXT: # %bb.1:
2393 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rtz
2394 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rtz
2395 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
2396 ; RV64IZHINX-NEXT: .LBB21_2:
2397 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
2398 ; RV64IZHINX-NEXT: ret
2399 ;
2400 ; RV32IZFHMIN-LABEL: test_trunc_ui16:
2401 ; RV32IZFHMIN: # %bb.0:
2402 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2403 ; RV32IZFHMIN-NEXT: lui a0, 307200
2404 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
2405 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
2406 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
2407 ; RV32IZFHMIN-NEXT: beqz a0, .LBB21_2
2408 ; RV32IZFHMIN-NEXT: # %bb.1:
2409 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2410 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
2411 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2412 ; RV32IZFHMIN-NEXT: .LBB21_2:
2413 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2414 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
2415 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2416 ; RV32IZFHMIN-NEXT: ret
2417 ;
2418 ; RV64IZFHMIN-LABEL: test_trunc_ui16:
2419 ; RV64IZFHMIN: # %bb.0:
2420 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2421 ; RV64IZFHMIN-NEXT: lui a0, 307200
2422 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
2423 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
2424 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
2425 ; RV64IZFHMIN-NEXT: beqz a0, .LBB21_2
2426 ; RV64IZFHMIN-NEXT: # %bb.1:
2427 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2428 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
2429 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2430 ; RV64IZFHMIN-NEXT: .LBB21_2:
2431 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2432 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
2433 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
2434 ; RV64IZFHMIN-NEXT: ret
2435 ;
2436 ; RV32IZHINXMIN-LABEL: test_trunc_ui16:
2437 ; RV32IZHINXMIN: # %bb.0:
2438 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2439 ; RV32IZHINXMIN-NEXT: lui a1, 307200
2440 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
2441 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
2442 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB21_2
2443 ; RV32IZHINXMIN-NEXT: # %bb.1:
2444 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2445 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
2446 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2447 ; RV32IZHINXMIN-NEXT: .LBB21_2:
2448 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
2449 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2450 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
2451 ; RV32IZHINXMIN-NEXT: ret
2452 ;
2453 ; RV64IZHINXMIN-LABEL: test_trunc_ui16:
2454 ; RV64IZHINXMIN: # %bb.0:
2455 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2456 ; RV64IZHINXMIN-NEXT: lui a1, 307200
2457 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
2458 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
2459 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB21_2
2460 ; RV64IZHINXMIN-NEXT: # %bb.1:
2461 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2462 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
2463 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2464 ; RV64IZHINXMIN-NEXT: .LBB21_2:
2465 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
2466 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2467 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
2468 ; RV64IZHINXMIN-NEXT: ret
2469 %a = call half @llvm.trunc.f16(half %x)
2470 %b = fptoui half %a to i16
2471 ret i16 %b
2472 }
2474 define signext i32 @test_trunc_ui32(half %x) {
2475 ; CHECKIZFH-LABEL: test_trunc_ui32:
2476 ; CHECKIZFH: # %bb.0:
2477 ; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rtz
2478 ; CHECKIZFH-NEXT: ret
2479 ;
2480 ; CHECKIZHINX-LABEL: test_trunc_ui32:
2481 ; CHECKIZHINX: # %bb.0:
2482 ; CHECKIZHINX-NEXT: li a1, 25
2483 ; CHECKIZHINX-NEXT: slli a1, a1, 10
2484 ; CHECKIZHINX-NEXT: fabs.h a2, a0
2485 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
2486 ; CHECKIZHINX-NEXT: beqz a1, .LBB22_2
2487 ; CHECKIZHINX-NEXT: # %bb.1:
2488 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rtz
2489 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rtz
2490 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
2491 ; CHECKIZHINX-NEXT: .LBB22_2:
2492 ; CHECKIZHINX-NEXT: fcvt.wu.h a0, a0, rtz
2493 ; CHECKIZHINX-NEXT: ret
2494 ;
2495 ; CHECKIZFHMIN-LABEL: test_trunc_ui32:
2496 ; CHECKIZFHMIN: # %bb.0:
2497 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
2498 ; CHECKIZFHMIN-NEXT: lui a0, 307200
2499 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
2500 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
2501 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
2502 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB22_2
2503 ; CHECKIZFHMIN-NEXT: # %bb.1:
2504 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2505 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
2506 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2507 ; CHECKIZFHMIN-NEXT: .LBB22_2:
2508 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5
2509 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5
2510 ; CHECKIZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
2511 ; CHECKIZFHMIN-NEXT: ret
2512 ;
2513 ; CHECKIZHINXMIN-LABEL: test_trunc_ui32:
2514 ; CHECKIZHINXMIN: # %bb.0:
2515 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
2516 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
2517 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
2518 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
2519 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB22_2
2520 ; CHECKIZHINXMIN-NEXT: # %bb.1:
2521 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2522 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
2523 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2524 ; CHECKIZHINXMIN-NEXT: .LBB22_2:
2525 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
2526 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
2527 ; CHECKIZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
2528 ; CHECKIZHINXMIN-NEXT: ret
2529 %a = call half @llvm.trunc.f16(half %x)
2530 %b = fptoui half %a to i32
2531 ret i32 %b
2532 }
2534 define i64 @test_trunc_ui64(half %x) {
2535 ; RV32IZFH-LABEL: test_trunc_ui64:
2536 ; RV32IZFH: # %bb.0:
2537 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI23_0)
2538 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI23_0)(a0)
2539 ; RV32IZFH-NEXT: fabs.h fa4, fa0
2540 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
2541 ; RV32IZFH-NEXT: beqz a0, .LBB23_2
2542 ; RV32IZFH-NEXT: # %bb.1:
2543 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
2544 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rtz
2545 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
2546 ; RV32IZFH-NEXT: .LBB23_2:
2547 ; RV32IZFH-NEXT: addi sp, sp, -16
2548 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
2549 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2550 ; RV32IZFH-NEXT: .cfi_offset ra, -4
2551 ; RV32IZFH-NEXT: call __fixunshfdi
2552 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2553 ; RV32IZFH-NEXT: .cfi_restore ra
2554 ; RV32IZFH-NEXT: addi sp, sp, 16
2555 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
2556 ; RV32IZFH-NEXT: ret
2557 ;
2558 ; RV64IZFH-LABEL: test_trunc_ui64:
2559 ; RV64IZFH: # %bb.0:
2560 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
2561 ; RV64IZFH-NEXT: ret
2562 ;
2563 ; RV32IZHINX-LABEL: test_trunc_ui64:
2564 ; RV32IZHINX: # %bb.0:
2565 ; RV32IZHINX-NEXT: li a1, 25
2566 ; RV32IZHINX-NEXT: slli a1, a1, 10
2567 ; RV32IZHINX-NEXT: fabs.h a2, a0
2568 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
2569 ; RV32IZHINX-NEXT: beqz a1, .LBB23_2
2570 ; RV32IZHINX-NEXT: # %bb.1:
2571 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rtz
2572 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rtz
2573 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
2574 ; RV32IZHINX-NEXT: .LBB23_2:
2575 ; RV32IZHINX-NEXT: addi sp, sp, -16
2576 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
2577 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2578 ; RV32IZHINX-NEXT: .cfi_offset ra, -4
2579 ; RV32IZHINX-NEXT: call __fixunshfdi
2580 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2581 ; RV32IZHINX-NEXT: .cfi_restore ra
2582 ; RV32IZHINX-NEXT: addi sp, sp, 16
2583 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
2584 ; RV32IZHINX-NEXT: ret
2585 ;
2586 ; RV64IZHINX-LABEL: test_trunc_ui64:
2587 ; RV64IZHINX: # %bb.0:
2588 ; RV64IZHINX-NEXT: li a1, 25
2589 ; RV64IZHINX-NEXT: slli a1, a1, 10
2590 ; RV64IZHINX-NEXT: fabs.h a2, a0
2591 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
2592 ; RV64IZHINX-NEXT: beqz a1, .LBB23_2
2593 ; RV64IZHINX-NEXT: # %bb.1:
2594 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rtz
2595 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rtz
2596 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
2597 ; RV64IZHINX-NEXT: .LBB23_2:
2598 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
2599 ; RV64IZHINX-NEXT: ret
2600 ;
2601 ; RV32IZFHMIN-LABEL: test_trunc_ui64:
2602 ; RV32IZFHMIN: # %bb.0:
2603 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2604 ; RV32IZFHMIN-NEXT: lui a0, 307200
2605 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
2606 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
2607 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
2608 ; RV32IZFHMIN-NEXT: beqz a0, .LBB23_2
2609 ; RV32IZFHMIN-NEXT: # %bb.1:
2610 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2611 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
2612 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2613 ; RV32IZFHMIN-NEXT: .LBB23_2:
2614 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
2615 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
2616 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2617 ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
2618 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
2619 ; RV32IZFHMIN-NEXT: call __fixunshfdi
2620 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2621 ; RV32IZFHMIN-NEXT: .cfi_restore ra
2622 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
2623 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
2624 ; RV32IZFHMIN-NEXT: ret
2625 ;
2626 ; RV64IZFHMIN-LABEL: test_trunc_ui64:
2627 ; RV64IZFHMIN: # %bb.0:
2628 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2629 ; RV64IZFHMIN-NEXT: lui a0, 307200
2630 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
2631 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
2632 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
2633 ; RV64IZFHMIN-NEXT: beqz a0, .LBB23_2
2634 ; RV64IZFHMIN-NEXT: # %bb.1:
2635 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2636 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
2637 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2638 ; RV64IZFHMIN-NEXT: .LBB23_2:
2639 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2640 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
2641 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
2642 ; RV64IZFHMIN-NEXT: ret
2643 ;
2644 ; RV32IZHINXMIN-LABEL: test_trunc_ui64:
2645 ; RV32IZHINXMIN: # %bb.0:
2646 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2647 ; RV32IZHINXMIN-NEXT: lui a1, 307200
2648 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
2649 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
2650 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB23_2
2651 ; RV32IZHINXMIN-NEXT: # %bb.1:
2652 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2653 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
2654 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2655 ; RV32IZHINXMIN-NEXT: .LBB23_2:
2656 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
2657 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
2658 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2659 ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
2660 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
2661 ; RV32IZHINXMIN-NEXT: call __fixunshfdi
2662 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2663 ; RV32IZHINXMIN-NEXT: .cfi_restore ra
2664 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
2665 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
2666 ; RV32IZHINXMIN-NEXT: ret
2667 ;
2668 ; RV64IZHINXMIN-LABEL: test_trunc_ui64:
2669 ; RV64IZHINXMIN: # %bb.0:
2670 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2671 ; RV64IZHINXMIN-NEXT: lui a1, 307200
2672 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
2673 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
2674 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB23_2
2675 ; RV64IZHINXMIN-NEXT: # %bb.1:
2676 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2677 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
2678 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2679 ; RV64IZHINXMIN-NEXT: .LBB23_2:
2680 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
2681 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2682 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
2683 ; RV64IZHINXMIN-NEXT: ret
2684 %a = call half @llvm.trunc.f16(half %x)
2685 %b = fptoui half %a to i64
2686 ret i64 %b
2687 }
2689 define signext i8 @test_round_si8(half %x) {
2690 ; RV32IZFH-LABEL: test_round_si8:
2691 ; RV32IZFH: # %bb.0:
2692 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm
2693 ; RV32IZFH-NEXT: ret
2694 ;
2695 ; RV64IZFH-LABEL: test_round_si8:
2696 ; RV64IZFH: # %bb.0:
2697 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rmm
2698 ; RV64IZFH-NEXT: ret
2699 ;
2700 ; RV32IZHINX-LABEL: test_round_si8:
2701 ; RV32IZHINX: # %bb.0:
2702 ; RV32IZHINX-NEXT: li a1, 25
2703 ; RV32IZHINX-NEXT: slli a1, a1, 10
2704 ; RV32IZHINX-NEXT: fabs.h a2, a0
2705 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
2706 ; RV32IZHINX-NEXT: beqz a1, .LBB24_2
2707 ; RV32IZHINX-NEXT: # %bb.1:
2708 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rmm
2709 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rmm
2710 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
2711 ; RV32IZHINX-NEXT: .LBB24_2:
2712 ; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
2713 ; RV32IZHINX-NEXT: ret
2714 ;
2715 ; RV64IZHINX-LABEL: test_round_si8:
2716 ; RV64IZHINX: # %bb.0:
2717 ; RV64IZHINX-NEXT: li a1, 25
2718 ; RV64IZHINX-NEXT: slli a1, a1, 10
2719 ; RV64IZHINX-NEXT: fabs.h a2, a0
2720 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
2721 ; RV64IZHINX-NEXT: beqz a1, .LBB24_2
2722 ; RV64IZHINX-NEXT: # %bb.1:
2723 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rmm
2724 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rmm
2725 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
2726 ; RV64IZHINX-NEXT: .LBB24_2:
2727 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
2728 ; RV64IZHINX-NEXT: ret
2729 ;
2730 ; RV32IZFHMIN-LABEL: test_round_si8:
2731 ; RV32IZFHMIN: # %bb.0:
2732 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2733 ; RV32IZFHMIN-NEXT: lui a0, 307200
2734 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
2735 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
2736 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
2737 ; RV32IZFHMIN-NEXT: beqz a0, .LBB24_2
2738 ; RV32IZFHMIN-NEXT: # %bb.1:
2739 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
2740 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
2741 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2742 ; RV32IZFHMIN-NEXT: .LBB24_2:
2743 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2744 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
2745 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2746 ; RV32IZFHMIN-NEXT: ret
2747 ;
2748 ; RV64IZFHMIN-LABEL: test_round_si8:
2749 ; RV64IZFHMIN: # %bb.0:
2750 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2751 ; RV64IZFHMIN-NEXT: lui a0, 307200
2752 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
2753 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
2754 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
2755 ; RV64IZFHMIN-NEXT: beqz a0, .LBB24_2
2756 ; RV64IZFHMIN-NEXT: # %bb.1:
2757 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
2758 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
2759 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2760 ; RV64IZFHMIN-NEXT: .LBB24_2:
2761 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2762 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
2763 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
2764 ; RV64IZFHMIN-NEXT: ret
2765 ;
2766 ; RV32IZHINXMIN-LABEL: test_round_si8:
2767 ; RV32IZHINXMIN: # %bb.0:
2768 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2769 ; RV32IZHINXMIN-NEXT: lui a1, 307200
2770 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
2771 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
2772 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB24_2
2773 ; RV32IZHINXMIN-NEXT: # %bb.1:
2774 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
2775 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
2776 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2777 ; RV32IZHINXMIN-NEXT: .LBB24_2:
2778 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
2779 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2780 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
2781 ; RV32IZHINXMIN-NEXT: ret
2782 ;
2783 ; RV64IZHINXMIN-LABEL: test_round_si8:
2784 ; RV64IZHINXMIN: # %bb.0:
2785 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2786 ; RV64IZHINXMIN-NEXT: lui a1, 307200
2787 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
2788 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
2789 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB24_2
2790 ; RV64IZHINXMIN-NEXT: # %bb.1:
2791 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
2792 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
2793 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2794 ; RV64IZHINXMIN-NEXT: .LBB24_2:
2795 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
2796 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2797 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
2798 ; RV64IZHINXMIN-NEXT: ret
2799 %a = call half @llvm.round.f16(half %x)
2800 %b = fptosi half %a to i8
2801 ret i8 %b
2802 }
2804 define signext i16 @test_round_si16(half %x) {
2805 ; RV32IZFH-LABEL: test_round_si16:
2806 ; RV32IZFH: # %bb.0:
2807 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm
2808 ; RV32IZFH-NEXT: ret
2809 ;
2810 ; RV64IZFH-LABEL: test_round_si16:
2811 ; RV64IZFH: # %bb.0:
2812 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rmm
2813 ; RV64IZFH-NEXT: ret
2814 ;
2815 ; RV32IZHINX-LABEL: test_round_si16:
2816 ; RV32IZHINX: # %bb.0:
2817 ; RV32IZHINX-NEXT: li a1, 25
2818 ; RV32IZHINX-NEXT: slli a1, a1, 10
2819 ; RV32IZHINX-NEXT: fabs.h a2, a0
2820 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
2821 ; RV32IZHINX-NEXT: beqz a1, .LBB25_2
2822 ; RV32IZHINX-NEXT: # %bb.1:
2823 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rmm
2824 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rmm
2825 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
2826 ; RV32IZHINX-NEXT: .LBB25_2:
2827 ; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
2828 ; RV32IZHINX-NEXT: ret
2829 ;
2830 ; RV64IZHINX-LABEL: test_round_si16:
2831 ; RV64IZHINX: # %bb.0:
2832 ; RV64IZHINX-NEXT: li a1, 25
2833 ; RV64IZHINX-NEXT: slli a1, a1, 10
2834 ; RV64IZHINX-NEXT: fabs.h a2, a0
2835 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
2836 ; RV64IZHINX-NEXT: beqz a1, .LBB25_2
2837 ; RV64IZHINX-NEXT: # %bb.1:
2838 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rmm
2839 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rmm
2840 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
2841 ; RV64IZHINX-NEXT: .LBB25_2:
2842 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
2843 ; RV64IZHINX-NEXT: ret
2844 ;
2845 ; RV32IZFHMIN-LABEL: test_round_si16:
2846 ; RV32IZFHMIN: # %bb.0:
2847 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2848 ; RV32IZFHMIN-NEXT: lui a0, 307200
2849 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
2850 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
2851 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
2852 ; RV32IZFHMIN-NEXT: beqz a0, .LBB25_2
2853 ; RV32IZFHMIN-NEXT: # %bb.1:
2854 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
2855 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
2856 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2857 ; RV32IZFHMIN-NEXT: .LBB25_2:
2858 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2859 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
2860 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2861 ; RV32IZFHMIN-NEXT: ret
2862 ;
2863 ; RV64IZFHMIN-LABEL: test_round_si16:
2864 ; RV64IZFHMIN: # %bb.0:
2865 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2866 ; RV64IZFHMIN-NEXT: lui a0, 307200
2867 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
2868 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
2869 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
2870 ; RV64IZFHMIN-NEXT: beqz a0, .LBB25_2
2871 ; RV64IZFHMIN-NEXT: # %bb.1:
2872 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
2873 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
2874 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2875 ; RV64IZFHMIN-NEXT: .LBB25_2:
2876 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2877 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
2878 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
2879 ; RV64IZFHMIN-NEXT: ret
2880 ;
2881 ; RV32IZHINXMIN-LABEL: test_round_si16:
2882 ; RV32IZHINXMIN: # %bb.0:
2883 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2884 ; RV32IZHINXMIN-NEXT: lui a1, 307200
2885 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
2886 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
2887 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB25_2
2888 ; RV32IZHINXMIN-NEXT: # %bb.1:
2889 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
2890 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
2891 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2892 ; RV32IZHINXMIN-NEXT: .LBB25_2:
2893 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
2894 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2895 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
2896 ; RV32IZHINXMIN-NEXT: ret
2897 ;
2898 ; RV64IZHINXMIN-LABEL: test_round_si16:
2899 ; RV64IZHINXMIN: # %bb.0:
2900 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2901 ; RV64IZHINXMIN-NEXT: lui a1, 307200
2902 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
2903 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
2904 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB25_2
2905 ; RV64IZHINXMIN-NEXT: # %bb.1:
2906 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
2907 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
2908 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2909 ; RV64IZHINXMIN-NEXT: .LBB25_2:
2910 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
2911 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2912 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
2913 ; RV64IZHINXMIN-NEXT: ret
2914 %a = call half @llvm.round.f16(half %x)
2915 %b = fptosi half %a to i16
2916 ret i16 %b
2917 }
2919 define signext i32 @test_round_si32(half %x) {
2920 ; CHECKIZFH-LABEL: test_round_si32:
2921 ; CHECKIZFH: # %bb.0:
2922 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rmm
2923 ; CHECKIZFH-NEXT: ret
2924 ;
2925 ; CHECKIZHINX-LABEL: test_round_si32:
2926 ; CHECKIZHINX: # %bb.0:
2927 ; CHECKIZHINX-NEXT: li a1, 25
2928 ; CHECKIZHINX-NEXT: slli a1, a1, 10
2929 ; CHECKIZHINX-NEXT: fabs.h a2, a0
2930 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
2931 ; CHECKIZHINX-NEXT: beqz a1, .LBB26_2
2932 ; CHECKIZHINX-NEXT: # %bb.1:
2933 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rmm
2934 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rmm
2935 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
2936 ; CHECKIZHINX-NEXT: .LBB26_2:
2937 ; CHECKIZHINX-NEXT: fcvt.w.h a0, a0, rtz
2938 ; CHECKIZHINX-NEXT: ret
2939 ;
2940 ; CHECKIZFHMIN-LABEL: test_round_si32:
2941 ; CHECKIZFHMIN: # %bb.0:
2942 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
2943 ; CHECKIZFHMIN-NEXT: lui a0, 307200
2944 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
2945 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
2946 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
2947 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB26_2
2948 ; CHECKIZFHMIN-NEXT: # %bb.1:
2949 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
2950 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
2951 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2952 ; CHECKIZFHMIN-NEXT: .LBB26_2:
2953 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5
2954 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5
2955 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2956 ; CHECKIZFHMIN-NEXT: ret
2957 ;
2958 ; CHECKIZHINXMIN-LABEL: test_round_si32:
2959 ; CHECKIZHINXMIN: # %bb.0:
2960 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
2961 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
2962 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
2963 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
2964 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB26_2
2965 ; CHECKIZHINXMIN-NEXT: # %bb.1:
2966 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
2967 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
2968 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2969 ; CHECKIZHINXMIN-NEXT: .LBB26_2:
2970 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
2971 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
2972 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
2973 ; CHECKIZHINXMIN-NEXT: ret
2974 %a = call half @llvm.round.f16(half %x)
2975 %b = fptosi half %a to i32
2976 ret i32 %b
2977 }
2979 define i64 @test_round_si64(half %x) {
2980 ; RV32IZFH-LABEL: test_round_si64:
2981 ; RV32IZFH: # %bb.0:
2982 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI27_0)
2983 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI27_0)(a0)
2984 ; RV32IZFH-NEXT: fabs.h fa4, fa0
2985 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
2986 ; RV32IZFH-NEXT: beqz a0, .LBB27_2
2987 ; RV32IZFH-NEXT: # %bb.1:
2988 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm
2989 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rmm
2990 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
2991 ; RV32IZFH-NEXT: .LBB27_2:
2992 ; RV32IZFH-NEXT: addi sp, sp, -16
2993 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
2994 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2995 ; RV32IZFH-NEXT: .cfi_offset ra, -4
2996 ; RV32IZFH-NEXT: call __fixhfdi
2997 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2998 ; RV32IZFH-NEXT: .cfi_restore ra
2999 ; RV32IZFH-NEXT: addi sp, sp, 16
3000 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
3001 ; RV32IZFH-NEXT: ret
3002 ;
3003 ; RV64IZFH-LABEL: test_round_si64:
3004 ; RV64IZFH: # %bb.0:
3005 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rmm
3006 ; RV64IZFH-NEXT: ret
3007 ;
3008 ; RV32IZHINX-LABEL: test_round_si64:
3009 ; RV32IZHINX: # %bb.0:
3010 ; RV32IZHINX-NEXT: li a1, 25
3011 ; RV32IZHINX-NEXT: slli a1, a1, 10
3012 ; RV32IZHINX-NEXT: fabs.h a2, a0
3013 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
3014 ; RV32IZHINX-NEXT: beqz a1, .LBB27_2
3015 ; RV32IZHINX-NEXT: # %bb.1:
3016 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rmm
3017 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rmm
3018 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
3019 ; RV32IZHINX-NEXT: .LBB27_2:
3020 ; RV32IZHINX-NEXT: addi sp, sp, -16
3021 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
3022 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3023 ; RV32IZHINX-NEXT: .cfi_offset ra, -4
3024 ; RV32IZHINX-NEXT: call __fixhfdi
3025 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3026 ; RV32IZHINX-NEXT: .cfi_restore ra
3027 ; RV32IZHINX-NEXT: addi sp, sp, 16
3028 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
3029 ; RV32IZHINX-NEXT: ret
3030 ;
3031 ; RV64IZHINX-LABEL: test_round_si64:
3032 ; RV64IZHINX: # %bb.0:
3033 ; RV64IZHINX-NEXT: li a1, 25
3034 ; RV64IZHINX-NEXT: slli a1, a1, 10
3035 ; RV64IZHINX-NEXT: fabs.h a2, a0
3036 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
3037 ; RV64IZHINX-NEXT: beqz a1, .LBB27_2
3038 ; RV64IZHINX-NEXT: # %bb.1:
3039 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rmm
3040 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rmm
3041 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
3042 ; RV64IZHINX-NEXT: .LBB27_2:
3043 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
3044 ; RV64IZHINX-NEXT: ret
3045 ;
3046 ; RV32IZFHMIN-LABEL: test_round_si64:
3047 ; RV32IZFHMIN: # %bb.0:
3048 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3049 ; RV32IZFHMIN-NEXT: lui a0, 307200
3050 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
3051 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
3052 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
3053 ; RV32IZFHMIN-NEXT: beqz a0, .LBB27_2
3054 ; RV32IZFHMIN-NEXT: # %bb.1:
3055 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
3056 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
3057 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3058 ; RV32IZFHMIN-NEXT: .LBB27_2:
3059 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
3060 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
3061 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3062 ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
3063 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
3064 ; RV32IZFHMIN-NEXT: call __fixhfdi
3065 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3066 ; RV32IZFHMIN-NEXT: .cfi_restore ra
3067 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
3068 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
3069 ; RV32IZFHMIN-NEXT: ret
3070 ;
3071 ; RV64IZFHMIN-LABEL: test_round_si64:
3072 ; RV64IZFHMIN: # %bb.0:
3073 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3074 ; RV64IZFHMIN-NEXT: lui a0, 307200
3075 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
3076 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
3077 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
3078 ; RV64IZFHMIN-NEXT: beqz a0, .LBB27_2
3079 ; RV64IZFHMIN-NEXT: # %bb.1:
3080 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
3081 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
3082 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3083 ; RV64IZFHMIN-NEXT: .LBB27_2:
3084 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3085 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3086 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
3087 ; RV64IZFHMIN-NEXT: ret
3088 ;
3089 ; RV32IZHINXMIN-LABEL: test_round_si64:
3090 ; RV32IZHINXMIN: # %bb.0:
3091 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3092 ; RV32IZHINXMIN-NEXT: lui a1, 307200
3093 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
3094 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
3095 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB27_2
3096 ; RV32IZHINXMIN-NEXT: # %bb.1:
3097 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
3098 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
3099 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3100 ; RV32IZHINXMIN-NEXT: .LBB27_2:
3101 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
3102 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
3103 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3104 ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
3105 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
3106 ; RV32IZHINXMIN-NEXT: call __fixhfdi
3107 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3108 ; RV32IZHINXMIN-NEXT: .cfi_restore ra
3109 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
3110 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
3111 ; RV32IZHINXMIN-NEXT: ret
3112 ;
3113 ; RV64IZHINXMIN-LABEL: test_round_si64:
3114 ; RV64IZHINXMIN: # %bb.0:
3115 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3116 ; RV64IZHINXMIN-NEXT: lui a1, 307200
3117 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
3118 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
3119 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB27_2
3120 ; RV64IZHINXMIN-NEXT: # %bb.1:
3121 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
3122 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
3123 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3124 ; RV64IZHINXMIN-NEXT: .LBB27_2:
3125 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
3126 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3127 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
3128 ; RV64IZHINXMIN-NEXT: ret
3129 %a = call half @llvm.round.f16(half %x)
3130 %b = fptosi half %a to i64
3131 ret i64 %b
3132 }
3134 define zeroext i8 @test_round_ui8(half %x) {
3135 ; RV32IZFH-LABEL: test_round_ui8:
3136 ; RV32IZFH: # %bb.0:
3137 ; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rmm
3138 ; RV32IZFH-NEXT: ret
3139 ;
3140 ; RV64IZFH-LABEL: test_round_ui8:
3141 ; RV64IZFH: # %bb.0:
3142 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rmm
3143 ; RV64IZFH-NEXT: ret
3144 ;
3145 ; RV32IZHINX-LABEL: test_round_ui8:
3146 ; RV32IZHINX: # %bb.0:
3147 ; RV32IZHINX-NEXT: li a1, 25
3148 ; RV32IZHINX-NEXT: slli a1, a1, 10
3149 ; RV32IZHINX-NEXT: fabs.h a2, a0
3150 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
3151 ; RV32IZHINX-NEXT: beqz a1, .LBB28_2
3152 ; RV32IZHINX-NEXT: # %bb.1:
3153 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rmm
3154 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rmm
3155 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
3156 ; RV32IZHINX-NEXT: .LBB28_2:
3157 ; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
3158 ; RV32IZHINX-NEXT: ret
3159 ;
3160 ; RV64IZHINX-LABEL: test_round_ui8:
3161 ; RV64IZHINX: # %bb.0:
3162 ; RV64IZHINX-NEXT: li a1, 25
3163 ; RV64IZHINX-NEXT: slli a1, a1, 10
3164 ; RV64IZHINX-NEXT: fabs.h a2, a0
3165 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
3166 ; RV64IZHINX-NEXT: beqz a1, .LBB28_2
3167 ; RV64IZHINX-NEXT: # %bb.1:
3168 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rmm
3169 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rmm
3170 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
3171 ; RV64IZHINX-NEXT: .LBB28_2:
3172 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
3173 ; RV64IZHINX-NEXT: ret
3174 ;
3175 ; RV32IZFHMIN-LABEL: test_round_ui8:
3176 ; RV32IZFHMIN: # %bb.0:
3177 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3178 ; RV32IZFHMIN-NEXT: lui a0, 307200
3179 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
3180 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
3181 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
3182 ; RV32IZFHMIN-NEXT: beqz a0, .LBB28_2
3183 ; RV32IZFHMIN-NEXT: # %bb.1:
3184 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
3185 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
3186 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3187 ; RV32IZFHMIN-NEXT: .LBB28_2:
3188 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3189 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3190 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
3191 ; RV32IZFHMIN-NEXT: ret
3192 ;
3193 ; RV64IZFHMIN-LABEL: test_round_ui8:
3194 ; RV64IZFHMIN: # %bb.0:
3195 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3196 ; RV64IZFHMIN-NEXT: lui a0, 307200
3197 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
3198 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
3199 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
3200 ; RV64IZFHMIN-NEXT: beqz a0, .LBB28_2
3201 ; RV64IZFHMIN-NEXT: # %bb.1:
3202 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
3203 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
3204 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3205 ; RV64IZFHMIN-NEXT: .LBB28_2:
3206 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3207 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3208 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
3209 ; RV64IZFHMIN-NEXT: ret
3210 ;
3211 ; RV32IZHINXMIN-LABEL: test_round_ui8:
3212 ; RV32IZHINXMIN: # %bb.0:
3213 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3214 ; RV32IZHINXMIN-NEXT: lui a1, 307200
3215 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
3216 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
3217 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB28_2
3218 ; RV32IZHINXMIN-NEXT: # %bb.1:
3219 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
3220 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
3221 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3222 ; RV32IZHINXMIN-NEXT: .LBB28_2:
3223 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
3224 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3225 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
3226 ; RV32IZHINXMIN-NEXT: ret
3227 ;
3228 ; RV64IZHINXMIN-LABEL: test_round_ui8:
3229 ; RV64IZHINXMIN: # %bb.0:
3230 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3231 ; RV64IZHINXMIN-NEXT: lui a1, 307200
3232 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
3233 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
3234 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB28_2
3235 ; RV64IZHINXMIN-NEXT: # %bb.1:
3236 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
3237 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
3238 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3239 ; RV64IZHINXMIN-NEXT: .LBB28_2:
3240 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
3241 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3242 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
3243 ; RV64IZHINXMIN-NEXT: ret
3244 %a = call half @llvm.round.f16(half %x)
3245 %b = fptoui half %a to i8
3246 ret i8 %b
3247 }
3249 define zeroext i16 @test_round_ui16(half %x) {
3250 ; RV32IZFH-LABEL: test_round_ui16:
3251 ; RV32IZFH: # %bb.0:
3252 ; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rmm
3253 ; RV32IZFH-NEXT: ret
3254 ;
3255 ; RV64IZFH-LABEL: test_round_ui16:
3256 ; RV64IZFH: # %bb.0:
3257 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rmm
3258 ; RV64IZFH-NEXT: ret
3259 ;
3260 ; RV32IZHINX-LABEL: test_round_ui16:
3261 ; RV32IZHINX: # %bb.0:
3262 ; RV32IZHINX-NEXT: li a1, 25
3263 ; RV32IZHINX-NEXT: slli a1, a1, 10
3264 ; RV32IZHINX-NEXT: fabs.h a2, a0
3265 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
3266 ; RV32IZHINX-NEXT: beqz a1, .LBB29_2
3267 ; RV32IZHINX-NEXT: # %bb.1:
3268 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rmm
3269 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rmm
3270 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
3271 ; RV32IZHINX-NEXT: .LBB29_2:
3272 ; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
3273 ; RV32IZHINX-NEXT: ret
3274 ;
3275 ; RV64IZHINX-LABEL: test_round_ui16:
3276 ; RV64IZHINX: # %bb.0:
3277 ; RV64IZHINX-NEXT: li a1, 25
3278 ; RV64IZHINX-NEXT: slli a1, a1, 10
3279 ; RV64IZHINX-NEXT: fabs.h a2, a0
3280 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
3281 ; RV64IZHINX-NEXT: beqz a1, .LBB29_2
3282 ; RV64IZHINX-NEXT: # %bb.1:
3283 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rmm
3284 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rmm
3285 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
3286 ; RV64IZHINX-NEXT: .LBB29_2:
3287 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
3288 ; RV64IZHINX-NEXT: ret
3289 ;
3290 ; RV32IZFHMIN-LABEL: test_round_ui16:
3291 ; RV32IZFHMIN: # %bb.0:
3292 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3293 ; RV32IZFHMIN-NEXT: lui a0, 307200
3294 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
3295 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
3296 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
3297 ; RV32IZFHMIN-NEXT: beqz a0, .LBB29_2
3298 ; RV32IZFHMIN-NEXT: # %bb.1:
3299 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
3300 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
3301 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3302 ; RV32IZFHMIN-NEXT: .LBB29_2:
3303 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3304 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3305 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
3306 ; RV32IZFHMIN-NEXT: ret
3307 ;
3308 ; RV64IZFHMIN-LABEL: test_round_ui16:
3309 ; RV64IZFHMIN: # %bb.0:
3310 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3311 ; RV64IZFHMIN-NEXT: lui a0, 307200
3312 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
3313 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
3314 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
3315 ; RV64IZFHMIN-NEXT: beqz a0, .LBB29_2
3316 ; RV64IZFHMIN-NEXT: # %bb.1:
3317 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
3318 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
3319 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3320 ; RV64IZFHMIN-NEXT: .LBB29_2:
3321 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3322 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3323 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
3324 ; RV64IZFHMIN-NEXT: ret
3325 ;
3326 ; RV32IZHINXMIN-LABEL: test_round_ui16:
3327 ; RV32IZHINXMIN: # %bb.0:
3328 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3329 ; RV32IZHINXMIN-NEXT: lui a1, 307200
3330 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
3331 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
3332 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB29_2
3333 ; RV32IZHINXMIN-NEXT: # %bb.1:
3334 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
3335 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
3336 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3337 ; RV32IZHINXMIN-NEXT: .LBB29_2:
3338 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
3339 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3340 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
3341 ; RV32IZHINXMIN-NEXT: ret
3342 ;
3343 ; RV64IZHINXMIN-LABEL: test_round_ui16:
3344 ; RV64IZHINXMIN: # %bb.0:
3345 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3346 ; RV64IZHINXMIN-NEXT: lui a1, 307200
3347 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
3348 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
3349 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB29_2
3350 ; RV64IZHINXMIN-NEXT: # %bb.1:
3351 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
3352 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
3353 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3354 ; RV64IZHINXMIN-NEXT: .LBB29_2:
3355 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
3356 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3357 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
3358 ; RV64IZHINXMIN-NEXT: ret
3359 %a = call half @llvm.round.f16(half %x)
3360 %b = fptoui half %a to i16
3361 ret i16 %b
3362 }
3364 define signext i32 @test_round_ui32(half %x) {
3365 ; CHECKIZFH-LABEL: test_round_ui32:
3366 ; CHECKIZFH: # %bb.0:
3367 ; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rmm
3368 ; CHECKIZFH-NEXT: ret
3369 ;
3370 ; CHECKIZHINX-LABEL: test_round_ui32:
3371 ; CHECKIZHINX: # %bb.0:
3372 ; CHECKIZHINX-NEXT: li a1, 25
3373 ; CHECKIZHINX-NEXT: slli a1, a1, 10
3374 ; CHECKIZHINX-NEXT: fabs.h a2, a0
3375 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
3376 ; CHECKIZHINX-NEXT: beqz a1, .LBB30_2
3377 ; CHECKIZHINX-NEXT: # %bb.1:
3378 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rmm
3379 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rmm
3380 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
3381 ; CHECKIZHINX-NEXT: .LBB30_2:
3382 ; CHECKIZHINX-NEXT: fcvt.wu.h a0, a0, rtz
3383 ; CHECKIZHINX-NEXT: ret
3384 ;
3385 ; CHECKIZFHMIN-LABEL: test_round_ui32:
3386 ; CHECKIZFHMIN: # %bb.0:
3387 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
3388 ; CHECKIZFHMIN-NEXT: lui a0, 307200
3389 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
3390 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
3391 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
3392 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB30_2
3393 ; CHECKIZFHMIN-NEXT: # %bb.1:
3394 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
3395 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
3396 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3397 ; CHECKIZFHMIN-NEXT: .LBB30_2:
3398 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5
3399 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5
3400 ; CHECKIZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
3401 ; CHECKIZFHMIN-NEXT: ret
3402 ;
3403 ; CHECKIZHINXMIN-LABEL: test_round_ui32:
3404 ; CHECKIZHINXMIN: # %bb.0:
3405 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
3406 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
3407 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
3408 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
3409 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB30_2
3410 ; CHECKIZHINXMIN-NEXT: # %bb.1:
3411 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
3412 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
3413 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3414 ; CHECKIZHINXMIN-NEXT: .LBB30_2:
3415 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
3416 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
3417 ; CHECKIZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
3418 ; CHECKIZHINXMIN-NEXT: ret
3419 %a = call half @llvm.round.f16(half %x)
3420 %b = fptoui half %a to i32
3421 ret i32 %b
3422 }
3424 define i64 @test_round_ui64(half %x) {
3425 ; RV32IZFH-LABEL: test_round_ui64:
3426 ; RV32IZFH: # %bb.0:
3427 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI31_0)
3428 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI31_0)(a0)
3429 ; RV32IZFH-NEXT: fabs.h fa4, fa0
3430 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
3431 ; RV32IZFH-NEXT: beqz a0, .LBB31_2
3432 ; RV32IZFH-NEXT: # %bb.1:
3433 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm
3434 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rmm
3435 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
3436 ; RV32IZFH-NEXT: .LBB31_2:
3437 ; RV32IZFH-NEXT: addi sp, sp, -16
3438 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
3439 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3440 ; RV32IZFH-NEXT: .cfi_offset ra, -4
3441 ; RV32IZFH-NEXT: call __fixunshfdi
3442 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3443 ; RV32IZFH-NEXT: .cfi_restore ra
3444 ; RV32IZFH-NEXT: addi sp, sp, 16
3445 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
3446 ; RV32IZFH-NEXT: ret
3447 ;
3448 ; RV64IZFH-LABEL: test_round_ui64:
3449 ; RV64IZFH: # %bb.0:
3450 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rmm
3451 ; RV64IZFH-NEXT: ret
3452 ;
3453 ; RV32IZHINX-LABEL: test_round_ui64:
3454 ; RV32IZHINX: # %bb.0:
3455 ; RV32IZHINX-NEXT: li a1, 25
3456 ; RV32IZHINX-NEXT: slli a1, a1, 10
3457 ; RV32IZHINX-NEXT: fabs.h a2, a0
3458 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
3459 ; RV32IZHINX-NEXT: beqz a1, .LBB31_2
3460 ; RV32IZHINX-NEXT: # %bb.1:
3461 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rmm
3462 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rmm
3463 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
3464 ; RV32IZHINX-NEXT: .LBB31_2:
3465 ; RV32IZHINX-NEXT: addi sp, sp, -16
3466 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
3467 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3468 ; RV32IZHINX-NEXT: .cfi_offset ra, -4
3469 ; RV32IZHINX-NEXT: call __fixunshfdi
3470 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3471 ; RV32IZHINX-NEXT: .cfi_restore ra
3472 ; RV32IZHINX-NEXT: addi sp, sp, 16
3473 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
3474 ; RV32IZHINX-NEXT: ret
3475 ;
3476 ; RV64IZHINX-LABEL: test_round_ui64:
3477 ; RV64IZHINX: # %bb.0:
3478 ; RV64IZHINX-NEXT: li a1, 25
3479 ; RV64IZHINX-NEXT: slli a1, a1, 10
3480 ; RV64IZHINX-NEXT: fabs.h a2, a0
3481 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
3482 ; RV64IZHINX-NEXT: beqz a1, .LBB31_2
3483 ; RV64IZHINX-NEXT: # %bb.1:
3484 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rmm
3485 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rmm
3486 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
3487 ; RV64IZHINX-NEXT: .LBB31_2:
3488 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
3489 ; RV64IZHINX-NEXT: ret
3490 ;
3491 ; RV32IZFHMIN-LABEL: test_round_ui64:
3492 ; RV32IZFHMIN: # %bb.0:
3493 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3494 ; RV32IZFHMIN-NEXT: lui a0, 307200
3495 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
3496 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
3497 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
3498 ; RV32IZFHMIN-NEXT: beqz a0, .LBB31_2
3499 ; RV32IZFHMIN-NEXT: # %bb.1:
3500 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
3501 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
3502 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3503 ; RV32IZFHMIN-NEXT: .LBB31_2:
3504 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
3505 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
3506 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3507 ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
3508 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
3509 ; RV32IZFHMIN-NEXT: call __fixunshfdi
3510 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3511 ; RV32IZFHMIN-NEXT: .cfi_restore ra
3512 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
3513 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
3514 ; RV32IZFHMIN-NEXT: ret
3515 ;
3516 ; RV64IZFHMIN-LABEL: test_round_ui64:
3517 ; RV64IZFHMIN: # %bb.0:
3518 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3519 ; RV64IZFHMIN-NEXT: lui a0, 307200
3520 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
3521 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
3522 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
3523 ; RV64IZFHMIN-NEXT: beqz a0, .LBB31_2
3524 ; RV64IZFHMIN-NEXT: # %bb.1:
3525 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
3526 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
3527 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3528 ; RV64IZFHMIN-NEXT: .LBB31_2:
3529 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3530 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3531 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
3532 ; RV64IZFHMIN-NEXT: ret
3533 ;
3534 ; RV32IZHINXMIN-LABEL: test_round_ui64:
3535 ; RV32IZHINXMIN: # %bb.0:
3536 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3537 ; RV32IZHINXMIN-NEXT: lui a1, 307200
3538 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
3539 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
3540 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB31_2
3541 ; RV32IZHINXMIN-NEXT: # %bb.1:
3542 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
3543 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
3544 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3545 ; RV32IZHINXMIN-NEXT: .LBB31_2:
3546 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
3547 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
3548 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3549 ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
3550 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
3551 ; RV32IZHINXMIN-NEXT: call __fixunshfdi
3552 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3553 ; RV32IZHINXMIN-NEXT: .cfi_restore ra
3554 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
3555 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
3556 ; RV32IZHINXMIN-NEXT: ret
3557 ;
3558 ; RV64IZHINXMIN-LABEL: test_round_ui64:
3559 ; RV64IZHINXMIN: # %bb.0:
3560 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3561 ; RV64IZHINXMIN-NEXT: lui a1, 307200
3562 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
3563 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
3564 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB31_2
3565 ; RV64IZHINXMIN-NEXT: # %bb.1:
3566 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
3567 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
3568 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3569 ; RV64IZHINXMIN-NEXT: .LBB31_2:
3570 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
3571 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3572 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
3573 ; RV64IZHINXMIN-NEXT: ret
3574 %a = call half @llvm.round.f16(half %x)
3575 %b = fptoui half %a to i64
3576 ret i64 %b
3577 }
3579 define signext i8 @test_roundeven_si8(half %x) {
3580 ; RV32IZFH-LABEL: test_roundeven_si8:
3581 ; RV32IZFH: # %bb.0:
3582 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rne
3583 ; RV32IZFH-NEXT: ret
3584 ;
3585 ; RV64IZFH-LABEL: test_roundeven_si8:
3586 ; RV64IZFH: # %bb.0:
3587 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rne
3588 ; RV64IZFH-NEXT: ret
3589 ;
3590 ; RV32IZHINX-LABEL: test_roundeven_si8:
3591 ; RV32IZHINX: # %bb.0:
3592 ; RV32IZHINX-NEXT: li a1, 25
3593 ; RV32IZHINX-NEXT: slli a1, a1, 10
3594 ; RV32IZHINX-NEXT: fabs.h a2, a0
3595 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
3596 ; RV32IZHINX-NEXT: beqz a1, .LBB32_2
3597 ; RV32IZHINX-NEXT: # %bb.1:
3598 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rne
3599 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rne
3600 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
3601 ; RV32IZHINX-NEXT: .LBB32_2:
3602 ; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
3603 ; RV32IZHINX-NEXT: ret
3604 ;
3605 ; RV64IZHINX-LABEL: test_roundeven_si8:
3606 ; RV64IZHINX: # %bb.0:
3607 ; RV64IZHINX-NEXT: li a1, 25
3608 ; RV64IZHINX-NEXT: slli a1, a1, 10
3609 ; RV64IZHINX-NEXT: fabs.h a2, a0
3610 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
3611 ; RV64IZHINX-NEXT: beqz a1, .LBB32_2
3612 ; RV64IZHINX-NEXT: # %bb.1:
3613 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rne
3614 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rne
3615 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
3616 ; RV64IZHINX-NEXT: .LBB32_2:
3617 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
3618 ; RV64IZHINX-NEXT: ret
3619 ;
3620 ; RV32IZFHMIN-LABEL: test_roundeven_si8:
3621 ; RV32IZFHMIN: # %bb.0:
3622 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3623 ; RV32IZFHMIN-NEXT: lui a0, 307200
3624 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
3625 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
3626 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
3627 ; RV32IZFHMIN-NEXT: beqz a0, .LBB32_2
3628 ; RV32IZFHMIN-NEXT: # %bb.1:
3629 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
3630 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
3631 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3632 ; RV32IZFHMIN-NEXT: .LBB32_2:
3633 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3634 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3635 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
3636 ; RV32IZFHMIN-NEXT: ret
3637 ;
3638 ; RV64IZFHMIN-LABEL: test_roundeven_si8:
3639 ; RV64IZFHMIN: # %bb.0:
3640 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3641 ; RV64IZFHMIN-NEXT: lui a0, 307200
3642 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
3643 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
3644 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
3645 ; RV64IZFHMIN-NEXT: beqz a0, .LBB32_2
3646 ; RV64IZFHMIN-NEXT: # %bb.1:
3647 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
3648 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
3649 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3650 ; RV64IZFHMIN-NEXT: .LBB32_2:
3651 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3652 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3653 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
3654 ; RV64IZFHMIN-NEXT: ret
3655 ;
3656 ; RV32IZHINXMIN-LABEL: test_roundeven_si8:
3657 ; RV32IZHINXMIN: # %bb.0:
3658 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3659 ; RV32IZHINXMIN-NEXT: lui a1, 307200
3660 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
3661 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
3662 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB32_2
3663 ; RV32IZHINXMIN-NEXT: # %bb.1:
3664 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
3665 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
3666 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3667 ; RV32IZHINXMIN-NEXT: .LBB32_2:
3668 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
3669 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3670 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
3671 ; RV32IZHINXMIN-NEXT: ret
3672 ;
3673 ; RV64IZHINXMIN-LABEL: test_roundeven_si8:
3674 ; RV64IZHINXMIN: # %bb.0:
3675 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3676 ; RV64IZHINXMIN-NEXT: lui a1, 307200
3677 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
3678 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
3679 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB32_2
3680 ; RV64IZHINXMIN-NEXT: # %bb.1:
3681 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
3682 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
3683 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3684 ; RV64IZHINXMIN-NEXT: .LBB32_2:
3685 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
3686 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3687 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
3688 ; RV64IZHINXMIN-NEXT: ret
3689 %a = call half @llvm.roundeven.f16(half %x)
3690 %b = fptosi half %a to i8
3691 ret i8 %b
3692 }
3694 define signext i16 @test_roundeven_si16(half %x) {
3695 ; RV32IZFH-LABEL: test_roundeven_si16:
3696 ; RV32IZFH: # %bb.0:
3697 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rne
3698 ; RV32IZFH-NEXT: ret
3699 ;
3700 ; RV64IZFH-LABEL: test_roundeven_si16:
3701 ; RV64IZFH: # %bb.0:
3702 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rne
3703 ; RV64IZFH-NEXT: ret
3704 ;
3705 ; RV32IZHINX-LABEL: test_roundeven_si16:
3706 ; RV32IZHINX: # %bb.0:
3707 ; RV32IZHINX-NEXT: li a1, 25
3708 ; RV32IZHINX-NEXT: slli a1, a1, 10
3709 ; RV32IZHINX-NEXT: fabs.h a2, a0
3710 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
3711 ; RV32IZHINX-NEXT: beqz a1, .LBB33_2
3712 ; RV32IZHINX-NEXT: # %bb.1:
3713 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rne
3714 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rne
3715 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
3716 ; RV32IZHINX-NEXT: .LBB33_2:
3717 ; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
3718 ; RV32IZHINX-NEXT: ret
3719 ;
3720 ; RV64IZHINX-LABEL: test_roundeven_si16:
3721 ; RV64IZHINX: # %bb.0:
3722 ; RV64IZHINX-NEXT: li a1, 25
3723 ; RV64IZHINX-NEXT: slli a1, a1, 10
3724 ; RV64IZHINX-NEXT: fabs.h a2, a0
3725 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
3726 ; RV64IZHINX-NEXT: beqz a1, .LBB33_2
3727 ; RV64IZHINX-NEXT: # %bb.1:
3728 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rne
3729 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rne
3730 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
3731 ; RV64IZHINX-NEXT: .LBB33_2:
3732 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
3733 ; RV64IZHINX-NEXT: ret
3734 ;
3735 ; RV32IZFHMIN-LABEL: test_roundeven_si16:
3736 ; RV32IZFHMIN: # %bb.0:
3737 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3738 ; RV32IZFHMIN-NEXT: lui a0, 307200
3739 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
3740 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
3741 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
3742 ; RV32IZFHMIN-NEXT: beqz a0, .LBB33_2
3743 ; RV32IZFHMIN-NEXT: # %bb.1:
3744 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
3745 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
3746 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3747 ; RV32IZFHMIN-NEXT: .LBB33_2:
3748 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3749 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3750 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
3751 ; RV32IZFHMIN-NEXT: ret
3752 ;
3753 ; RV64IZFHMIN-LABEL: test_roundeven_si16:
3754 ; RV64IZFHMIN: # %bb.0:
3755 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3756 ; RV64IZFHMIN-NEXT: lui a0, 307200
3757 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
3758 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
3759 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
3760 ; RV64IZFHMIN-NEXT: beqz a0, .LBB33_2
3761 ; RV64IZFHMIN-NEXT: # %bb.1:
3762 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
3763 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
3764 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3765 ; RV64IZFHMIN-NEXT: .LBB33_2:
3766 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3767 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3768 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
3769 ; RV64IZFHMIN-NEXT: ret
3770 ;
3771 ; RV32IZHINXMIN-LABEL: test_roundeven_si16:
3772 ; RV32IZHINXMIN: # %bb.0:
3773 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3774 ; RV32IZHINXMIN-NEXT: lui a1, 307200
3775 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
3776 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
3777 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB33_2
3778 ; RV32IZHINXMIN-NEXT: # %bb.1:
3779 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
3780 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
3781 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3782 ; RV32IZHINXMIN-NEXT: .LBB33_2:
3783 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
3784 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3785 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
3786 ; RV32IZHINXMIN-NEXT: ret
3787 ;
3788 ; RV64IZHINXMIN-LABEL: test_roundeven_si16:
3789 ; RV64IZHINXMIN: # %bb.0:
3790 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3791 ; RV64IZHINXMIN-NEXT: lui a1, 307200
3792 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
3793 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
3794 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB33_2
3795 ; RV64IZHINXMIN-NEXT: # %bb.1:
3796 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
3797 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
3798 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3799 ; RV64IZHINXMIN-NEXT: .LBB33_2:
3800 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
3801 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3802 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
3803 ; RV64IZHINXMIN-NEXT: ret
3804 %a = call half @llvm.roundeven.f16(half %x)
3805 %b = fptosi half %a to i16
3806 ret i16 %b
3807 }
3809 define signext i32 @test_roundeven_si32(half %x) {
3810 ; CHECKIZFH-LABEL: test_roundeven_si32:
3811 ; CHECKIZFH: # %bb.0:
3812 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rne
3813 ; CHECKIZFH-NEXT: ret
3814 ;
3815 ; CHECKIZHINX-LABEL: test_roundeven_si32:
3816 ; CHECKIZHINX: # %bb.0:
3817 ; CHECKIZHINX-NEXT: li a1, 25
3818 ; CHECKIZHINX-NEXT: slli a1, a1, 10
3819 ; CHECKIZHINX-NEXT: fabs.h a2, a0
3820 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
3821 ; CHECKIZHINX-NEXT: beqz a1, .LBB34_2
3822 ; CHECKIZHINX-NEXT: # %bb.1:
3823 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rne
3824 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rne
3825 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
3826 ; CHECKIZHINX-NEXT: .LBB34_2:
3827 ; CHECKIZHINX-NEXT: fcvt.w.h a0, a0, rtz
3828 ; CHECKIZHINX-NEXT: ret
3829 ;
3830 ; CHECKIZFHMIN-LABEL: test_roundeven_si32:
3831 ; CHECKIZFHMIN: # %bb.0:
3832 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
3833 ; CHECKIZFHMIN-NEXT: lui a0, 307200
3834 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
3835 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
3836 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
3837 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB34_2
3838 ; CHECKIZFHMIN-NEXT: # %bb.1:
3839 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
3840 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
3841 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3842 ; CHECKIZFHMIN-NEXT: .LBB34_2:
3843 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5
3844 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5
3845 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
3846 ; CHECKIZFHMIN-NEXT: ret
3847 ;
3848 ; CHECKIZHINXMIN-LABEL: test_roundeven_si32:
3849 ; CHECKIZHINXMIN: # %bb.0:
3850 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
3851 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
3852 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
3853 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
3854 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB34_2
3855 ; CHECKIZHINXMIN-NEXT: # %bb.1:
3856 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
3857 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
3858 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3859 ; CHECKIZHINXMIN-NEXT: .LBB34_2:
3860 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
3861 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
3862 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
3863 ; CHECKIZHINXMIN-NEXT: ret
3864 %a = call half @llvm.roundeven.f16(half %x)
3865 %b = fptosi half %a to i32
3866 ret i32 %b
3867 }
3869 define i64 @test_roundeven_si64(half %x) {
3870 ; RV32IZFH-LABEL: test_roundeven_si64:
3871 ; RV32IZFH: # %bb.0:
3872 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI35_0)
3873 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI35_0)(a0)
3874 ; RV32IZFH-NEXT: fabs.h fa4, fa0
3875 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
3876 ; RV32IZFH-NEXT: beqz a0, .LBB35_2
3877 ; RV32IZFH-NEXT: # %bb.1:
3878 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rne
3879 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rne
3880 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
3881 ; RV32IZFH-NEXT: .LBB35_2:
3882 ; RV32IZFH-NEXT: addi sp, sp, -16
3883 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
3884 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3885 ; RV32IZFH-NEXT: .cfi_offset ra, -4
3886 ; RV32IZFH-NEXT: call __fixhfdi
3887 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3888 ; RV32IZFH-NEXT: .cfi_restore ra
3889 ; RV32IZFH-NEXT: addi sp, sp, 16
3890 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
3891 ; RV32IZFH-NEXT: ret
3892 ;
3893 ; RV64IZFH-LABEL: test_roundeven_si64:
3894 ; RV64IZFH: # %bb.0:
3895 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rne
3896 ; RV64IZFH-NEXT: ret
3897 ;
3898 ; RV32IZHINX-LABEL: test_roundeven_si64:
3899 ; RV32IZHINX: # %bb.0:
3900 ; RV32IZHINX-NEXT: li a1, 25
3901 ; RV32IZHINX-NEXT: slli a1, a1, 10
3902 ; RV32IZHINX-NEXT: fabs.h a2, a0
3903 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
3904 ; RV32IZHINX-NEXT: beqz a1, .LBB35_2
3905 ; RV32IZHINX-NEXT: # %bb.1:
3906 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rne
3907 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rne
3908 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
3909 ; RV32IZHINX-NEXT: .LBB35_2:
3910 ; RV32IZHINX-NEXT: addi sp, sp, -16
3911 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
3912 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3913 ; RV32IZHINX-NEXT: .cfi_offset ra, -4
3914 ; RV32IZHINX-NEXT: call __fixhfdi
3915 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3916 ; RV32IZHINX-NEXT: .cfi_restore ra
3917 ; RV32IZHINX-NEXT: addi sp, sp, 16
3918 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
3919 ; RV32IZHINX-NEXT: ret
3920 ;
3921 ; RV64IZHINX-LABEL: test_roundeven_si64:
3922 ; RV64IZHINX: # %bb.0:
3923 ; RV64IZHINX-NEXT: li a1, 25
3924 ; RV64IZHINX-NEXT: slli a1, a1, 10
3925 ; RV64IZHINX-NEXT: fabs.h a2, a0
3926 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
3927 ; RV64IZHINX-NEXT: beqz a1, .LBB35_2
3928 ; RV64IZHINX-NEXT: # %bb.1:
3929 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rne
3930 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rne
3931 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
3932 ; RV64IZHINX-NEXT: .LBB35_2:
3933 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
3934 ; RV64IZHINX-NEXT: ret
3935 ;
3936 ; RV32IZFHMIN-LABEL: test_roundeven_si64:
3937 ; RV32IZFHMIN: # %bb.0:
3938 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3939 ; RV32IZFHMIN-NEXT: lui a0, 307200
3940 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
3941 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
3942 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
3943 ; RV32IZFHMIN-NEXT: beqz a0, .LBB35_2
3944 ; RV32IZFHMIN-NEXT: # %bb.1:
3945 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
3946 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
3947 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3948 ; RV32IZFHMIN-NEXT: .LBB35_2:
3949 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
3950 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
3951 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3952 ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
3953 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
3954 ; RV32IZFHMIN-NEXT: call __fixhfdi
3955 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3956 ; RV32IZFHMIN-NEXT: .cfi_restore ra
3957 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
3958 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
3959 ; RV32IZFHMIN-NEXT: ret
3960 ;
3961 ; RV64IZFHMIN-LABEL: test_roundeven_si64:
3962 ; RV64IZFHMIN: # %bb.0:
3963 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3964 ; RV64IZFHMIN-NEXT: lui a0, 307200
3965 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
3966 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
3967 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
3968 ; RV64IZFHMIN-NEXT: beqz a0, .LBB35_2
3969 ; RV64IZFHMIN-NEXT: # %bb.1:
3970 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
3971 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
3972 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3973 ; RV64IZFHMIN-NEXT: .LBB35_2:
3974 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3975 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3976 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
3977 ; RV64IZFHMIN-NEXT: ret
3978 ;
3979 ; RV32IZHINXMIN-LABEL: test_roundeven_si64:
3980 ; RV32IZHINXMIN: # %bb.0:
3981 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3982 ; RV32IZHINXMIN-NEXT: lui a1, 307200
3983 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
3984 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
3985 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB35_2
3986 ; RV32IZHINXMIN-NEXT: # %bb.1:
3987 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
3988 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
3989 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3990 ; RV32IZHINXMIN-NEXT: .LBB35_2:
3991 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
3992 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
3993 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3994 ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
3995 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
3996 ; RV32IZHINXMIN-NEXT: call __fixhfdi
3997 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3998 ; RV32IZHINXMIN-NEXT: .cfi_restore ra
3999 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
4000 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
4001 ; RV32IZHINXMIN-NEXT: ret
4002 ;
4003 ; RV64IZHINXMIN-LABEL: test_roundeven_si64:
4004 ; RV64IZHINXMIN: # %bb.0:
4005 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
4006 ; RV64IZHINXMIN-NEXT: lui a1, 307200
4007 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
4008 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
4009 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB35_2
4010 ; RV64IZHINXMIN-NEXT: # %bb.1:
4011 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
4012 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
4013 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4014 ; RV64IZHINXMIN-NEXT: .LBB35_2:
4015 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
4016 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
4017 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
4018 ; RV64IZHINXMIN-NEXT: ret
4019 %a = call half @llvm.roundeven.f16(half %x)
4020 %b = fptosi half %a to i64
4021 ret i64 %b
4022 }
4024 define zeroext i8 @test_roundeven_ui8(half %x) {
4025 ; RV32IZFH-LABEL: test_roundeven_ui8:
4026 ; RV32IZFH: # %bb.0:
4027 ; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rne
4028 ; RV32IZFH-NEXT: ret
4029 ;
4030 ; RV64IZFH-LABEL: test_roundeven_ui8:
4031 ; RV64IZFH: # %bb.0:
4032 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rne
4033 ; RV64IZFH-NEXT: ret
4034 ;
4035 ; RV32IZHINX-LABEL: test_roundeven_ui8:
4036 ; RV32IZHINX: # %bb.0:
4037 ; RV32IZHINX-NEXT: li a1, 25
4038 ; RV32IZHINX-NEXT: slli a1, a1, 10
4039 ; RV32IZHINX-NEXT: fabs.h a2, a0
4040 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
4041 ; RV32IZHINX-NEXT: beqz a1, .LBB36_2
4042 ; RV32IZHINX-NEXT: # %bb.1:
4043 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rne
4044 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rne
4045 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
4046 ; RV32IZHINX-NEXT: .LBB36_2:
4047 ; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
4048 ; RV32IZHINX-NEXT: ret
4049 ;
4050 ; RV64IZHINX-LABEL: test_roundeven_ui8:
4051 ; RV64IZHINX: # %bb.0:
4052 ; RV64IZHINX-NEXT: li a1, 25
4053 ; RV64IZHINX-NEXT: slli a1, a1, 10
4054 ; RV64IZHINX-NEXT: fabs.h a2, a0
4055 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
4056 ; RV64IZHINX-NEXT: beqz a1, .LBB36_2
4057 ; RV64IZHINX-NEXT: # %bb.1:
4058 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rne
4059 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rne
4060 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
4061 ; RV64IZHINX-NEXT: .LBB36_2:
4062 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
4063 ; RV64IZHINX-NEXT: ret
4064 ;
4065 ; RV32IZFHMIN-LABEL: test_roundeven_ui8:
4066 ; RV32IZFHMIN: # %bb.0:
4067 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
4068 ; RV32IZFHMIN-NEXT: lui a0, 307200
4069 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
4070 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
4071 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
4072 ; RV32IZFHMIN-NEXT: beqz a0, .LBB36_2
4073 ; RV32IZFHMIN-NEXT: # %bb.1:
4074 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
4075 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
4076 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
4077 ; RV32IZFHMIN-NEXT: .LBB36_2:
4078 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
4079 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
4080 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
4081 ; RV32IZFHMIN-NEXT: ret
4082 ;
4083 ; RV64IZFHMIN-LABEL: test_roundeven_ui8:
4084 ; RV64IZFHMIN: # %bb.0:
4085 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
4086 ; RV64IZFHMIN-NEXT: lui a0, 307200
4087 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
4088 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
4089 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
4090 ; RV64IZFHMIN-NEXT: beqz a0, .LBB36_2
4091 ; RV64IZFHMIN-NEXT: # %bb.1:
4092 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
4093 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
4094 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
4095 ; RV64IZFHMIN-NEXT: .LBB36_2:
4096 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
4097 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
4098 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
4099 ; RV64IZFHMIN-NEXT: ret
4100 ;
4101 ; RV32IZHINXMIN-LABEL: test_roundeven_ui8:
4102 ; RV32IZHINXMIN: # %bb.0:
4103 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
4104 ; RV32IZHINXMIN-NEXT: lui a1, 307200
4105 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
4106 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
4107 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB36_2
4108 ; RV32IZHINXMIN-NEXT: # %bb.1:
4109 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
4110 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
4111 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4112 ; RV32IZHINXMIN-NEXT: .LBB36_2:
4113 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
4114 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
4115 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
4116 ; RV32IZHINXMIN-NEXT: ret
4117 ;
4118 ; RV64IZHINXMIN-LABEL: test_roundeven_ui8:
4119 ; RV64IZHINXMIN: # %bb.0:
4120 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
4121 ; RV64IZHINXMIN-NEXT: lui a1, 307200
4122 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
4123 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
4124 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB36_2
4125 ; RV64IZHINXMIN-NEXT: # %bb.1:
4126 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
4127 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
4128 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4129 ; RV64IZHINXMIN-NEXT: .LBB36_2:
4130 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
4131 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
4132 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
4133 ; RV64IZHINXMIN-NEXT: ret
4134 %a = call half @llvm.roundeven.f16(half %x)
4135 %b = fptoui half %a to i8
4136 ret i8 %b
4137 }
4139 define zeroext i16 @test_roundeven_ui16(half %x) {
4140 ; RV32IZFH-LABEL: test_roundeven_ui16:
4141 ; RV32IZFH: # %bb.0:
4142 ; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rne
4143 ; RV32IZFH-NEXT: ret
4144 ;
4145 ; RV64IZFH-LABEL: test_roundeven_ui16:
4146 ; RV64IZFH: # %bb.0:
4147 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rne
4148 ; RV64IZFH-NEXT: ret
4149 ;
4150 ; RV32IZHINX-LABEL: test_roundeven_ui16:
4151 ; RV32IZHINX: # %bb.0:
4152 ; RV32IZHINX-NEXT: li a1, 25
4153 ; RV32IZHINX-NEXT: slli a1, a1, 10
4154 ; RV32IZHINX-NEXT: fabs.h a2, a0
4155 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
4156 ; RV32IZHINX-NEXT: beqz a1, .LBB37_2
4157 ; RV32IZHINX-NEXT: # %bb.1:
4158 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rne
4159 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rne
4160 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
4161 ; RV32IZHINX-NEXT: .LBB37_2:
4162 ; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
4163 ; RV32IZHINX-NEXT: ret
4164 ;
4165 ; RV64IZHINX-LABEL: test_roundeven_ui16:
4166 ; RV64IZHINX: # %bb.0:
4167 ; RV64IZHINX-NEXT: li a1, 25
4168 ; RV64IZHINX-NEXT: slli a1, a1, 10
4169 ; RV64IZHINX-NEXT: fabs.h a2, a0
4170 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
4171 ; RV64IZHINX-NEXT: beqz a1, .LBB37_2
4172 ; RV64IZHINX-NEXT: # %bb.1:
4173 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rne
4174 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rne
4175 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
4176 ; RV64IZHINX-NEXT: .LBB37_2:
4177 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
4178 ; RV64IZHINX-NEXT: ret
4179 ;
4180 ; RV32IZFHMIN-LABEL: test_roundeven_ui16:
4181 ; RV32IZFHMIN: # %bb.0:
4182 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
4183 ; RV32IZFHMIN-NEXT: lui a0, 307200
4184 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
4185 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
4186 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
4187 ; RV32IZFHMIN-NEXT: beqz a0, .LBB37_2
4188 ; RV32IZFHMIN-NEXT: # %bb.1:
4189 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
4190 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
4191 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
4192 ; RV32IZFHMIN-NEXT: .LBB37_2:
4193 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
4194 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
4195 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
4196 ; RV32IZFHMIN-NEXT: ret
4197 ;
4198 ; RV64IZFHMIN-LABEL: test_roundeven_ui16:
4199 ; RV64IZFHMIN: # %bb.0:
4200 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
4201 ; RV64IZFHMIN-NEXT: lui a0, 307200
4202 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
4203 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
4204 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
4205 ; RV64IZFHMIN-NEXT: beqz a0, .LBB37_2
4206 ; RV64IZFHMIN-NEXT: # %bb.1:
4207 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
4208 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
4209 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
4210 ; RV64IZFHMIN-NEXT: .LBB37_2:
4211 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
4212 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
4213 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
4214 ; RV64IZFHMIN-NEXT: ret
4215 ;
4216 ; RV32IZHINXMIN-LABEL: test_roundeven_ui16:
4217 ; RV32IZHINXMIN: # %bb.0:
4218 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
4219 ; RV32IZHINXMIN-NEXT: lui a1, 307200
4220 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
4221 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
4222 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB37_2
4223 ; RV32IZHINXMIN-NEXT: # %bb.1:
4224 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
4225 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
4226 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4227 ; RV32IZHINXMIN-NEXT: .LBB37_2:
4228 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
4229 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
4230 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
4231 ; RV32IZHINXMIN-NEXT: ret
4232 ;
4233 ; RV64IZHINXMIN-LABEL: test_roundeven_ui16:
4234 ; RV64IZHINXMIN: # %bb.0:
4235 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
4236 ; RV64IZHINXMIN-NEXT: lui a1, 307200
4237 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
4238 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
4239 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB37_2
4240 ; RV64IZHINXMIN-NEXT: # %bb.1:
4241 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
4242 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
4243 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4244 ; RV64IZHINXMIN-NEXT: .LBB37_2:
4245 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
4246 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
4247 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
4248 ; RV64IZHINXMIN-NEXT: ret
4249 %a = call half @llvm.roundeven.f16(half %x)
4250 %b = fptoui half %a to i16
4251 ret i16 %b
4252 }
4254 define signext i32 @test_roundeven_ui32(half %x) {
4255 ; CHECKIZFH-LABEL: test_roundeven_ui32:
4256 ; CHECKIZFH: # %bb.0:
4257 ; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rne
4258 ; CHECKIZFH-NEXT: ret
4259 ;
4260 ; CHECKIZHINX-LABEL: test_roundeven_ui32:
4261 ; CHECKIZHINX: # %bb.0:
4262 ; CHECKIZHINX-NEXT: li a1, 25
4263 ; CHECKIZHINX-NEXT: slli a1, a1, 10
4264 ; CHECKIZHINX-NEXT: fabs.h a2, a0
4265 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
4266 ; CHECKIZHINX-NEXT: beqz a1, .LBB38_2
4267 ; CHECKIZHINX-NEXT: # %bb.1:
4268 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rne
4269 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rne
4270 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
4271 ; CHECKIZHINX-NEXT: .LBB38_2:
4272 ; CHECKIZHINX-NEXT: fcvt.wu.h a0, a0, rtz
4273 ; CHECKIZHINX-NEXT: ret
4274 ;
4275 ; CHECKIZFHMIN-LABEL: test_roundeven_ui32:
4276 ; CHECKIZFHMIN: # %bb.0:
4277 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
4278 ; CHECKIZFHMIN-NEXT: lui a0, 307200
4279 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
4280 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
4281 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
4282 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB38_2
4283 ; CHECKIZFHMIN-NEXT: # %bb.1:
4284 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
4285 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
4286 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
4287 ; CHECKIZFHMIN-NEXT: .LBB38_2:
4288 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5
4289 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5
4290 ; CHECKIZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
4291 ; CHECKIZFHMIN-NEXT: ret
4292 ;
4293 ; CHECKIZHINXMIN-LABEL: test_roundeven_ui32:
4294 ; CHECKIZHINXMIN: # %bb.0:
4295 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
4296 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
4297 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
4298 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
4299 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB38_2
4300 ; CHECKIZHINXMIN-NEXT: # %bb.1:
4301 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
4302 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
4303 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4304 ; CHECKIZHINXMIN-NEXT: .LBB38_2:
4305 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
4306 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
4307 ; CHECKIZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
4308 ; CHECKIZHINXMIN-NEXT: ret
4309 %a = call half @llvm.roundeven.f16(half %x)
4310 %b = fptoui half %a to i32
4311 ret i32 %b
4312 }
4314 define i64 @test_roundeven_ui64(half %x) {
4315 ; RV32IZFH-LABEL: test_roundeven_ui64:
4316 ; RV32IZFH: # %bb.0:
4317 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI39_0)
4318 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI39_0)(a0)
4319 ; RV32IZFH-NEXT: fabs.h fa4, fa0
4320 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
4321 ; RV32IZFH-NEXT: beqz a0, .LBB39_2
4322 ; RV32IZFH-NEXT: # %bb.1:
4323 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rne
4324 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rne
4325 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
4326 ; RV32IZFH-NEXT: .LBB39_2:
4327 ; RV32IZFH-NEXT: addi sp, sp, -16
4328 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
4329 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
4330 ; RV32IZFH-NEXT: .cfi_offset ra, -4
4331 ; RV32IZFH-NEXT: call __fixunshfdi
4332 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
4333 ; RV32IZFH-NEXT: .cfi_restore ra
4334 ; RV32IZFH-NEXT: addi sp, sp, 16
4335 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
4336 ; RV32IZFH-NEXT: ret
4337 ;
4338 ; RV64IZFH-LABEL: test_roundeven_ui64:
4339 ; RV64IZFH: # %bb.0:
4340 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rne
4341 ; RV64IZFH-NEXT: ret
4342 ;
4343 ; RV32IZHINX-LABEL: test_roundeven_ui64:
4344 ; RV32IZHINX: # %bb.0:
4345 ; RV32IZHINX-NEXT: li a1, 25
4346 ; RV32IZHINX-NEXT: slli a1, a1, 10
4347 ; RV32IZHINX-NEXT: fabs.h a2, a0
4348 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
4349 ; RV32IZHINX-NEXT: beqz a1, .LBB39_2
4350 ; RV32IZHINX-NEXT: # %bb.1:
4351 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rne
4352 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rne
4353 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
4354 ; RV32IZHINX-NEXT: .LBB39_2:
4355 ; RV32IZHINX-NEXT: addi sp, sp, -16
4356 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
4357 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
4358 ; RV32IZHINX-NEXT: .cfi_offset ra, -4
4359 ; RV32IZHINX-NEXT: call __fixunshfdi
4360 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
4361 ; RV32IZHINX-NEXT: .cfi_restore ra
4362 ; RV32IZHINX-NEXT: addi sp, sp, 16
4363 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
4364 ; RV32IZHINX-NEXT: ret
4365 ;
4366 ; RV64IZHINX-LABEL: test_roundeven_ui64:
4367 ; RV64IZHINX: # %bb.0:
4368 ; RV64IZHINX-NEXT: li a1, 25
4369 ; RV64IZHINX-NEXT: slli a1, a1, 10
4370 ; RV64IZHINX-NEXT: fabs.h a2, a0
4371 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
4372 ; RV64IZHINX-NEXT: beqz a1, .LBB39_2
4373 ; RV64IZHINX-NEXT: # %bb.1:
4374 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rne
4375 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rne
4376 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
4377 ; RV64IZHINX-NEXT: .LBB39_2:
4378 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
4379 ; RV64IZHINX-NEXT: ret
4380 ;
4381 ; RV32IZFHMIN-LABEL: test_roundeven_ui64:
4382 ; RV32IZFHMIN: # %bb.0:
4383 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
4384 ; RV32IZFHMIN-NEXT: lui a0, 307200
4385 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
4386 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
4387 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
4388 ; RV32IZFHMIN-NEXT: beqz a0, .LBB39_2
4389 ; RV32IZFHMIN-NEXT: # %bb.1:
4390 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
4391 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
4392 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
4393 ; RV32IZFHMIN-NEXT: .LBB39_2:
4394 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
4395 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
4396 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
4397 ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
4398 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
4399 ; RV32IZFHMIN-NEXT: call __fixunshfdi
4400 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
4401 ; RV32IZFHMIN-NEXT: .cfi_restore ra
4402 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
4403 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
4404 ; RV32IZFHMIN-NEXT: ret
4405 ;
4406 ; RV64IZFHMIN-LABEL: test_roundeven_ui64:
4407 ; RV64IZFHMIN: # %bb.0:
4408 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
4409 ; RV64IZFHMIN-NEXT: lui a0, 307200
4410 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
4411 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
4412 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
4413 ; RV64IZFHMIN-NEXT: beqz a0, .LBB39_2
4414 ; RV64IZFHMIN-NEXT: # %bb.1:
4415 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
4416 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
4417 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
4418 ; RV64IZFHMIN-NEXT: .LBB39_2:
4419 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
4420 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
4421 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
4422 ; RV64IZFHMIN-NEXT: ret
4423 ;
4424 ; RV32IZHINXMIN-LABEL: test_roundeven_ui64:
4425 ; RV32IZHINXMIN: # %bb.0:
4426 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
4427 ; RV32IZHINXMIN-NEXT: lui a1, 307200
4428 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
4429 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
4430 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB39_2
4431 ; RV32IZHINXMIN-NEXT: # %bb.1:
4432 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
4433 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
4434 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4435 ; RV32IZHINXMIN-NEXT: .LBB39_2:
4436 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
4437 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
4438 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
4439 ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
4440 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
4441 ; RV32IZHINXMIN-NEXT: call __fixunshfdi
4442 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
4443 ; RV32IZHINXMIN-NEXT: .cfi_restore ra
4444 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
4445 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
4446 ; RV32IZHINXMIN-NEXT: ret
4447 ;
4448 ; RV64IZHINXMIN-LABEL: test_roundeven_ui64:
4449 ; RV64IZHINXMIN: # %bb.0:
4450 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
4451 ; RV64IZHINXMIN-NEXT: lui a1, 307200
4452 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
4453 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
4454 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB39_2
4455 ; RV64IZHINXMIN-NEXT: # %bb.1:
4456 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
4457 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
4458 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4459 ; RV64IZHINXMIN-NEXT: .LBB39_2:
4460 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
4461 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
4462 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
4463 ; RV64IZHINXMIN-NEXT: ret
4464 %a = call half @llvm.roundeven.f16(half %x)
4465 %b = fptoui half %a to i64
4466 ret i64 %b
4467 }
4469 define half @test_floor_half(half %x) {
4470 ; RV32IFD-LABEL: test_floor_half:
4471 ; RV32IFD: # %bb.0:
4472 ; RV32IFD-NEXT: addi sp, sp, -16
4473 ; RV32IFD-NEXT: .cfi_def_cfa_offset 16
4474 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
4475 ; RV32IFD-NEXT: .cfi_offset ra, -4
4476 ; RV32IFD-NEXT: call floor@plt
4477 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
4478 ; RV32IFD-NEXT: addi sp, sp, 16
4479 ; RV32IFD-NEXT: ret
4480 ;
4481 ; RV64IFD-LABEL: test_floor_half:
4482 ; RV64IFD: # %bb.0:
4483 ; RV64IFD-NEXT: addi sp, sp, -16
4484 ; RV64IFD-NEXT: .cfi_def_cfa_offset 16
4485 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
4486 ; RV64IFD-NEXT: .cfi_offset ra, -8
4487 ; RV64IFD-NEXT: call floor@plt
4488 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
4489 ; RV64IFD-NEXT: addi sp, sp, 16
4490 ; RV64IFD-NEXT: ret
4491 ; CHECKIZFH-LABEL: test_floor_half:
4492 ; CHECKIZFH: # %bb.0:
4493 ; CHECKIZFH-NEXT: lui a0, %hi(.LCPI40_0)
4494 ; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI40_0)(a0)
4495 ; CHECKIZFH-NEXT: fabs.h fa4, fa0
4496 ; CHECKIZFH-NEXT: flt.h a0, fa4, fa5
4497 ; CHECKIZFH-NEXT: beqz a0, .LBB40_2
4498 ; CHECKIZFH-NEXT: # %bb.1:
4499 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rdn
4500 ; CHECKIZFH-NEXT: fcvt.h.w fa5, a0, rdn
4501 ; CHECKIZFH-NEXT: fsgnj.h fa0, fa5, fa0
4502 ; CHECKIZFH-NEXT: .LBB40_2:
4503 ; CHECKIZFH-NEXT: ret
4504 ;
4505 ; CHECKIZHINX-LABEL: test_floor_half:
4506 ; CHECKIZHINX: # %bb.0:
4507 ; CHECKIZHINX-NEXT: li a1, 25
4508 ; CHECKIZHINX-NEXT: slli a1, a1, 10
4509 ; CHECKIZHINX-NEXT: fabs.h a2, a0
4510 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
4511 ; CHECKIZHINX-NEXT: beqz a1, .LBB40_2
4512 ; CHECKIZHINX-NEXT: # %bb.1:
4513 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rdn
4514 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rdn
4515 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
4516 ; CHECKIZHINX-NEXT: .LBB40_2:
4517 ; CHECKIZHINX-NEXT: ret
4518 ;
4519 ; CHECKIZFHMIN-LABEL: test_floor_half:
4520 ; CHECKIZFHMIN: # %bb.0:
4521 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
4522 ; CHECKIZFHMIN-NEXT: lui a0, 307200
4523 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
4524 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
4525 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
4526 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB40_2
4527 ; CHECKIZFHMIN-NEXT: # %bb.1:
4528 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
4529 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
4530 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
4531 ; CHECKIZFHMIN-NEXT: .LBB40_2:
4532 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
4533 ; CHECKIZFHMIN-NEXT: ret
4534 ;
4535 ; CHECKIZHINXMIN-LABEL: test_floor_half:
4536 ; CHECKIZHINXMIN: # %bb.0:
4537 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
4538 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
4539 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
4540 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
4541 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB40_2
4542 ; CHECKIZHINXMIN-NEXT: # %bb.1:
4543 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
4544 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
4545 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4546 ; CHECKIZHINXMIN-NEXT: .LBB40_2:
4547 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
4548 ; CHECKIZHINXMIN-NEXT: ret
4549 %a = call half @llvm.floor.f16(half %x)
4550 ret half %a
4551 }
4553 define half @test_ceil_half(half %x) {
4554 ; RV32IFD-LABEL: test_ceil_half:
4555 ; RV32IFD: # %bb.0:
4556 ; RV32IFD-NEXT: addi sp, sp, -16
4557 ; RV32IFD-NEXT: .cfi_def_cfa_offset 16
4558 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
4559 ; RV32IFD-NEXT: .cfi_offset ra, -4
4560 ; RV32IFD-NEXT: call ceil@plt
4561 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
4562 ; RV32IFD-NEXT: addi sp, sp, 16
4563 ; RV32IFD-NEXT: ret
4564 ;
4565 ; RV64IFD-LABEL: test_ceil_half:
4566 ; RV64IFD: # %bb.0:
4567 ; RV64IFD-NEXT: addi sp, sp, -16
4568 ; RV64IFD-NEXT: .cfi_def_cfa_offset 16
4569 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
4570 ; RV64IFD-NEXT: .cfi_offset ra, -8
4571 ; RV64IFD-NEXT: call ceil@plt
4572 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
4573 ; RV64IFD-NEXT: addi sp, sp, 16
4574 ; RV64IFD-NEXT: ret
4575 ; CHECKIZFH-LABEL: test_ceil_half:
4576 ; CHECKIZFH: # %bb.0:
4577 ; CHECKIZFH-NEXT: lui a0, %hi(.LCPI41_0)
4578 ; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI41_0)(a0)
4579 ; CHECKIZFH-NEXT: fabs.h fa4, fa0
4580 ; CHECKIZFH-NEXT: flt.h a0, fa4, fa5
4581 ; CHECKIZFH-NEXT: beqz a0, .LBB41_2
4582 ; CHECKIZFH-NEXT: # %bb.1:
4583 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rup
4584 ; CHECKIZFH-NEXT: fcvt.h.w fa5, a0, rup
4585 ; CHECKIZFH-NEXT: fsgnj.h fa0, fa5, fa0
4586 ; CHECKIZFH-NEXT: .LBB41_2:
4587 ; CHECKIZFH-NEXT: ret
4588 ;
4589 ; CHECKIZHINX-LABEL: test_ceil_half:
4590 ; CHECKIZHINX: # %bb.0:
4591 ; CHECKIZHINX-NEXT: li a1, 25
4592 ; CHECKIZHINX-NEXT: slli a1, a1, 10
4593 ; CHECKIZHINX-NEXT: fabs.h a2, a0
4594 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
4595 ; CHECKIZHINX-NEXT: beqz a1, .LBB41_2
4596 ; CHECKIZHINX-NEXT: # %bb.1:
4597 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rup
4598 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rup
4599 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
4600 ; CHECKIZHINX-NEXT: .LBB41_2:
4601 ; CHECKIZHINX-NEXT: ret
4602 ;
4603 ; CHECKIZFHMIN-LABEL: test_ceil_half:
4604 ; CHECKIZFHMIN: # %bb.0:
4605 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
4606 ; CHECKIZFHMIN-NEXT: lui a0, 307200
4607 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
4608 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
4609 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
4610 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB41_2
4611 ; CHECKIZFHMIN-NEXT: # %bb.1:
4612 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
4613 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
4614 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
4615 ; CHECKIZFHMIN-NEXT: .LBB41_2:
4616 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
4617 ; CHECKIZFHMIN-NEXT: ret
4618 ;
4619 ; CHECKIZHINXMIN-LABEL: test_ceil_half:
4620 ; CHECKIZHINXMIN: # %bb.0:
4621 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
4622 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
4623 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
4624 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
4625 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB41_2
4626 ; CHECKIZHINXMIN-NEXT: # %bb.1:
4627 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
4628 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
4629 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4630 ; CHECKIZHINXMIN-NEXT: .LBB41_2:
4631 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
4632 ; CHECKIZHINXMIN-NEXT: ret
4633 %a = call half @llvm.ceil.f16(half %x)
4634 ret half %a
4635 }
4637 define half @test_trunc_half(half %x) {
4638 ; RV32IFD-LABEL: test_trunc_half:
4639 ; RV32IFD: # %bb.0:
4640 ; RV32IFD-NEXT: addi sp, sp, -16
4641 ; RV32IFD-NEXT: .cfi_def_cfa_offset 16
4642 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
4643 ; RV32IFD-NEXT: .cfi_offset ra, -4
4644 ; RV32IFD-NEXT: call trunc@plt
4645 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
4646 ; RV32IFD-NEXT: addi sp, sp, 16
4647 ; RV32IFD-NEXT: ret
4648 ;
4649 ; RV64IFD-LABEL: test_trunc_half:
4650 ; RV64IFD: # %bb.0:
4651 ; RV64IFD-NEXT: addi sp, sp, -16
4652 ; RV64IFD-NEXT: .cfi_def_cfa_offset 16
4653 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
4654 ; RV64IFD-NEXT: .cfi_offset ra, -8
4655 ; RV64IFD-NEXT: call trunc@plt
4656 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
4657 ; RV64IFD-NEXT: addi sp, sp, 16
4658 ; RV64IFD-NEXT: ret
4659 ; CHECKIZFH-LABEL: test_trunc_half:
4660 ; CHECKIZFH: # %bb.0:
4661 ; CHECKIZFH-NEXT: lui a0, %hi(.LCPI42_0)
4662 ; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI42_0)(a0)
4663 ; CHECKIZFH-NEXT: fabs.h fa4, fa0
4664 ; CHECKIZFH-NEXT: flt.h a0, fa4, fa5
4665 ; CHECKIZFH-NEXT: beqz a0, .LBB42_2
4666 ; CHECKIZFH-NEXT: # %bb.1:
4667 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rtz
4668 ; CHECKIZFH-NEXT: fcvt.h.w fa5, a0, rtz
4669 ; CHECKIZFH-NEXT: fsgnj.h fa0, fa5, fa0
4670 ; CHECKIZFH-NEXT: .LBB42_2:
4671 ; CHECKIZFH-NEXT: ret
4672 ;
4673 ; CHECKIZHINX-LABEL: test_trunc_half:
4674 ; CHECKIZHINX: # %bb.0:
4675 ; CHECKIZHINX-NEXT: li a1, 25
4676 ; CHECKIZHINX-NEXT: slli a1, a1, 10
4677 ; CHECKIZHINX-NEXT: fabs.h a2, a0
4678 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
4679 ; CHECKIZHINX-NEXT: beqz a1, .LBB42_2
4680 ; CHECKIZHINX-NEXT: # %bb.1:
4681 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rtz
4682 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rtz
4683 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
4684 ; CHECKIZHINX-NEXT: .LBB42_2:
4685 ; CHECKIZHINX-NEXT: ret
4686 ;
4687 ; CHECKIZFHMIN-LABEL: test_trunc_half:
4688 ; CHECKIZFHMIN: # %bb.0:
4689 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
4690 ; CHECKIZFHMIN-NEXT: lui a0, 307200
4691 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
4692 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
4693 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
4694 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB42_2
4695 ; CHECKIZFHMIN-NEXT: # %bb.1:
4696 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
4697 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
4698 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
4699 ; CHECKIZFHMIN-NEXT: .LBB42_2:
4700 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
4701 ; CHECKIZFHMIN-NEXT: ret
4702 ;
4703 ; CHECKIZHINXMIN-LABEL: test_trunc_half:
4704 ; CHECKIZHINXMIN: # %bb.0:
4705 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
4706 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
4707 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
4708 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
4709 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB42_2
4710 ; CHECKIZHINXMIN-NEXT: # %bb.1:
4711 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
4712 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
4713 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4714 ; CHECKIZHINXMIN-NEXT: .LBB42_2:
4715 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
4716 ; CHECKIZHINXMIN-NEXT: ret
4717 %a = call half @llvm.trunc.f16(half %x)
4718 ret half %a
4719 }
4721 define half @test_round_half(half %x) {
4722 ; RV32IFD-LABEL: test_round_half:
4723 ; RV32IFD: # %bb.0:
4724 ; RV32IFD-NEXT: addi sp, sp, -16
4725 ; RV32IFD-NEXT: .cfi_def_cfa_offset 16
4726 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
4727 ; RV32IFD-NEXT: .cfi_offset ra, -4
4728 ; RV32IFD-NEXT: call round@plt
4729 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
4730 ; RV32IFD-NEXT: addi sp, sp, 16
4731 ; RV32IFD-NEXT: ret
4732 ;
4733 ; RV64IFD-LABEL: test_round_half:
4734 ; RV64IFD: # %bb.0:
4735 ; RV64IFD-NEXT: addi sp, sp, -16
4736 ; RV64IFD-NEXT: .cfi_def_cfa_offset 16
4737 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
4738 ; RV64IFD-NEXT: .cfi_offset ra, -8
4739 ; RV64IFD-NEXT: call round@plt
4740 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
4741 ; RV64IFD-NEXT: addi sp, sp, 16
4742 ; RV64IFD-NEXT: ret
4743 ; CHECKIZFH-LABEL: test_round_half:
4744 ; CHECKIZFH: # %bb.0:
4745 ; CHECKIZFH-NEXT: lui a0, %hi(.LCPI43_0)
4746 ; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI43_0)(a0)
4747 ; CHECKIZFH-NEXT: fabs.h fa4, fa0
4748 ; CHECKIZFH-NEXT: flt.h a0, fa4, fa5
4749 ; CHECKIZFH-NEXT: beqz a0, .LBB43_2
4750 ; CHECKIZFH-NEXT: # %bb.1:
4751 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rmm
4752 ; CHECKIZFH-NEXT: fcvt.h.w fa5, a0, rmm
4753 ; CHECKIZFH-NEXT: fsgnj.h fa0, fa5, fa0
4754 ; CHECKIZFH-NEXT: .LBB43_2:
4755 ; CHECKIZFH-NEXT: ret
4756 ;
4757 ; CHECKIZHINX-LABEL: test_round_half:
4758 ; CHECKIZHINX: # %bb.0:
4759 ; CHECKIZHINX-NEXT: li a1, 25
4760 ; CHECKIZHINX-NEXT: slli a1, a1, 10
4761 ; CHECKIZHINX-NEXT: fabs.h a2, a0
4762 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
4763 ; CHECKIZHINX-NEXT: beqz a1, .LBB43_2
4764 ; CHECKIZHINX-NEXT: # %bb.1:
4765 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rmm
4766 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rmm
4767 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
4768 ; CHECKIZHINX-NEXT: .LBB43_2:
4769 ; CHECKIZHINX-NEXT: ret
4770 ;
4771 ; CHECKIZFHMIN-LABEL: test_round_half:
4772 ; CHECKIZFHMIN: # %bb.0:
4773 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
4774 ; CHECKIZFHMIN-NEXT: lui a0, 307200
4775 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
4776 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
4777 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
4778 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB43_2
4779 ; CHECKIZFHMIN-NEXT: # %bb.1:
4780 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
4781 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
4782 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
4783 ; CHECKIZFHMIN-NEXT: .LBB43_2:
4784 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
4785 ; CHECKIZFHMIN-NEXT: ret
4786 ;
4787 ; CHECKIZHINXMIN-LABEL: test_round_half:
4788 ; CHECKIZHINXMIN: # %bb.0:
4789 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
4790 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
4791 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
4792 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
4793 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB43_2
4794 ; CHECKIZHINXMIN-NEXT: # %bb.1:
4795 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
4796 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
4797 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4798 ; CHECKIZHINXMIN-NEXT: .LBB43_2:
4799 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
4800 ; CHECKIZHINXMIN-NEXT: ret
4801 %a = call half @llvm.round.f16(half %x)
4802 ret half %a
4803 }
4805 define half @test_roundeven_half(half %x) {
4806 ; RV32IFD-LABEL: test_roundeven_half:
4807 ; RV32IFD: # %bb.0:
4808 ; RV32IFD-NEXT: addi sp, sp, -16
4809 ; RV32IFD-NEXT: .cfi_def_cfa_offset 16
4810 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
4811 ; RV32IFD-NEXT: .cfi_offset ra, -4
4812 ; RV32IFD-NEXT: call roundeven@plt
4813 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
4814 ; RV32IFD-NEXT: addi sp, sp, 16
4815 ; RV32IFD-NEXT: ret
4816 ;
4817 ; RV64IFD-LABEL: test_roundeven_half:
4818 ; RV64IFD: # %bb.0:
4819 ; RV64IFD-NEXT: addi sp, sp, -16
4820 ; RV64IFD-NEXT: .cfi_def_cfa_offset 16
4821 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
4822 ; RV64IFD-NEXT: .cfi_offset ra, -8
4823 ; RV64IFD-NEXT: call roundeven@plt
4824 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
4825 ; RV64IFD-NEXT: addi sp, sp, 16
4826 ; RV64IFD-NEXT: ret
4827 ; CHECKIZFH-LABEL: test_roundeven_half:
4828 ; CHECKIZFH: # %bb.0:
4829 ; CHECKIZFH-NEXT: lui a0, %hi(.LCPI44_0)
4830 ; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI44_0)(a0)
4831 ; CHECKIZFH-NEXT: fabs.h fa4, fa0
4832 ; CHECKIZFH-NEXT: flt.h a0, fa4, fa5
4833 ; CHECKIZFH-NEXT: beqz a0, .LBB44_2
4834 ; CHECKIZFH-NEXT: # %bb.1:
4835 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rne
4836 ; CHECKIZFH-NEXT: fcvt.h.w fa5, a0, rne
4837 ; CHECKIZFH-NEXT: fsgnj.h fa0, fa5, fa0
4838 ; CHECKIZFH-NEXT: .LBB44_2:
4839 ; CHECKIZFH-NEXT: ret
4840 ;
4841 ; CHECKIZHINX-LABEL: test_roundeven_half:
4842 ; CHECKIZHINX: # %bb.0:
4843 ; CHECKIZHINX-NEXT: li a1, 25
4844 ; CHECKIZHINX-NEXT: slli a1, a1, 10
4845 ; CHECKIZHINX-NEXT: fabs.h a2, a0
4846 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
4847 ; CHECKIZHINX-NEXT: beqz a1, .LBB44_2
4848 ; CHECKIZHINX-NEXT: # %bb.1:
4849 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rne
4850 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rne
4851 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
4852 ; CHECKIZHINX-NEXT: .LBB44_2:
4853 ; CHECKIZHINX-NEXT: ret
4854 ;
4855 ; CHECKIZFHMIN-LABEL: test_roundeven_half:
4856 ; CHECKIZFHMIN: # %bb.0:
4857 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
4858 ; CHECKIZFHMIN-NEXT: lui a0, 307200
4859 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
4860 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
4861 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
4862 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB44_2
4863 ; CHECKIZFHMIN-NEXT: # %bb.1:
4864 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
4865 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
4866 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
4867 ; CHECKIZFHMIN-NEXT: .LBB44_2:
4868 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
4869 ; CHECKIZFHMIN-NEXT: ret
4870 ;
4871 ; CHECKIZHINXMIN-LABEL: test_roundeven_half:
4872 ; CHECKIZHINXMIN: # %bb.0:
4873 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
4874 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
4875 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
4876 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
4877 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB44_2
4878 ; CHECKIZHINXMIN-NEXT: # %bb.1:
4879 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
4880 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
4881 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4882 ; CHECKIZHINXMIN-NEXT: .LBB44_2:
4883 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
4884 ; CHECKIZHINXMIN-NEXT: ret
4885 %a = call half @llvm.roundeven.f16(half %x)
4886 ret half %a
4887 }
4889 declare half @llvm.floor.f16(half)
4890 declare half @llvm.ceil.f16(half)
4891 declare half @llvm.trunc.f16(half)
4892 declare half @llvm.round.f16(half)
4893 declare half @llvm.roundeven.f16(half)