| blob | e387586cd46c27e7a4ed3dad8ebc3d328e5acdbe |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv64 -target-abi=lp64 -verify-machineinstrs < %s \
3 ; RUN: | FileCheck %s -check-prefixes=CHECK,RV64I
4 ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s \
5 ; RUN: | FileCheck %s -check-prefixes=CHECK,RV64IF
6 ; RUN: llc -mtriple=riscv64 -mattr=+zfinx -target-abi=lp64 -verify-machineinstrs < %s \
7 ; RUN: | FileCheck %s -check-prefixes=CHECK,RV64IZFINX
9 define i128 @fptosi_f32_to_i128(float %a) nounwind {
10 ; CHECK-LABEL: fptosi_f32_to_i128:
11 ; CHECK: # %bb.0:
12 ; CHECK-NEXT: addi sp, sp, -16
13 ; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
14 ; CHECK-NEXT: call __fixsfti
15 ; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
16 ; CHECK-NEXT: addi sp, sp, 16
17 ; CHECK-NEXT: ret
18 %1 = fptosi float %a to i128
19 ret i128 %1
20 }
22 define i128 @fptoui_f32_to_i128(float %a) nounwind {
23 ; CHECK-LABEL: fptoui_f32_to_i128:
24 ; CHECK: # %bb.0:
25 ; CHECK-NEXT: addi sp, sp, -16
26 ; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
27 ; CHECK-NEXT: call __fixunssfti
28 ; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
29 ; CHECK-NEXT: addi sp, sp, 16
30 ; CHECK-NEXT: ret
31 %1 = fptoui float %a to i128
32 ret i128 %1
33 }
35 define float @sitofp_i128_to_f32(i128 %a) nounwind {
36 ; CHECK-LABEL: sitofp_i128_to_f32:
37 ; CHECK: # %bb.0:
38 ; CHECK-NEXT: addi sp, sp, -16
39 ; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
40 ; CHECK-NEXT: call __floattisf
41 ; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
42 ; CHECK-NEXT: addi sp, sp, 16
43 ; CHECK-NEXT: ret
44 %1 = sitofp i128 %a to float
45 ret float %1
46 }
48 define float @uitofp_i128_to_f32(i128 %a) nounwind {
49 ; CHECK-LABEL: uitofp_i128_to_f32:
50 ; CHECK: # %bb.0:
51 ; CHECK-NEXT: addi sp, sp, -16
52 ; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
53 ; CHECK-NEXT: call __floatuntisf
54 ; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
55 ; CHECK-NEXT: addi sp, sp, 16
56 ; CHECK-NEXT: ret
57 %1 = uitofp i128 %a to float
58 ret float %1
59 }
61 define i128 @fptosi_sat_f32_to_i128(float %a) nounwind {
62 ; RV64I-LABEL: fptosi_sat_f32_to_i128:
63 ; RV64I: # %bb.0:
64 ; RV64I-NEXT: addi sp, sp, -64
65 ; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
66 ; RV64I-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
67 ; RV64I-NEXT: sd s1, 40(sp) # 8-byte Folded Spill
68 ; RV64I-NEXT: sd s2, 32(sp) # 8-byte Folded Spill
69 ; RV64I-NEXT: sd s3, 24(sp) # 8-byte Folded Spill
70 ; RV64I-NEXT: sd s4, 16(sp) # 8-byte Folded Spill
71 ; RV64I-NEXT: sd s5, 8(sp) # 8-byte Folded Spill
72 ; RV64I-NEXT: mv s1, a0
73 ; RV64I-NEXT: lui a1, 1044480
74 ; RV64I-NEXT: call __gesf2
75 ; RV64I-NEXT: mv s2, a0
76 ; RV64I-NEXT: mv a0, s1
77 ; RV64I-NEXT: call __fixsfti
78 ; RV64I-NEXT: mv s0, a0
79 ; RV64I-NEXT: mv s3, a1
80 ; RV64I-NEXT: li s5, -1
81 ; RV64I-NEXT: bgez s2, .LBB4_2
82 ; RV64I-NEXT: # %bb.1:
83 ; RV64I-NEXT: slli s3, s5, 63
84 ; RV64I-NEXT: .LBB4_2:
85 ; RV64I-NEXT: lui a1, 520192
86 ; RV64I-NEXT: addiw a1, a1, -1
87 ; RV64I-NEXT: mv a0, s1
88 ; RV64I-NEXT: call __gtsf2
89 ; RV64I-NEXT: mv s4, a0
90 ; RV64I-NEXT: blez a0, .LBB4_4
91 ; RV64I-NEXT: # %bb.3:
92 ; RV64I-NEXT: srli s3, s5, 1
93 ; RV64I-NEXT: .LBB4_4:
94 ; RV64I-NEXT: mv a0, s1
95 ; RV64I-NEXT: mv a1, s1
96 ; RV64I-NEXT: call __unordsf2
97 ; RV64I-NEXT: snez a0, a0
98 ; RV64I-NEXT: slti a1, s2, 0
99 ; RV64I-NEXT: sgtz a2, s4
100 ; RV64I-NEXT: addi a0, a0, -1
101 ; RV64I-NEXT: addi a3, a1, -1
102 ; RV64I-NEXT: and a1, a0, s3
103 ; RV64I-NEXT: and a3, a3, s0
104 ; RV64I-NEXT: neg a2, a2
105 ; RV64I-NEXT: or a2, a2, a3
106 ; RV64I-NEXT: and a0, a0, a2
107 ; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
108 ; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
109 ; RV64I-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
110 ; RV64I-NEXT: ld s2, 32(sp) # 8-byte Folded Reload
111 ; RV64I-NEXT: ld s3, 24(sp) # 8-byte Folded Reload
112 ; RV64I-NEXT: ld s4, 16(sp) # 8-byte Folded Reload
113 ; RV64I-NEXT: ld s5, 8(sp) # 8-byte Folded Reload
114 ; RV64I-NEXT: addi sp, sp, 64
115 ; RV64I-NEXT: ret
116 ;
117 ; RV64IF-LABEL: fptosi_sat_f32_to_i128:
118 ; RV64IF: # %bb.0:
119 ; RV64IF-NEXT: addi sp, sp, -32
120 ; RV64IF-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
121 ; RV64IF-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
122 ; RV64IF-NEXT: fsw fs0, 12(sp) # 4-byte Folded Spill
123 ; RV64IF-NEXT: fmv.s fs0, fa0
124 ; RV64IF-NEXT: lui a0, 1044480
125 ; RV64IF-NEXT: fmv.w.x fa5, a0
126 ; RV64IF-NEXT: fle.s s0, fa5, fa0
127 ; RV64IF-NEXT: call __fixsfti
128 ; RV64IF-NEXT: li a3, -1
129 ; RV64IF-NEXT: bnez s0, .LBB4_2
130 ; RV64IF-NEXT: # %bb.1:
131 ; RV64IF-NEXT: slli a1, a3, 63
132 ; RV64IF-NEXT: .LBB4_2:
133 ; RV64IF-NEXT: lui a2, %hi(.LCPI4_0)
134 ; RV64IF-NEXT: flw fa5, %lo(.LCPI4_0)(a2)
135 ; RV64IF-NEXT: flt.s a2, fa5, fs0
136 ; RV64IF-NEXT: beqz a2, .LBB4_4
137 ; RV64IF-NEXT: # %bb.3:
138 ; RV64IF-NEXT: srli a1, a3, 1
139 ; RV64IF-NEXT: .LBB4_4:
140 ; RV64IF-NEXT: feq.s a3, fs0, fs0
141 ; RV64IF-NEXT: neg a4, s0
142 ; RV64IF-NEXT: neg a2, a2
143 ; RV64IF-NEXT: neg a3, a3
144 ; RV64IF-NEXT: and a0, a4, a0
145 ; RV64IF-NEXT: and a1, a3, a1
146 ; RV64IF-NEXT: or a0, a2, a0
147 ; RV64IF-NEXT: and a0, a3, a0
148 ; RV64IF-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
149 ; RV64IF-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
150 ; RV64IF-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload
151 ; RV64IF-NEXT: addi sp, sp, 32
152 ; RV64IF-NEXT: ret
153 ;
154 ; RV64IZFINX-LABEL: fptosi_sat_f32_to_i128:
155 ; RV64IZFINX: # %bb.0:
156 ; RV64IZFINX-NEXT: addi sp, sp, -32
157 ; RV64IZFINX-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
158 ; RV64IZFINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
159 ; RV64IZFINX-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
160 ; RV64IZFINX-NEXT: mv s0, a0
161 ; RV64IZFINX-NEXT: lui a0, 1044480
162 ; RV64IZFINX-NEXT: fle.s s1, a0, s0
163 ; RV64IZFINX-NEXT: mv a0, s0
164 ; RV64IZFINX-NEXT: call __fixsfti
165 ; RV64IZFINX-NEXT: li a2, -1
166 ; RV64IZFINX-NEXT: bnez s1, .LBB4_2
167 ; RV64IZFINX-NEXT: # %bb.1:
168 ; RV64IZFINX-NEXT: slli a1, a2, 63
169 ; RV64IZFINX-NEXT: .LBB4_2:
170 ; RV64IZFINX-NEXT: lui a3, 520192
171 ; RV64IZFINX-NEXT: addiw a3, a3, -1
172 ; RV64IZFINX-NEXT: flt.s a3, a3, s0
173 ; RV64IZFINX-NEXT: beqz a3, .LBB4_4
174 ; RV64IZFINX-NEXT: # %bb.3:
175 ; RV64IZFINX-NEXT: srli a1, a2, 1
176 ; RV64IZFINX-NEXT: .LBB4_4:
177 ; RV64IZFINX-NEXT: feq.s a2, s0, s0
178 ; RV64IZFINX-NEXT: neg a4, s1
179 ; RV64IZFINX-NEXT: neg a3, a3
180 ; RV64IZFINX-NEXT: neg a2, a2
181 ; RV64IZFINX-NEXT: and a0, a4, a0
182 ; RV64IZFINX-NEXT: and a1, a2, a1
183 ; RV64IZFINX-NEXT: or a0, a3, a0
184 ; RV64IZFINX-NEXT: and a0, a2, a0
185 ; RV64IZFINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
186 ; RV64IZFINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
187 ; RV64IZFINX-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
188 ; RV64IZFINX-NEXT: addi sp, sp, 32
189 ; RV64IZFINX-NEXT: ret
190 %1 = tail call i128 @llvm.fptosi.sat.i128.f32(float %a)
191 ret i128 %1
192 }
193 declare i128 @llvm.fptosi.sat.i128.f32(float)
195 define i128 @fptoui_sat_f32_to_i128(float %a) nounwind {
196 ; RV64I-LABEL: fptoui_sat_f32_to_i128:
197 ; RV64I: # %bb.0:
198 ; RV64I-NEXT: addi sp, sp, -32
199 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
200 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
201 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
202 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
203 ; RV64I-NEXT: mv s0, a0
204 ; RV64I-NEXT: lui a1, 522240
205 ; RV64I-NEXT: addiw a1, a1, -1
206 ; RV64I-NEXT: call __gtsf2
207 ; RV64I-NEXT: sgtz a0, a0
208 ; RV64I-NEXT: neg s1, a0
209 ; RV64I-NEXT: mv a0, s0
210 ; RV64I-NEXT: li a1, 0
211 ; RV64I-NEXT: call __gesf2
212 ; RV64I-NEXT: slti a0, a0, 0
213 ; RV64I-NEXT: addi s2, a0, -1
214 ; RV64I-NEXT: mv a0, s0
215 ; RV64I-NEXT: call __fixunssfti
216 ; RV64I-NEXT: and a0, s2, a0
217 ; RV64I-NEXT: and a1, s2, a1
218 ; RV64I-NEXT: or a0, s1, a0
219 ; RV64I-NEXT: or a1, s1, a1
220 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
221 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
222 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
223 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
224 ; RV64I-NEXT: addi sp, sp, 32
225 ; RV64I-NEXT: ret
226 ;
227 ; RV64IF-LABEL: fptoui_sat_f32_to_i128:
228 ; RV64IF: # %bb.0:
229 ; RV64IF-NEXT: addi sp, sp, -32
230 ; RV64IF-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
231 ; RV64IF-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
232 ; RV64IF-NEXT: fsw fs0, 12(sp) # 4-byte Folded Spill
233 ; RV64IF-NEXT: fmv.s fs0, fa0
234 ; RV64IF-NEXT: fmv.w.x fa5, zero
235 ; RV64IF-NEXT: fle.s a0, fa5, fa0
236 ; RV64IF-NEXT: neg s0, a0
237 ; RV64IF-NEXT: call __fixunssfti
238 ; RV64IF-NEXT: lui a2, %hi(.LCPI5_0)
239 ; RV64IF-NEXT: flw fa5, %lo(.LCPI5_0)(a2)
240 ; RV64IF-NEXT: and a0, s0, a0
241 ; RV64IF-NEXT: and a1, s0, a1
242 ; RV64IF-NEXT: flt.s a2, fa5, fs0
243 ; RV64IF-NEXT: neg a2, a2
244 ; RV64IF-NEXT: or a0, a2, a0
245 ; RV64IF-NEXT: or a1, a2, a1
246 ; RV64IF-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
247 ; RV64IF-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
248 ; RV64IF-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload
249 ; RV64IF-NEXT: addi sp, sp, 32
250 ; RV64IF-NEXT: ret
251 ;
252 ; RV64IZFINX-LABEL: fptoui_sat_f32_to_i128:
253 ; RV64IZFINX: # %bb.0:
254 ; RV64IZFINX-NEXT: addi sp, sp, -32
255 ; RV64IZFINX-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
256 ; RV64IZFINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
257 ; RV64IZFINX-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
258 ; RV64IZFINX-NEXT: mv s0, a0
259 ; RV64IZFINX-NEXT: fle.s a0, zero, a0
260 ; RV64IZFINX-NEXT: neg s1, a0
261 ; RV64IZFINX-NEXT: mv a0, s0
262 ; RV64IZFINX-NEXT: call __fixunssfti
263 ; RV64IZFINX-NEXT: and a0, s1, a0
264 ; RV64IZFINX-NEXT: lui a2, 522240
265 ; RV64IZFINX-NEXT: and a1, s1, a1
266 ; RV64IZFINX-NEXT: addiw a2, a2, -1
267 ; RV64IZFINX-NEXT: flt.s a2, a2, s0
268 ; RV64IZFINX-NEXT: neg a2, a2
269 ; RV64IZFINX-NEXT: or a0, a2, a0
270 ; RV64IZFINX-NEXT: or a1, a2, a1
271 ; RV64IZFINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
272 ; RV64IZFINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
273 ; RV64IZFINX-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
274 ; RV64IZFINX-NEXT: addi sp, sp, 32
275 ; RV64IZFINX-NEXT: ret
276 %1 = tail call i128 @llvm.fptoui.sat.i128.f32(float %a)
277 ret i128 %1
278 }
279 declare i128 @llvm.fptoui.sat.i128.f32(float)