[TTI] getTypeBasedIntrinsicInstrCost - add basic handling for strided load/store...
[llvm-project.git] / llvm / test / CodeGen / RISCV / rvv / allone-masked-to-unmasked.mir
blob97654c050f81cbc95a4f5937dcd1890629b1cbe2
1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2 # RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vector-peephole -verify-machineinstrs | FileCheck %s
4 # Take into account that the masked vcpop pseudo doesn't have a passthru
5 ---
6 name: vcpop.m
7 body: |
8   bb.0:
9     ; CHECK-LABEL: name: vcpop.m
10     ; CHECK: %allones:vr = PseudoVMSET_M_B64 $noreg, 0 /* e8 */
11     ; CHECK-NEXT: $v0 = COPY %allones
12     ; CHECK-NEXT: [[PseudoVCPOP_M_B64_:%[0-9]+]]:gpr = PseudoVCPOP_M_B64 $noreg, 42, 0 /* e8 */
13     %allones:vr = PseudoVMSET_M_B64 $noreg, 0
14     $v0 = COPY %allones
15     %2:gpr = PseudoVCPOP_M_B64_MASK $noreg, $v0, 42, 0
16 ...