1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2 ; RUN: llc -verify-machineinstrs -mtriple=riscv32 -mattr=+m,+v %s -o - \
3 ; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32
4 ; RUN: llc -verify-machineinstrs -mtriple=riscv64 -mattr=+m,+v %s -o - \
5 ; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64
7 declare <1 x i8> @llvm.masked.expandload.v1i8(ptr, <1 x i1>, <1 x i8>)
8 define <1 x i8> @expandload_v1i8(ptr %base, <1 x i8> %src0, <1 x i1> %mask) {
9 ; CHECK-LABEL: expandload_v1i8:
11 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
12 ; CHECK-NEXT: vcpop.m a1, v0
13 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
14 ; CHECK-NEXT: vle8.v v9, (a0)
15 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
16 ; CHECK-NEXT: viota.m v10, v0
17 ; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
19 %res = call <1 x i8> @llvm.masked.expandload.v1i8(ptr %base, <1 x i1> %mask, <1 x i8> %src0)
23 declare <2 x i8> @llvm.masked.expandload.v2i8(ptr, <2 x i1>, <2 x i8>)
24 define <2 x i8> @expandload_v2i8(ptr %base, <2 x i8> %src0, <2 x i1> %mask) {
25 ; CHECK-LABEL: expandload_v2i8:
27 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
28 ; CHECK-NEXT: vcpop.m a1, v0
29 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
30 ; CHECK-NEXT: vle8.v v9, (a0)
31 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
32 ; CHECK-NEXT: viota.m v10, v0
33 ; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
35 %res = call <2 x i8> @llvm.masked.expandload.v2i8(ptr %base, <2 x i1> %mask, <2 x i8> %src0)
39 declare <4 x i8> @llvm.masked.expandload.v4i8(ptr, <4 x i1>, <4 x i8>)
40 define <4 x i8> @expandload_v4i8(ptr %base, <4 x i8> %src0, <4 x i1> %mask) {
41 ; CHECK-LABEL: expandload_v4i8:
43 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
44 ; CHECK-NEXT: vcpop.m a1, v0
45 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
46 ; CHECK-NEXT: vle8.v v9, (a0)
47 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
48 ; CHECK-NEXT: viota.m v10, v0
49 ; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
51 %res = call <4 x i8> @llvm.masked.expandload.v4i8(ptr %base, <4 x i1> %mask, <4 x i8> %src0)
55 declare <8 x i8> @llvm.masked.expandload.v8i8(ptr, <8 x i1>, <8 x i8>)
56 define <8 x i8> @expandload_v8i8(ptr %base, <8 x i8> %src0, <8 x i1> %mask) {
57 ; CHECK-LABEL: expandload_v8i8:
59 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
60 ; CHECK-NEXT: vcpop.m a1, v0
61 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
62 ; CHECK-NEXT: vle8.v v9, (a0)
63 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
64 ; CHECK-NEXT: viota.m v10, v0
65 ; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
67 %res = call <8 x i8> @llvm.masked.expandload.v8i8(ptr %base, <8 x i1> %mask, <8 x i8> %src0)
71 declare <1 x i16> @llvm.masked.expandload.v1i16(ptr, <1 x i1>, <1 x i16>)
72 define <1 x i16> @expandload_v1i16(ptr %base, <1 x i16> %src0, <1 x i1> %mask) {
73 ; CHECK-LABEL: expandload_v1i16:
75 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
76 ; CHECK-NEXT: vcpop.m a1, v0
77 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
78 ; CHECK-NEXT: vle16.v v9, (a0)
79 ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
80 ; CHECK-NEXT: viota.m v10, v0
81 ; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
83 %res = call <1 x i16> @llvm.masked.expandload.v1i16(ptr align 2 %base, <1 x i1> %mask, <1 x i16> %src0)
87 declare <2 x i16> @llvm.masked.expandload.v2i16(ptr, <2 x i1>, <2 x i16>)
88 define <2 x i16> @expandload_v2i16(ptr %base, <2 x i16> %src0, <2 x i1> %mask) {
89 ; CHECK-LABEL: expandload_v2i16:
91 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
92 ; CHECK-NEXT: vcpop.m a1, v0
93 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
94 ; CHECK-NEXT: vle16.v v9, (a0)
95 ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
96 ; CHECK-NEXT: viota.m v10, v0
97 ; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
99 %res = call <2 x i16> @llvm.masked.expandload.v2i16(ptr align 2 %base, <2 x i1> %mask, <2 x i16> %src0)
103 declare <4 x i16> @llvm.masked.expandload.v4i16(ptr, <4 x i1>, <4 x i16>)
104 define <4 x i16> @expandload_v4i16(ptr %base, <4 x i16> %src0, <4 x i1> %mask) {
105 ; CHECK-LABEL: expandload_v4i16:
107 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
108 ; CHECK-NEXT: vcpop.m a1, v0
109 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
110 ; CHECK-NEXT: vle16.v v9, (a0)
111 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
112 ; CHECK-NEXT: viota.m v10, v0
113 ; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
115 %res = call <4 x i16> @llvm.masked.expandload.v4i16(ptr align 2 %base, <4 x i1> %mask, <4 x i16> %src0)
119 declare <8 x i16> @llvm.masked.expandload.v8i16(ptr, <8 x i1>, <8 x i16>)
120 define <8 x i16> @expandload_v8i16(ptr %base, <8 x i16> %src0, <8 x i1> %mask) {
121 ; CHECK-LABEL: expandload_v8i16:
123 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
124 ; CHECK-NEXT: vcpop.m a1, v0
125 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
126 ; CHECK-NEXT: vle16.v v9, (a0)
127 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
128 ; CHECK-NEXT: viota.m v10, v0
129 ; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
131 %res = call <8 x i16> @llvm.masked.expandload.v8i16(ptr align 2 %base, <8 x i1> %mask, <8 x i16> %src0)
135 declare <1 x i32> @llvm.masked.expandload.v1i32(ptr, <1 x i1>, <1 x i32>)
136 define <1 x i32> @expandload_v1i32(ptr %base, <1 x i32> %src0, <1 x i1> %mask) {
137 ; CHECK-LABEL: expandload_v1i32:
139 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
140 ; CHECK-NEXT: vcpop.m a1, v0
141 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
142 ; CHECK-NEXT: vle32.v v9, (a0)
143 ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
144 ; CHECK-NEXT: viota.m v10, v0
145 ; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
147 %res = call <1 x i32> @llvm.masked.expandload.v1i32(ptr align 4 %base, <1 x i1> %mask, <1 x i32> %src0)
151 declare <2 x i32> @llvm.masked.expandload.v2i32(ptr, <2 x i1>, <2 x i32>)
152 define <2 x i32> @expandload_v2i32(ptr %base, <2 x i32> %src0, <2 x i1> %mask) {
153 ; CHECK-LABEL: expandload_v2i32:
155 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
156 ; CHECK-NEXT: vcpop.m a1, v0
157 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
158 ; CHECK-NEXT: vle32.v v9, (a0)
159 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
160 ; CHECK-NEXT: viota.m v10, v0
161 ; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
163 %res = call <2 x i32> @llvm.masked.expandload.v2i32(ptr align 4 %base, <2 x i1> %mask, <2 x i32> %src0)
167 declare <4 x i32> @llvm.masked.expandload.v4i32(ptr, <4 x i1>, <4 x i32>)
168 define <4 x i32> @expandload_v4i32(ptr %base, <4 x i32> %src0, <4 x i1> %mask) {
169 ; CHECK-LABEL: expandload_v4i32:
171 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
172 ; CHECK-NEXT: vcpop.m a1, v0
173 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
174 ; CHECK-NEXT: vle32.v v9, (a0)
175 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
176 ; CHECK-NEXT: viota.m v10, v0
177 ; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
179 %res = call <4 x i32> @llvm.masked.expandload.v4i32(ptr align 4 %base, <4 x i1> %mask, <4 x i32> %src0)
183 declare <8 x i32> @llvm.masked.expandload.v8i32(ptr, <8 x i1>, <8 x i32>)
184 define <8 x i32> @expandload_v8i32(ptr %base, <8 x i32> %src0, <8 x i1> %mask) {
185 ; CHECK-LABEL: expandload_v8i32:
187 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
188 ; CHECK-NEXT: vcpop.m a1, v0
189 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
190 ; CHECK-NEXT: vle32.v v10, (a0)
191 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
192 ; CHECK-NEXT: viota.m v12, v0
193 ; CHECK-NEXT: vrgather.vv v8, v10, v12, v0.t
195 %res = call <8 x i32> @llvm.masked.expandload.v8i32(ptr align 4 %base, <8 x i1> %mask, <8 x i32> %src0)
199 declare <1 x i64> @llvm.masked.expandload.v1i64(ptr, <1 x i1>, <1 x i64>)
200 define <1 x i64> @expandload_v1i64(ptr %base, <1 x i64> %src0, <1 x i1> %mask) {
201 ; CHECK-LABEL: expandload_v1i64:
203 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
204 ; CHECK-NEXT: vcpop.m a1, v0
205 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
206 ; CHECK-NEXT: vle64.v v9, (a0)
207 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
208 ; CHECK-NEXT: viota.m v10, v0
209 ; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
211 %res = call <1 x i64> @llvm.masked.expandload.v1i64(ptr align 8 %base, <1 x i1> %mask, <1 x i64> %src0)
215 declare <2 x i64> @llvm.masked.expandload.v2i64(ptr, <2 x i1>, <2 x i64>)
216 define <2 x i64> @expandload_v2i64(ptr %base, <2 x i64> %src0, <2 x i1> %mask) {
217 ; CHECK-LABEL: expandload_v2i64:
219 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
220 ; CHECK-NEXT: vcpop.m a1, v0
221 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
222 ; CHECK-NEXT: vle64.v v9, (a0)
223 ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
224 ; CHECK-NEXT: viota.m v10, v0
225 ; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
227 %res = call <2 x i64> @llvm.masked.expandload.v2i64(ptr align 8 %base, <2 x i1> %mask, <2 x i64> %src0)
231 declare <4 x i64> @llvm.masked.expandload.v4i64(ptr, <4 x i1>, <4 x i64>)
232 define <4 x i64> @expandload_v4i64(ptr %base, <4 x i64> %src0, <4 x i1> %mask) {
233 ; CHECK-LABEL: expandload_v4i64:
235 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
236 ; CHECK-NEXT: vcpop.m a1, v0
237 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
238 ; CHECK-NEXT: vle64.v v10, (a0)
239 ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
240 ; CHECK-NEXT: viota.m v12, v0
241 ; CHECK-NEXT: vrgather.vv v8, v10, v12, v0.t
243 %res = call <4 x i64> @llvm.masked.expandload.v4i64(ptr align 8 %base, <4 x i1> %mask, <4 x i64> %src0)
247 declare <8 x i64> @llvm.masked.expandload.v8i64(ptr, <8 x i1>, <8 x i64>)
248 define <8 x i64> @expandload_v8i64(ptr %base, <8 x i64> %src0, <8 x i1> %mask) {
249 ; CHECK-LABEL: expandload_v8i64:
251 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
252 ; CHECK-NEXT: vcpop.m a1, v0
253 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
254 ; CHECK-NEXT: vle64.v v12, (a0)
255 ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
256 ; CHECK-NEXT: viota.m v16, v0
257 ; CHECK-NEXT: vrgather.vv v8, v12, v16, v0.t
259 %res = call <8 x i64> @llvm.masked.expandload.v8i64(ptr align 8 %base, <8 x i1> %mask, <8 x i64> %src0)
262 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: