1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
3 ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32
4 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
5 ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64
7 declare <2 x i8> @llvm.usub.sat.v2i8(<2 x i8>, <2 x i8>)
9 define <2 x i8> @usub_v2i8_vv(<2 x i8> %va, <2 x i8> %b) {
10 ; CHECK-LABEL: usub_v2i8_vv:
12 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
13 ; CHECK-NEXT: vssubu.vv v8, v8, v9
15 %v = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %va, <2 x i8> %b)
19 define <2 x i8> @usub_v2i8_vx(<2 x i8> %va, i8 %b) {
20 ; CHECK-LABEL: usub_v2i8_vx:
22 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
23 ; CHECK-NEXT: vssubu.vx v8, v8, a0
25 %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
26 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
27 %v = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %va, <2 x i8> %vb)
31 define <2 x i8> @usub_v2i8_vi(<2 x i8> %va) {
32 ; CHECK-LABEL: usub_v2i8_vi:
34 ; CHECK-NEXT: li a0, 2
35 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
36 ; CHECK-NEXT: vssubu.vx v8, v8, a0
38 %v = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 2))
42 declare <4 x i8> @llvm.usub.sat.v4i8(<4 x i8>, <4 x i8>)
44 define <4 x i8> @usub_v4i8_vv(<4 x i8> %va, <4 x i8> %b) {
45 ; CHECK-LABEL: usub_v4i8_vv:
47 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
48 ; CHECK-NEXT: vssubu.vv v8, v8, v9
50 %v = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> %va, <4 x i8> %b)
54 define <4 x i8> @usub_v4i8_vx(<4 x i8> %va, i8 %b) {
55 ; CHECK-LABEL: usub_v4i8_vx:
57 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
58 ; CHECK-NEXT: vssubu.vx v8, v8, a0
60 %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
61 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
62 %v = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> %va, <4 x i8> %vb)
66 define <4 x i8> @usub_v4i8_vi(<4 x i8> %va) {
67 ; CHECK-LABEL: usub_v4i8_vi:
69 ; CHECK-NEXT: li a0, 2
70 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
71 ; CHECK-NEXT: vssubu.vx v8, v8, a0
73 %v = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 2))
77 declare <8 x i8> @llvm.usub.sat.v8i8(<8 x i8>, <8 x i8>)
79 define <8 x i8> @usub_v8i8_vv(<8 x i8> %va, <8 x i8> %b) {
80 ; CHECK-LABEL: usub_v8i8_vv:
82 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
83 ; CHECK-NEXT: vssubu.vv v8, v8, v9
85 %v = call <8 x i8> @llvm.usub.sat.v8i8(<8 x i8> %va, <8 x i8> %b)
89 define <8 x i8> @usub_v8i8_vx(<8 x i8> %va, i8 %b) {
90 ; CHECK-LABEL: usub_v8i8_vx:
92 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
93 ; CHECK-NEXT: vssubu.vx v8, v8, a0
95 %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
96 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
97 %v = call <8 x i8> @llvm.usub.sat.v8i8(<8 x i8> %va, <8 x i8> %vb)
101 define <8 x i8> @usub_v8i8_vi(<8 x i8> %va) {
102 ; CHECK-LABEL: usub_v8i8_vi:
104 ; CHECK-NEXT: li a0, 2
105 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
106 ; CHECK-NEXT: vssubu.vx v8, v8, a0
108 %v = call <8 x i8> @llvm.usub.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 2))
112 declare <16 x i8> @llvm.usub.sat.v16i8(<16 x i8>, <16 x i8>)
114 define <16 x i8> @usub_v16i8_vv(<16 x i8> %va, <16 x i8> %b) {
115 ; CHECK-LABEL: usub_v16i8_vv:
117 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
118 ; CHECK-NEXT: vssubu.vv v8, v8, v9
120 %v = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %va, <16 x i8> %b)
124 define <16 x i8> @usub_v16i8_vx(<16 x i8> %va, i8 %b) {
125 ; CHECK-LABEL: usub_v16i8_vx:
127 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
128 ; CHECK-NEXT: vssubu.vx v8, v8, a0
130 %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
131 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer
132 %v = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %va, <16 x i8> %vb)
136 define <16 x i8> @usub_v16i8_vi(<16 x i8> %va) {
137 ; CHECK-LABEL: usub_v16i8_vi:
139 ; CHECK-NEXT: li a0, 2
140 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
141 ; CHECK-NEXT: vssubu.vx v8, v8, a0
143 %v = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 2))
147 declare <2 x i16> @llvm.usub.sat.v2i16(<2 x i16>, <2 x i16>)
149 define <2 x i16> @usub_v2i16_vv(<2 x i16> %va, <2 x i16> %b) {
150 ; CHECK-LABEL: usub_v2i16_vv:
152 ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
153 ; CHECK-NEXT: vssubu.vv v8, v8, v9
155 %v = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %va, <2 x i16> %b)
159 define <2 x i16> @usub_v2i16_vx(<2 x i16> %va, i16 %b) {
160 ; CHECK-LABEL: usub_v2i16_vx:
162 ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
163 ; CHECK-NEXT: vssubu.vx v8, v8, a0
165 %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
166 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer
167 %v = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %va, <2 x i16> %vb)
171 define <2 x i16> @usub_v2i16_vi(<2 x i16> %va) {
172 ; CHECK-LABEL: usub_v2i16_vi:
174 ; CHECK-NEXT: li a0, 2
175 ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
176 ; CHECK-NEXT: vssubu.vx v8, v8, a0
178 %v = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 2))
182 declare <4 x i16> @llvm.usub.sat.v4i16(<4 x i16>, <4 x i16>)
184 define <4 x i16> @usub_v4i16_vv(<4 x i16> %va, <4 x i16> %b) {
185 ; CHECK-LABEL: usub_v4i16_vv:
187 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
188 ; CHECK-NEXT: vssubu.vv v8, v8, v9
190 %v = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %va, <4 x i16> %b)
194 define <4 x i16> @usub_v4i16_vx(<4 x i16> %va, i16 %b) {
195 ; CHECK-LABEL: usub_v4i16_vx:
197 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
198 ; CHECK-NEXT: vssubu.vx v8, v8, a0
200 %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
201 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer
202 %v = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %va, <4 x i16> %vb)
206 define <4 x i16> @usub_v4i16_vi(<4 x i16> %va) {
207 ; CHECK-LABEL: usub_v4i16_vi:
209 ; CHECK-NEXT: li a0, 2
210 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
211 ; CHECK-NEXT: vssubu.vx v8, v8, a0
213 %v = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 2))
217 declare <8 x i16> @llvm.usub.sat.v8i16(<8 x i16>, <8 x i16>)
219 define <8 x i16> @usub_v8i16_vv(<8 x i16> %va, <8 x i16> %b) {
220 ; CHECK-LABEL: usub_v8i16_vv:
222 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
223 ; CHECK-NEXT: vssubu.vv v8, v8, v9
225 %v = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %va, <8 x i16> %b)
229 define <8 x i16> @usub_v8i16_vx(<8 x i16> %va, i16 %b) {
230 ; CHECK-LABEL: usub_v8i16_vx:
232 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
233 ; CHECK-NEXT: vssubu.vx v8, v8, a0
235 %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
236 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
237 %v = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %va, <8 x i16> %vb)
241 define <8 x i16> @usub_v8i16_vi(<8 x i16> %va) {
242 ; CHECK-LABEL: usub_v8i16_vi:
244 ; CHECK-NEXT: li a0, 2
245 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
246 ; CHECK-NEXT: vssubu.vx v8, v8, a0
248 %v = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 2))
252 declare <16 x i16> @llvm.usub.sat.v16i16(<16 x i16>, <16 x i16>)
254 define <16 x i16> @usub_v16i16_vv(<16 x i16> %va, <16 x i16> %b) {
255 ; CHECK-LABEL: usub_v16i16_vv:
257 ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
258 ; CHECK-NEXT: vssubu.vv v8, v8, v10
260 %v = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> %va, <16 x i16> %b)
264 define <16 x i16> @usub_v16i16_vx(<16 x i16> %va, i16 %b) {
265 ; CHECK-LABEL: usub_v16i16_vx:
267 ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
268 ; CHECK-NEXT: vssubu.vx v8, v8, a0
270 %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
271 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer
272 %v = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> %va, <16 x i16> %vb)
276 define <16 x i16> @usub_v16i16_vi(<16 x i16> %va) {
277 ; CHECK-LABEL: usub_v16i16_vi:
279 ; CHECK-NEXT: li a0, 2
280 ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
281 ; CHECK-NEXT: vssubu.vx v8, v8, a0
283 %v = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 2))
287 declare <2 x i32> @llvm.usub.sat.v2i32(<2 x i32>, <2 x i32>)
289 define <2 x i32> @usub_v2i32_vv(<2 x i32> %va, <2 x i32> %b) {
290 ; CHECK-LABEL: usub_v2i32_vv:
292 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
293 ; CHECK-NEXT: vssubu.vv v8, v8, v9
295 %v = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %va, <2 x i32> %b)
299 define <2 x i32> @usub_v2i32_vx(<2 x i32> %va, i32 %b) {
300 ; CHECK-LABEL: usub_v2i32_vx:
302 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
303 ; CHECK-NEXT: vssubu.vx v8, v8, a0
305 %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
306 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
307 %v = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %va, <2 x i32> %vb)
311 define <2 x i32> @usub_v2i32_vi(<2 x i32> %va) {
312 ; CHECK-LABEL: usub_v2i32_vi:
314 ; CHECK-NEXT: li a0, 2
315 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
316 ; CHECK-NEXT: vssubu.vx v8, v8, a0
318 %v = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 2))
322 declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>)
324 define <4 x i32> @usub_v4i32_vv(<4 x i32> %va, <4 x i32> %b) {
325 ; CHECK-LABEL: usub_v4i32_vv:
327 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
328 ; CHECK-NEXT: vssubu.vv v8, v8, v9
330 %v = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %va, <4 x i32> %b)
334 define <4 x i32> @usub_v4i32_vx(<4 x i32> %va, i32 %b) {
335 ; CHECK-LABEL: usub_v4i32_vx:
337 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
338 ; CHECK-NEXT: vssubu.vx v8, v8, a0
340 %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
341 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer
342 %v = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %va, <4 x i32> %vb)
346 define <4 x i32> @usub_v4i32_vi(<4 x i32> %va) {
347 ; CHECK-LABEL: usub_v4i32_vi:
349 ; CHECK-NEXT: li a0, 2
350 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
351 ; CHECK-NEXT: vssubu.vx v8, v8, a0
353 %v = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 2))
357 declare <8 x i32> @llvm.usub.sat.v8i32(<8 x i32>, <8 x i32>)
359 define <8 x i32> @usub_v8i32_vv(<8 x i32> %va, <8 x i32> %b) {
360 ; CHECK-LABEL: usub_v8i32_vv:
362 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
363 ; CHECK-NEXT: vssubu.vv v8, v8, v10
365 %v = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> %va, <8 x i32> %b)
369 define <8 x i32> @usub_v8i32_vx(<8 x i32> %va, i32 %b) {
370 ; CHECK-LABEL: usub_v8i32_vx:
372 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
373 ; CHECK-NEXT: vssubu.vx v8, v8, a0
375 %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
376 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer
377 %v = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> %va, <8 x i32> %vb)
381 define <8 x i32> @usub_v8i32_vi(<8 x i32> %va) {
382 ; CHECK-LABEL: usub_v8i32_vi:
384 ; CHECK-NEXT: li a0, 2
385 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
386 ; CHECK-NEXT: vssubu.vx v8, v8, a0
388 %v = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 2))
392 declare <16 x i32> @llvm.usub.sat.v16i32(<16 x i32>, <16 x i32>)
394 define <16 x i32> @usub_v16i32_vv(<16 x i32> %va, <16 x i32> %b) {
395 ; CHECK-LABEL: usub_v16i32_vv:
397 ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
398 ; CHECK-NEXT: vssubu.vv v8, v8, v12
400 %v = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %va, <16 x i32> %b)
404 define <16 x i32> @usub_v16i32_vx(<16 x i32> %va, i32 %b) {
405 ; CHECK-LABEL: usub_v16i32_vx:
407 ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
408 ; CHECK-NEXT: vssubu.vx v8, v8, a0
410 %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
411 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer
412 %v = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %va, <16 x i32> %vb)
416 define <16 x i32> @usub_v16i32_vi(<16 x i32> %va) {
417 ; CHECK-LABEL: usub_v16i32_vi:
419 ; CHECK-NEXT: li a0, 2
420 ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
421 ; CHECK-NEXT: vssubu.vx v8, v8, a0
423 %v = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 2))
427 declare <2 x i64> @llvm.usub.sat.v2i64(<2 x i64>, <2 x i64>)
429 define <2 x i64> @usub_v2i64_vv(<2 x i64> %va, <2 x i64> %b) {
430 ; CHECK-LABEL: usub_v2i64_vv:
432 ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
433 ; CHECK-NEXT: vssubu.vv v8, v8, v9
435 %v = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> %va, <2 x i64> %b)
439 define <2 x i64> @usub_v2i64_vx(<2 x i64> %va, i64 %b) {
440 ; RV32-LABEL: usub_v2i64_vx:
442 ; RV32-NEXT: addi sp, sp, -16
443 ; RV32-NEXT: .cfi_def_cfa_offset 16
444 ; RV32-NEXT: sw a0, 8(sp)
445 ; RV32-NEXT: sw a1, 12(sp)
446 ; RV32-NEXT: addi a0, sp, 8
447 ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
448 ; RV32-NEXT: vlse64.v v9, (a0), zero
449 ; RV32-NEXT: vssubu.vv v8, v8, v9
450 ; RV32-NEXT: addi sp, sp, 16
451 ; RV32-NEXT: .cfi_def_cfa_offset 0
454 ; RV64-LABEL: usub_v2i64_vx:
456 ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
457 ; RV64-NEXT: vssubu.vx v8, v8, a0
459 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
460 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
461 %v = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> %va, <2 x i64> %vb)
465 define <2 x i64> @usub_v2i64_vi(<2 x i64> %va) {
466 ; CHECK-LABEL: usub_v2i64_vi:
468 ; CHECK-NEXT: li a0, 2
469 ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
470 ; CHECK-NEXT: vssubu.vx v8, v8, a0
472 %v = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 2))
476 declare <4 x i64> @llvm.usub.sat.v4i64(<4 x i64>, <4 x i64>)
478 define <4 x i64> @usub_v4i64_vv(<4 x i64> %va, <4 x i64> %b) {
479 ; CHECK-LABEL: usub_v4i64_vv:
481 ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
482 ; CHECK-NEXT: vssubu.vv v8, v8, v10
484 %v = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> %va, <4 x i64> %b)
488 define <4 x i64> @usub_v4i64_vx(<4 x i64> %va, i64 %b) {
489 ; RV32-LABEL: usub_v4i64_vx:
491 ; RV32-NEXT: addi sp, sp, -16
492 ; RV32-NEXT: .cfi_def_cfa_offset 16
493 ; RV32-NEXT: sw a0, 8(sp)
494 ; RV32-NEXT: sw a1, 12(sp)
495 ; RV32-NEXT: addi a0, sp, 8
496 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
497 ; RV32-NEXT: vlse64.v v10, (a0), zero
498 ; RV32-NEXT: vssubu.vv v8, v8, v10
499 ; RV32-NEXT: addi sp, sp, 16
500 ; RV32-NEXT: .cfi_def_cfa_offset 0
503 ; RV64-LABEL: usub_v4i64_vx:
505 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
506 ; RV64-NEXT: vssubu.vx v8, v8, a0
508 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
509 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
510 %v = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> %va, <4 x i64> %vb)
514 define <4 x i64> @usub_v4i64_vi(<4 x i64> %va) {
515 ; CHECK-LABEL: usub_v4i64_vi:
517 ; CHECK-NEXT: li a0, 2
518 ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
519 ; CHECK-NEXT: vssubu.vx v8, v8, a0
521 %v = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 2))
525 declare <8 x i64> @llvm.usub.sat.v8i64(<8 x i64>, <8 x i64>)
527 define <8 x i64> @usub_v8i64_vv(<8 x i64> %va, <8 x i64> %b) {
528 ; CHECK-LABEL: usub_v8i64_vv:
530 ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
531 ; CHECK-NEXT: vssubu.vv v8, v8, v12
533 %v = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> %va, <8 x i64> %b)
537 define <8 x i64> @usub_v8i64_vx(<8 x i64> %va, i64 %b) {
538 ; RV32-LABEL: usub_v8i64_vx:
540 ; RV32-NEXT: addi sp, sp, -16
541 ; RV32-NEXT: .cfi_def_cfa_offset 16
542 ; RV32-NEXT: sw a0, 8(sp)
543 ; RV32-NEXT: sw a1, 12(sp)
544 ; RV32-NEXT: addi a0, sp, 8
545 ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
546 ; RV32-NEXT: vlse64.v v12, (a0), zero
547 ; RV32-NEXT: vssubu.vv v8, v8, v12
548 ; RV32-NEXT: addi sp, sp, 16
549 ; RV32-NEXT: .cfi_def_cfa_offset 0
552 ; RV64-LABEL: usub_v8i64_vx:
554 ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
555 ; RV64-NEXT: vssubu.vx v8, v8, a0
557 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
558 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
559 %v = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> %va, <8 x i64> %vb)
563 define <8 x i64> @usub_v8i64_vi(<8 x i64> %va) {
564 ; CHECK-LABEL: usub_v8i64_vi:
566 ; CHECK-NEXT: li a0, 2
567 ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
568 ; CHECK-NEXT: vssubu.vx v8, v8, a0
570 %v = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 2))
574 declare <16 x i64> @llvm.usub.sat.v16i64(<16 x i64>, <16 x i64>)
576 define <16 x i64> @usub_v16i64_vv(<16 x i64> %va, <16 x i64> %b) {
577 ; CHECK-LABEL: usub_v16i64_vv:
579 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
580 ; CHECK-NEXT: vssubu.vv v8, v8, v16
582 %v = call <16 x i64> @llvm.usub.sat.v16i64(<16 x i64> %va, <16 x i64> %b)
586 define <16 x i64> @usub_v16i64_vx(<16 x i64> %va, i64 %b) {
587 ; RV32-LABEL: usub_v16i64_vx:
589 ; RV32-NEXT: addi sp, sp, -16
590 ; RV32-NEXT: .cfi_def_cfa_offset 16
591 ; RV32-NEXT: sw a0, 8(sp)
592 ; RV32-NEXT: sw a1, 12(sp)
593 ; RV32-NEXT: addi a0, sp, 8
594 ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
595 ; RV32-NEXT: vlse64.v v16, (a0), zero
596 ; RV32-NEXT: vssubu.vv v8, v8, v16
597 ; RV32-NEXT: addi sp, sp, 16
598 ; RV32-NEXT: .cfi_def_cfa_offset 0
601 ; RV64-LABEL: usub_v16i64_vx:
603 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
604 ; RV64-NEXT: vssubu.vx v8, v8, a0
606 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
607 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
608 %v = call <16 x i64> @llvm.usub.sat.v16i64(<16 x i64> %va, <16 x i64> %vb)
612 define <16 x i64> @usub_v16i64_vi(<16 x i64> %va) {
613 ; CHECK-LABEL: usub_v16i64_vi:
615 ; CHECK-NEXT: li a0, 2
616 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
617 ; CHECK-NEXT: vssubu.vx v8, v8, a0
619 %v = call <16 x i64> @llvm.usub.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 2))