| blob | 030dfcbc1353bac921088ab11ee4efa3fa4dea33 |
1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple=riscv32 -run-pass=finalize-isel -simplify-mir -o - %s \
3 # RUN: | FileCheck -check-prefix=RV32I %s
4 # RUN: llc -mtriple=riscv64 -run-pass=finalize-isel -simplify-mir -o - %s \
5 # RUN: | FileCheck -check-prefix=RV64I %s
6 # RUN: llc -mtriple=riscv32 -passes=finalize-isel -simplify-mir -o - %s \
7 # RUN: | FileCheck -check-prefix=RV32I %s
8 # RUN: llc -mtriple=riscv64 -passes=finalize-isel -simplify-mir -o - %s \
9 # RUN: | FileCheck -check-prefix=RV64I %s
11 # Provide dummy definitions of functions and just enough metadata to create a
12 # DBG_VALUE.
13 --- |
14 define void @cmov_interleaved_bad() {
15 ret void
16 }
17 define void @cmov_interleaved_debug_value() {
18 ret void
19 }
20 ...
21 ---
22 # Here we have a sequence of select instructions with a non-select instruction
23 # in the middle. Because the non-select depends on the result of a previous
24 # select, we cannot optimize the sequence to share control-flow.
25 name: cmov_interleaved_bad
26 alignment: 4
27 tracksRegLiveness: true
28 registers:
29 - { id: 0, class: gpr }
30 - { id: 1, class: gpr }
31 - { id: 2, class: gpr }
32 - { id: 3, class: gpr }
33 - { id: 4, class: gpr }
34 - { id: 5, class: gpr }
35 - { id: 6, class: gpr }
36 - { id: 7, class: gpr }
37 - { id: 8, class: gpr }
38 - { id: 9, class: gpr }
39 - { id: 10, class: gpr }
40 liveins:
41 - { reg: '$x10', virtual-reg: '%0' }
42 - { reg: '$x11', virtual-reg: '%1' }
43 - { reg: '$x12', virtual-reg: '%2' }
44 - { reg: '$x13', virtual-reg: '%3' }
45 body: |
46 bb.0:
47 liveins: $x10, $x11, $x12, $x13
49 ; RV32I-LABEL: name: cmov_interleaved_bad
50 ; RV32I: successors: %bb.1, %bb.2
51 ; RV32I-NEXT: liveins: $x10, $x11, $x12, $x13
52 ; RV32I-NEXT: {{ $}}
53 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
54 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
55 ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
56 ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
57 ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
58 ; RV32I-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
59 ; RV32I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2
60 ; RV32I-NEXT: {{ $}}
61 ; RV32I-NEXT: .1:
62 ; RV32I-NEXT: {{ $}}
63 ; RV32I-NEXT: .2:
64 ; RV32I-NEXT: successors: %bb.3, %bb.4
65 ; RV32I-NEXT: {{ $}}
66 ; RV32I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
67 ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
68 ; RV32I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.4
69 ; RV32I-NEXT: {{ $}}
70 ; RV32I-NEXT: .3:
71 ; RV32I-NEXT: {{ $}}
72 ; RV32I-NEXT: .4:
73 ; RV32I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
74 ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
75 ; RV32I-NEXT: $x10 = COPY [[ADD]]
76 ; RV32I-NEXT: PseudoRET implicit $x10
77 ; RV64I-LABEL: name: cmov_interleaved_bad
78 ; RV64I: successors: %bb.1, %bb.2
79 ; RV64I-NEXT: liveins: $x10, $x11, $x12, $x13
80 ; RV64I-NEXT: {{ $}}
81 ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
82 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
83 ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
84 ; RV64I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
85 ; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
86 ; RV64I-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
87 ; RV64I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2
88 ; RV64I-NEXT: {{ $}}
89 ; RV64I-NEXT: .1:
90 ; RV64I-NEXT: {{ $}}
91 ; RV64I-NEXT: .2:
92 ; RV64I-NEXT: successors: %bb.3, %bb.4
93 ; RV64I-NEXT: {{ $}}
94 ; RV64I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
95 ; RV64I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
96 ; RV64I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.4
97 ; RV64I-NEXT: {{ $}}
98 ; RV64I-NEXT: .3:
99 ; RV64I-NEXT: {{ $}}
100 ; RV64I-NEXT: .4:
101 ; RV64I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
102 ; RV64I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
103 ; RV64I-NEXT: $x10 = COPY [[ADD]]
104 ; RV64I-NEXT: PseudoRET implicit $x10
105 %3:gpr = COPY $x13
106 %2:gpr = COPY $x12
107 %1:gpr = COPY $x11
108 %0:gpr = COPY $x10
109 %5:gpr = ANDI %0, 1
110 %6:gpr = COPY $x0
111 %7:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %1, %2
112 %8:gpr = ADDI %7, 1
113 %9:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %3, %2
114 %10:gpr = ADD %7, killed %9
115 $x10 = COPY %10
116 PseudoRET implicit $x10
118 ...
119 ---
120 # Demonstrate that debug info associated with selects is correctly moved to
121 # the tail basic block, while debug info associated with non-selects is left
122 # in the head basic block.
123 name: cmov_interleaved_debug_value
124 alignment: 4
125 tracksRegLiveness: true
126 registers:
127 - { id: 0, class: gpr }
128 - { id: 1, class: gpr }
129 - { id: 2, class: gpr }
130 - { id: 3, class: gpr }
131 - { id: 4, class: gpr }
132 - { id: 5, class: gpr }
133 - { id: 6, class: gpr }
134 - { id: 7, class: gpr }
135 - { id: 8, class: gpr }
136 - { id: 9, class: gpr }
137 - { id: 10, class: gpr }
138 liveins:
139 - { reg: '$x10', virtual-reg: '%0' }
140 - { reg: '$x11', virtual-reg: '%1' }
141 - { reg: '$x12', virtual-reg: '%2' }
142 - { reg: '$x13', virtual-reg: '%3' }
143 body: |
144 bb.0:
145 liveins: $x10, $x11, $x12, $x13
147 ; RV32I-LABEL: name: cmov_interleaved_debug_value
148 ; RV32I: successors: %bb.1, %bb.2
149 ; RV32I-NEXT: liveins: $x10, $x11, $x12, $x13
150 ; RV32I-NEXT: {{ $}}
151 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
152 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
153 ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
154 ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
155 ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
156 ; RV32I-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
157 ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
158 ; RV32I-NEXT: DBG_VALUE [[ADDI]], $noreg
159 ; RV32I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2
160 ; RV32I-NEXT: {{ $}}
161 ; RV32I-NEXT: .1:
162 ; RV32I-NEXT: {{ $}}
163 ; RV32I-NEXT: .2:
164 ; RV32I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
165 ; RV32I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
166 ; RV32I-NEXT: DBG_VALUE [[PHI]], $noreg
167 ; RV32I-NEXT: DBG_VALUE [[PHI1]], $noreg
168 ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
169 ; RV32I-NEXT: $x10 = COPY [[ADD]]
170 ; RV32I-NEXT: PseudoRET implicit $x10
171 ; RV64I-LABEL: name: cmov_interleaved_debug_value
172 ; RV64I: successors: %bb.1, %bb.2
173 ; RV64I-NEXT: liveins: $x10, $x11, $x12, $x13
174 ; RV64I-NEXT: {{ $}}
175 ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
176 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
177 ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
178 ; RV64I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
179 ; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
180 ; RV64I-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
181 ; RV64I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
182 ; RV64I-NEXT: DBG_VALUE [[ADDI]], $noreg
183 ; RV64I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2
184 ; RV64I-NEXT: {{ $}}
185 ; RV64I-NEXT: .1:
186 ; RV64I-NEXT: {{ $}}
187 ; RV64I-NEXT: .2:
188 ; RV64I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
189 ; RV64I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
190 ; RV64I-NEXT: DBG_VALUE [[PHI]], $noreg
191 ; RV64I-NEXT: DBG_VALUE [[PHI1]], $noreg
192 ; RV64I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
193 ; RV64I-NEXT: $x10 = COPY [[ADD]]
194 ; RV64I-NEXT: PseudoRET implicit $x10
195 %3:gpr = COPY $x13
196 %2:gpr = COPY $x12
197 %1:gpr = COPY $x11
198 %0:gpr = COPY $x10
199 %5:gpr = ANDI %0, 1
200 %6:gpr = COPY $x0
201 %7:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %1, %2
202 DBG_VALUE %7, $noreg
203 %8:gpr = ADDI %0, 1
204 DBG_VALUE %8, $noreg
205 %9:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %3, %2
206 DBG_VALUE %9, $noreg
207 %10:gpr = ADD %7, killed %9
208 $x10 = COPY %10
209 PseudoRET implicit $x10
211 ...
212 ---