| blob | 77548b49d77f23710215e9891eaee96be31e74e1 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-MVE
3 ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-MVEFP
5 ;
6 ; Float to signed 32-bit -- Vector size variation
7 ;
9 declare <1 x i32> @llvm.fptosi.sat.v1f32.v1i32 (<1 x float>)
10 declare <2 x i32> @llvm.fptosi.sat.v2f32.v2i32 (<2 x float>)
11 declare <3 x i32> @llvm.fptosi.sat.v3f32.v3i32 (<3 x float>)
12 declare <4 x i32> @llvm.fptosi.sat.v4f32.v4i32 (<4 x float>)
13 declare <5 x i32> @llvm.fptosi.sat.v5f32.v5i32 (<5 x float>)
14 declare <6 x i32> @llvm.fptosi.sat.v6f32.v6i32 (<6 x float>)
15 declare <7 x i32> @llvm.fptosi.sat.v7f32.v7i32 (<7 x float>)
16 declare <8 x i32> @llvm.fptosi.sat.v8f32.v8i32 (<8 x float>)
18 define arm_aapcs_vfpcc <1 x i32> @test_signed_v1f32_v1i32(<1 x float> %f) {
19 ; CHECK-LABEL: test_signed_v1f32_v1i32:
20 ; CHECK: @ %bb.0:
21 ; CHECK-NEXT: vcvt.s32.f32 s0, s0
22 ; CHECK-NEXT: vmov r0, s0
23 ; CHECK-NEXT: bx lr
24 %x = call <1 x i32> @llvm.fptosi.sat.v1f32.v1i32(<1 x float> %f)
25 ret <1 x i32> %x
26 }
28 define arm_aapcs_vfpcc <2 x i32> @test_signed_v2f32_v2i32(<2 x float> %f) {
29 ; CHECK-LABEL: test_signed_v2f32_v2i32:
30 ; CHECK: @ %bb.0:
31 ; CHECK-NEXT: .save {r4, r5, r7, lr}
32 ; CHECK-NEXT: push {r4, r5, r7, lr}
33 ; CHECK-NEXT: .vsave {d8, d9, d10}
34 ; CHECK-NEXT: vpush {d8, d9, d10}
35 ; CHECK-NEXT: vmov q4, q0
36 ; CHECK-NEXT: vmov r0, s17
37 ; CHECK-NEXT: bl __aeabi_f2lz
38 ; CHECK-NEXT: mov r5, r0
39 ; CHECK-NEXT: vmov r0, s16
40 ; CHECK-NEXT: vldr s18, .LCPI1_0
41 ; CHECK-NEXT: mov r4, r1
42 ; CHECK-NEXT: vldr s20, .LCPI1_1
43 ; CHECK-NEXT: vcmp.f32 s17, s18
44 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
45 ; CHECK-NEXT: itt lt
46 ; CHECK-NEXT: movlt.w r4, #-1
47 ; CHECK-NEXT: movlt.w r5, #-2147483648
48 ; CHECK-NEXT: vcmp.f32 s17, s20
49 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
50 ; CHECK-NEXT: itt gt
51 ; CHECK-NEXT: mvngt r5, #-2147483648
52 ; CHECK-NEXT: movgt r4, #0
53 ; CHECK-NEXT: vcmp.f32 s17, s17
54 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
55 ; CHECK-NEXT: itt vs
56 ; CHECK-NEXT: movvs r4, #0
57 ; CHECK-NEXT: movvs r5, #0
58 ; CHECK-NEXT: bl __aeabi_f2lz
59 ; CHECK-NEXT: vcmp.f32 s16, s18
60 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
61 ; CHECK-NEXT: itt lt
62 ; CHECK-NEXT: movlt.w r0, #-2147483648
63 ; CHECK-NEXT: movlt.w r1, #-1
64 ; CHECK-NEXT: vcmp.f32 s16, s20
65 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
66 ; CHECK-NEXT: itt gt
67 ; CHECK-NEXT: movgt r1, #0
68 ; CHECK-NEXT: mvngt r0, #-2147483648
69 ; CHECK-NEXT: vcmp.f32 s16, s16
70 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
71 ; CHECK-NEXT: itt vs
72 ; CHECK-NEXT: movvs r0, #0
73 ; CHECK-NEXT: movvs r1, #0
74 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
75 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r4
76 ; CHECK-NEXT: vpop {d8, d9, d10}
77 ; CHECK-NEXT: pop {r4, r5, r7, pc}
78 ; CHECK-NEXT: .p2align 2
79 ; CHECK-NEXT: @ %bb.1:
80 ; CHECK-NEXT: .LCPI1_0:
81 ; CHECK-NEXT: .long 0xcf000000 @ float -2.14748365E+9
82 ; CHECK-NEXT: .LCPI1_1:
83 ; CHECK-NEXT: .long 0x4effffff @ float 2.14748352E+9
84 %x = call <2 x i32> @llvm.fptosi.sat.v2f32.v2i32(<2 x float> %f)
85 ret <2 x i32> %x
86 }
88 define arm_aapcs_vfpcc <3 x i32> @test_signed_v3f32_v3i32(<3 x float> %f) {
89 ; CHECK-MVE-LABEL: test_signed_v3f32_v3i32:
90 ; CHECK-MVE: @ %bb.0:
91 ; CHECK-MVE-NEXT: vcvt.s32.f32 s2, s2
92 ; CHECK-MVE-NEXT: vcvt.s32.f32 s0, s0
93 ; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s3
94 ; CHECK-MVE-NEXT: vcvt.s32.f32 s6, s1
95 ; CHECK-MVE-NEXT: vmov r0, s2
96 ; CHECK-MVE-NEXT: vmov r1, s0
97 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
98 ; CHECK-MVE-NEXT: vmov r0, s4
99 ; CHECK-MVE-NEXT: vmov r1, s6
100 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r1, r0
101 ; CHECK-MVE-NEXT: bx lr
102 ;
103 ; CHECK-MVEFP-LABEL: test_signed_v3f32_v3i32:
104 ; CHECK-MVEFP: @ %bb.0:
105 ; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
106 ; CHECK-MVEFP-NEXT: bx lr
107 %x = call <3 x i32> @llvm.fptosi.sat.v3f32.v3i32(<3 x float> %f)
108 ret <3 x i32> %x
109 }
111 define arm_aapcs_vfpcc <4 x i32> @test_signed_v4f32_v4i32(<4 x float> %f) {
112 ; CHECK-MVE-LABEL: test_signed_v4f32_v4i32:
113 ; CHECK-MVE: @ %bb.0:
114 ; CHECK-MVE-NEXT: vcvt.s32.f32 s2, s2
115 ; CHECK-MVE-NEXT: vcvt.s32.f32 s0, s0
116 ; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s3
117 ; CHECK-MVE-NEXT: vcvt.s32.f32 s6, s1
118 ; CHECK-MVE-NEXT: vmov r0, s2
119 ; CHECK-MVE-NEXT: vmov r1, s0
120 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
121 ; CHECK-MVE-NEXT: vmov r0, s4
122 ; CHECK-MVE-NEXT: vmov r1, s6
123 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r1, r0
124 ; CHECK-MVE-NEXT: bx lr
125 ;
126 ; CHECK-MVEFP-LABEL: test_signed_v4f32_v4i32:
127 ; CHECK-MVEFP: @ %bb.0:
128 ; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
129 ; CHECK-MVEFP-NEXT: bx lr
130 %x = call <4 x i32> @llvm.fptosi.sat.v4f32.v4i32(<4 x float> %f)
131 ret <4 x i32> %x
132 }
134 define arm_aapcs_vfpcc <5 x i32> @test_signed_v5f32_v5i32(<5 x float> %f) {
135 ; CHECK-MVE-LABEL: test_signed_v5f32_v5i32:
136 ; CHECK-MVE: @ %bb.0:
137 ; CHECK-MVE-NEXT: vcvt.s32.f32 s2, s2
138 ; CHECK-MVE-NEXT: vcvt.s32.f32 s0, s0
139 ; CHECK-MVE-NEXT: vcvt.s32.f32 s6, s3
140 ; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s1
141 ; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s4
142 ; CHECK-MVE-NEXT: vmov r1, s2
143 ; CHECK-MVE-NEXT: vmov r2, s0
144 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r2, r1
145 ; CHECK-MVE-NEXT: vmov r1, s6
146 ; CHECK-MVE-NEXT: vmov r2, s8
147 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r2, r1
148 ; CHECK-MVE-NEXT: vstrw.32 q0, [r0]
149 ; CHECK-MVE-NEXT: vstr s4, [r0, #16]
150 ; CHECK-MVE-NEXT: bx lr
151 ;
152 ; CHECK-MVEFP-LABEL: test_signed_v5f32_v5i32:
153 ; CHECK-MVEFP: @ %bb.0:
154 ; CHECK-MVEFP-NEXT: vcvt.s32.f32 q1, q1
155 ; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
156 ; CHECK-MVEFP-NEXT: vmov r1, s4
157 ; CHECK-MVEFP-NEXT: str r1, [r0, #16]
158 ; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0]
159 ; CHECK-MVEFP-NEXT: bx lr
160 %x = call <5 x i32> @llvm.fptosi.sat.v5f32.v5i32(<5 x float> %f)
161 ret <5 x i32> %x
162 }
164 define arm_aapcs_vfpcc <6 x i32> @test_signed_v6f32_v6i32(<6 x float> %f) {
165 ; CHECK-MVE-LABEL: test_signed_v6f32_v6i32:
166 ; CHECK-MVE: @ %bb.0:
167 ; CHECK-MVE-NEXT: vcvt.s32.f32 s2, s2
168 ; CHECK-MVE-NEXT: vcvt.s32.f32 s0, s0
169 ; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s3
170 ; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s1
171 ; CHECK-MVE-NEXT: vcvt.s32.f32 s6, s5
172 ; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s4
173 ; CHECK-MVE-NEXT: vmov r1, s2
174 ; CHECK-MVE-NEXT: vmov r2, s0
175 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r2, r1
176 ; CHECK-MVE-NEXT: vmov r1, s8
177 ; CHECK-MVE-NEXT: vmov r2, s10
178 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r2, r1
179 ; CHECK-MVE-NEXT: vstr s6, [r0, #20]
180 ; CHECK-MVE-NEXT: vstrw.32 q0, [r0]
181 ; CHECK-MVE-NEXT: vstr s4, [r0, #16]
182 ; CHECK-MVE-NEXT: bx lr
183 ;
184 ; CHECK-MVEFP-LABEL: test_signed_v6f32_v6i32:
185 ; CHECK-MVEFP: @ %bb.0:
186 ; CHECK-MVEFP-NEXT: vcvt.s32.f32 q1, q1
187 ; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
188 ; CHECK-MVEFP-NEXT: vmov.f32 s6, s5
189 ; CHECK-MVEFP-NEXT: vmov r2, s4
190 ; CHECK-MVEFP-NEXT: vmov r1, s6
191 ; CHECK-MVEFP-NEXT: strd r2, r1, [r0, #16]
192 ; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0]
193 ; CHECK-MVEFP-NEXT: bx lr
194 %x = call <6 x i32> @llvm.fptosi.sat.v6f32.v6i32(<6 x float> %f)
195 ret <6 x i32> %x
196 }
198 define arm_aapcs_vfpcc <7 x i32> @test_signed_v7f32_v7i32(<7 x float> %f) {
199 ; CHECK-MVE-LABEL: test_signed_v7f32_v7i32:
200 ; CHECK-MVE: @ %bb.0:
201 ; CHECK-MVE-NEXT: vcvt.s32.f32 s2, s2
202 ; CHECK-MVE-NEXT: vcvt.s32.f32 s0, s0
203 ; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s3
204 ; CHECK-MVE-NEXT: vcvt.s32.f32 s12, s1
205 ; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s5
206 ; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s4
207 ; CHECK-MVE-NEXT: vcvt.s32.f32 s6, s6
208 ; CHECK-MVE-NEXT: vmov r1, s2
209 ; CHECK-MVE-NEXT: vmov r2, s0
210 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r2, r1
211 ; CHECK-MVE-NEXT: vmov r1, s10
212 ; CHECK-MVE-NEXT: vmov r2, s12
213 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r2, r1
214 ; CHECK-MVE-NEXT: vstr s8, [r0, #20]
215 ; CHECK-MVE-NEXT: vstr s4, [r0, #16]
216 ; CHECK-MVE-NEXT: vstrw.32 q0, [r0]
217 ; CHECK-MVE-NEXT: vstr s6, [r0, #24]
218 ; CHECK-MVE-NEXT: bx lr
219 ;
220 ; CHECK-MVEFP-LABEL: test_signed_v7f32_v7i32:
221 ; CHECK-MVEFP: @ %bb.0:
222 ; CHECK-MVEFP-NEXT: vcvt.s32.f32 q1, q1
223 ; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
224 ; CHECK-MVEFP-NEXT: vmov.f32 s10, s5
225 ; CHECK-MVEFP-NEXT: vmov r2, s4
226 ; CHECK-MVEFP-NEXT: vmov r3, s6
227 ; CHECK-MVEFP-NEXT: vmov r1, s10
228 ; CHECK-MVEFP-NEXT: strd r2, r1, [r0, #16]
229 ; CHECK-MVEFP-NEXT: str r3, [r0, #24]
230 ; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0]
231 ; CHECK-MVEFP-NEXT: bx lr
232 %x = call <7 x i32> @llvm.fptosi.sat.v7f32.v7i32(<7 x float> %f)
233 ret <7 x i32> %x
234 }
236 define arm_aapcs_vfpcc <8 x i32> @test_signed_v8f32_v8i32(<8 x float> %f) {
237 ; CHECK-MVE-LABEL: test_signed_v8f32_v8i32:
238 ; CHECK-MVE: @ %bb.0:
239 ; CHECK-MVE-NEXT: vcvt.s32.f32 s2, s2
240 ; CHECK-MVE-NEXT: vcvt.s32.f32 s0, s0
241 ; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s3
242 ; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s1
243 ; CHECK-MVE-NEXT: vcvt.s32.f32 s6, s6
244 ; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s4
245 ; CHECK-MVE-NEXT: vcvt.s32.f32 s12, s7
246 ; CHECK-MVE-NEXT: vcvt.s32.f32 s14, s5
247 ; CHECK-MVE-NEXT: vmov r0, s2
248 ; CHECK-MVE-NEXT: vmov r1, s0
249 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
250 ; CHECK-MVE-NEXT: vmov r0, s8
251 ; CHECK-MVE-NEXT: vmov r1, s10
252 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r1, r0
253 ; CHECK-MVE-NEXT: vmov r0, s6
254 ; CHECK-MVE-NEXT: vmov r1, s4
255 ; CHECK-MVE-NEXT: vmov q1[2], q1[0], r1, r0
256 ; CHECK-MVE-NEXT: vmov r0, s12
257 ; CHECK-MVE-NEXT: vmov r1, s14
258 ; CHECK-MVE-NEXT: vmov q1[3], q1[1], r1, r0
259 ; CHECK-MVE-NEXT: bx lr
260 ;
261 ; CHECK-MVEFP-LABEL: test_signed_v8f32_v8i32:
262 ; CHECK-MVEFP: @ %bb.0:
263 ; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
264 ; CHECK-MVEFP-NEXT: vcvt.s32.f32 q1, q1
265 ; CHECK-MVEFP-NEXT: bx lr
266 %x = call <8 x i32> @llvm.fptosi.sat.v8f32.v8i32(<8 x float> %f)
267 ret <8 x i32> %x
268 }
270 ;
271 ; Double to signed 32-bit -- Vector size variation
272 ;
274 declare <1 x i32> @llvm.fptosi.sat.v1f64.v1i32 (<1 x double>)
275 declare <2 x i32> @llvm.fptosi.sat.v2f64.v2i32 (<2 x double>)
276 declare <3 x i32> @llvm.fptosi.sat.v3f64.v3i32 (<3 x double>)
277 declare <4 x i32> @llvm.fptosi.sat.v4f64.v4i32 (<4 x double>)
278 declare <5 x i32> @llvm.fptosi.sat.v5f64.v5i32 (<5 x double>)
279 declare <6 x i32> @llvm.fptosi.sat.v6f64.v6i32 (<6 x double>)
281 define arm_aapcs_vfpcc <1 x i32> @test_signed_v1f64_v1i32(<1 x double> %f) {
282 ; CHECK-LABEL: test_signed_v1f64_v1i32:
283 ; CHECK: @ %bb.0:
284 ; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
285 ; CHECK-NEXT: push {r4, r5, r6, r7, lr}
286 ; CHECK-NEXT: .pad #4
287 ; CHECK-NEXT: sub sp, #4
288 ; CHECK-NEXT: vldr d1, .LCPI8_0
289 ; CHECK-NEXT: vmov r5, r4, d0
290 ; CHECK-NEXT: vmov r2, r3, d1
291 ; CHECK-NEXT: mov r0, r5
292 ; CHECK-NEXT: mov r1, r4
293 ; CHECK-NEXT: bl __aeabi_dcmpge
294 ; CHECK-NEXT: mov r6, r0
295 ; CHECK-NEXT: mov r0, r5
296 ; CHECK-NEXT: mov r1, r4
297 ; CHECK-NEXT: bl __aeabi_d2iz
298 ; CHECK-NEXT: vldr d0, .LCPI8_1
299 ; CHECK-NEXT: mov r7, r0
300 ; CHECK-NEXT: mov r0, r5
301 ; CHECK-NEXT: mov r1, r4
302 ; CHECK-NEXT: vmov r2, r3, d0
303 ; CHECK-NEXT: cmp r6, #0
304 ; CHECK-NEXT: it eq
305 ; CHECK-NEXT: moveq.w r7, #-2147483648
306 ; CHECK-NEXT: bl __aeabi_dcmpgt
307 ; CHECK-NEXT: cmp r0, #0
308 ; CHECK-NEXT: mov r0, r5
309 ; CHECK-NEXT: mov r1, r4
310 ; CHECK-NEXT: mov r2, r5
311 ; CHECK-NEXT: mov r3, r4
312 ; CHECK-NEXT: it ne
313 ; CHECK-NEXT: mvnne r7, #-2147483648
314 ; CHECK-NEXT: bl __aeabi_dcmpun
315 ; CHECK-NEXT: cmp r0, #0
316 ; CHECK-NEXT: it ne
317 ; CHECK-NEXT: movne r7, #0
318 ; CHECK-NEXT: mov r0, r7
319 ; CHECK-NEXT: add sp, #4
320 ; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
321 ; CHECK-NEXT: .p2align 3
322 ; CHECK-NEXT: @ %bb.1:
323 ; CHECK-NEXT: .LCPI8_0:
324 ; CHECK-NEXT: .long 0 @ double -2147483648
325 ; CHECK-NEXT: .long 3252682752
326 ; CHECK-NEXT: .LCPI8_1:
327 ; CHECK-NEXT: .long 4290772992 @ double 2147483647
328 ; CHECK-NEXT: .long 1105199103
329 %x = call <1 x i32> @llvm.fptosi.sat.v1f64.v1i32(<1 x double> %f)
330 ret <1 x i32> %x
331 }
333 define arm_aapcs_vfpcc <2 x i32> @test_signed_v2f64_v2i32(<2 x double> %f) {
334 ; CHECK-LABEL: test_signed_v2f64_v2i32:
335 ; CHECK: @ %bb.0:
336 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
337 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
338 ; CHECK-NEXT: .pad #4
339 ; CHECK-NEXT: sub sp, #4
340 ; CHECK-NEXT: .vsave {d8, d9}
341 ; CHECK-NEXT: vpush {d8, d9}
342 ; CHECK-NEXT: .pad #16
343 ; CHECK-NEXT: sub sp, #16
344 ; CHECK-NEXT: vmov q4, q0
345 ; CHECK-NEXT: vldr d0, .LCPI9_0
346 ; CHECK-NEXT: vmov r9, r8, d9
347 ; CHECK-NEXT: vmov r7, r3, d0
348 ; CHECK-NEXT: str r3, [sp, #12] @ 4-byte Spill
349 ; CHECK-NEXT: mov r0, r9
350 ; CHECK-NEXT: mov r1, r8
351 ; CHECK-NEXT: mov r2, r7
352 ; CHECK-NEXT: bl __aeabi_dcmpge
353 ; CHECK-NEXT: mov r6, r0
354 ; CHECK-NEXT: mov r0, r9
355 ; CHECK-NEXT: mov r1, r8
356 ; CHECK-NEXT: bl __aeabi_d2lz
357 ; CHECK-NEXT: vldr d0, .LCPI9_1
358 ; CHECK-NEXT: mov r5, r0
359 ; CHECK-NEXT: mov r4, r1
360 ; CHECK-NEXT: mov r0, r9
361 ; CHECK-NEXT: vmov r2, r3, d0
362 ; CHECK-NEXT: mov r1, r8
363 ; CHECK-NEXT: vmov r11, r10, d8
364 ; CHECK-NEXT: cmp r6, #0
365 ; CHECK-NEXT: strd r2, r3, [sp, #4] @ 8-byte Folded Spill
366 ; CHECK-NEXT: itt eq
367 ; CHECK-NEXT: moveq.w r4, #-1
368 ; CHECK-NEXT: moveq.w r5, #-2147483648
369 ; CHECK-NEXT: bl __aeabi_dcmpgt
370 ; CHECK-NEXT: cmp r0, #0
371 ; CHECK-NEXT: mov r0, r9
372 ; CHECK-NEXT: mov r1, r8
373 ; CHECK-NEXT: mov r2, r9
374 ; CHECK-NEXT: mov r3, r8
375 ; CHECK-NEXT: itt ne
376 ; CHECK-NEXT: mvnne r5, #-2147483648
377 ; CHECK-NEXT: movne r4, #0
378 ; CHECK-NEXT: bl __aeabi_dcmpun
379 ; CHECK-NEXT: cmp r0, #0
380 ; CHECK-NEXT: itt ne
381 ; CHECK-NEXT: movne r4, #0
382 ; CHECK-NEXT: movne r5, #0
383 ; CHECK-NEXT: ldr r3, [sp, #12] @ 4-byte Reload
384 ; CHECK-NEXT: mov r0, r11
385 ; CHECK-NEXT: mov r1, r10
386 ; CHECK-NEXT: mov r2, r7
387 ; CHECK-NEXT: bl __aeabi_dcmpge
388 ; CHECK-NEXT: mov r8, r0
389 ; CHECK-NEXT: mov r0, r11
390 ; CHECK-NEXT: mov r1, r10
391 ; CHECK-NEXT: bl __aeabi_d2lz
392 ; CHECK-NEXT: mov r7, r0
393 ; CHECK-NEXT: mov r6, r1
394 ; CHECK-NEXT: cmp.w r8, #0
395 ; CHECK-NEXT: itt eq
396 ; CHECK-NEXT: moveq.w r7, #-2147483648
397 ; CHECK-NEXT: moveq.w r6, #-1
398 ; CHECK-NEXT: ldrd r2, r3, [sp, #4] @ 8-byte Folded Reload
399 ; CHECK-NEXT: mov r0, r11
400 ; CHECK-NEXT: mov r1, r10
401 ; CHECK-NEXT: bl __aeabi_dcmpgt
402 ; CHECK-NEXT: cmp r0, #0
403 ; CHECK-NEXT: mov r0, r11
404 ; CHECK-NEXT: mov r1, r10
405 ; CHECK-NEXT: mov r2, r11
406 ; CHECK-NEXT: mov r3, r10
407 ; CHECK-NEXT: itt ne
408 ; CHECK-NEXT: movne r6, #0
409 ; CHECK-NEXT: mvnne r7, #-2147483648
410 ; CHECK-NEXT: bl __aeabi_dcmpun
411 ; CHECK-NEXT: cmp r0, #0
412 ; CHECK-NEXT: itt ne
413 ; CHECK-NEXT: movne r7, #0
414 ; CHECK-NEXT: movne r6, #0
415 ; CHECK-NEXT: vmov q0[2], q0[0], r7, r5
416 ; CHECK-NEXT: vmov q0[3], q0[1], r6, r4
417 ; CHECK-NEXT: add sp, #16
418 ; CHECK-NEXT: vpop {d8, d9}
419 ; CHECK-NEXT: add sp, #4
420 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
421 ; CHECK-NEXT: .p2align 3
422 ; CHECK-NEXT: @ %bb.1:
423 ; CHECK-NEXT: .LCPI9_0:
424 ; CHECK-NEXT: .long 0 @ double -2147483648
425 ; CHECK-NEXT: .long 3252682752
426 ; CHECK-NEXT: .LCPI9_1:
427 ; CHECK-NEXT: .long 4290772992 @ double 2147483647
428 ; CHECK-NEXT: .long 1105199103
429 %x = call <2 x i32> @llvm.fptosi.sat.v2f64.v2i32(<2 x double> %f)
430 ret <2 x i32> %x
431 }
433 define arm_aapcs_vfpcc <3 x i32> @test_signed_v3f64_v3i32(<3 x double> %f) {
434 ; CHECK-LABEL: test_signed_v3f64_v3i32:
435 ; CHECK: @ %bb.0:
436 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
437 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
438 ; CHECK-NEXT: .pad #4
439 ; CHECK-NEXT: sub sp, #4
440 ; CHECK-NEXT: .vsave {d8, d9}
441 ; CHECK-NEXT: vpush {d8, d9}
442 ; CHECK-NEXT: .pad #24
443 ; CHECK-NEXT: sub sp, #24
444 ; CHECK-NEXT: vmov.f32 s18, s0
445 ; CHECK-NEXT: vmov.f32 s19, s1
446 ; CHECK-NEXT: vldr d0, .LCPI10_0
447 ; CHECK-NEXT: vmov r10, r7, d1
448 ; CHECK-NEXT: vmov r6, r3, d0
449 ; CHECK-NEXT: vmov.f32 s16, s4
450 ; CHECK-NEXT: vmov.f32 s17, s5
451 ; CHECK-NEXT: str r3, [sp, #8] @ 4-byte Spill
452 ; CHECK-NEXT: mov r0, r10
453 ; CHECK-NEXT: mov r1, r7
454 ; CHECK-NEXT: mov r2, r6
455 ; CHECK-NEXT: bl __aeabi_dcmpge
456 ; CHECK-NEXT: mov r4, r0
457 ; CHECK-NEXT: mov r0, r10
458 ; CHECK-NEXT: mov r1, r7
459 ; CHECK-NEXT: bl __aeabi_d2lz
460 ; CHECK-NEXT: vldr d0, .LCPI10_1
461 ; CHECK-NEXT: mov r11, r0
462 ; CHECK-NEXT: vmov r1, r0, d9
463 ; CHECK-NEXT: cmp r4, #0
464 ; CHECK-NEXT: vmov r2, r3, d0
465 ; CHECK-NEXT: vmov r9, r8, d8
466 ; CHECK-NEXT: str r2, [sp, #20] @ 4-byte Spill
467 ; CHECK-NEXT: strd r1, r0, [sp, #12] @ 8-byte Folded Spill
468 ; CHECK-NEXT: mov r0, r10
469 ; CHECK-NEXT: mov r1, r7
470 ; CHECK-NEXT: it eq
471 ; CHECK-NEXT: moveq.w r11, #-2147483648
472 ; CHECK-NEXT: mov r4, r3
473 ; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill
474 ; CHECK-NEXT: bl __aeabi_dcmpgt
475 ; CHECK-NEXT: cmp r0, #0
476 ; CHECK-NEXT: mov r0, r10
477 ; CHECK-NEXT: mov r1, r7
478 ; CHECK-NEXT: mov r2, r10
479 ; CHECK-NEXT: mov r3, r7
480 ; CHECK-NEXT: it ne
481 ; CHECK-NEXT: mvnne r11, #-2147483648
482 ; CHECK-NEXT: bl __aeabi_dcmpun
483 ; CHECK-NEXT: cmp r0, #0
484 ; CHECK-NEXT: it ne
485 ; CHECK-NEXT: movne.w r11, #0
486 ; CHECK-NEXT: ldr.w r10, [sp, #8] @ 4-byte Reload
487 ; CHECK-NEXT: mov r0, r9
488 ; CHECK-NEXT: mov r1, r8
489 ; CHECK-NEXT: mov r2, r6
490 ; CHECK-NEXT: mov r3, r10
491 ; CHECK-NEXT: bl __aeabi_dcmpge
492 ; CHECK-NEXT: mov r5, r0
493 ; CHECK-NEXT: mov r0, r9
494 ; CHECK-NEXT: mov r1, r8
495 ; CHECK-NEXT: bl __aeabi_d2lz
496 ; CHECK-NEXT: mov r7, r0
497 ; CHECK-NEXT: cmp r5, #0
498 ; CHECK-NEXT: it eq
499 ; CHECK-NEXT: moveq.w r7, #-2147483648
500 ; CHECK-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
501 ; CHECK-NEXT: mov r0, r9
502 ; CHECK-NEXT: mov r1, r8
503 ; CHECK-NEXT: mov r3, r4
504 ; CHECK-NEXT: bl __aeabi_dcmpgt
505 ; CHECK-NEXT: cmp r0, #0
506 ; CHECK-NEXT: mov r0, r9
507 ; CHECK-NEXT: mov r1, r8
508 ; CHECK-NEXT: mov r2, r9
509 ; CHECK-NEXT: mov r3, r8
510 ; CHECK-NEXT: it ne
511 ; CHECK-NEXT: mvnne r7, #-2147483648
512 ; CHECK-NEXT: bl __aeabi_dcmpun
513 ; CHECK-NEXT: cmp r0, #0
514 ; CHECK-NEXT: it ne
515 ; CHECK-NEXT: movne r7, #0
516 ; CHECK-NEXT: ldr r5, [sp, #12] @ 4-byte Reload
517 ; CHECK-NEXT: mov r2, r6
518 ; CHECK-NEXT: ldr r4, [sp, #16] @ 4-byte Reload
519 ; CHECK-NEXT: mov r3, r10
520 ; CHECK-NEXT: mov r0, r5
521 ; CHECK-NEXT: mov r1, r4
522 ; CHECK-NEXT: bl __aeabi_dcmpge
523 ; CHECK-NEXT: mov r8, r0
524 ; CHECK-NEXT: mov r0, r5
525 ; CHECK-NEXT: mov r1, r4
526 ; CHECK-NEXT: bl __aeabi_d2lz
527 ; CHECK-NEXT: mov r6, r0
528 ; CHECK-NEXT: cmp.w r8, #0
529 ; CHECK-NEXT: it eq
530 ; CHECK-NEXT: moveq.w r6, #-2147483648
531 ; CHECK-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
532 ; CHECK-NEXT: ldr r3, [sp, #4] @ 4-byte Reload
533 ; CHECK-NEXT: mov r0, r5
534 ; CHECK-NEXT: mov r1, r4
535 ; CHECK-NEXT: bl __aeabi_dcmpgt
536 ; CHECK-NEXT: cmp r0, #0
537 ; CHECK-NEXT: mov r0, r5
538 ; CHECK-NEXT: mov r1, r4
539 ; CHECK-NEXT: mov r2, r5
540 ; CHECK-NEXT: mov r3, r4
541 ; CHECK-NEXT: it ne
542 ; CHECK-NEXT: mvnne r6, #-2147483648
543 ; CHECK-NEXT: bl __aeabi_dcmpun
544 ; CHECK-NEXT: vmov.32 q0[1], r11
545 ; CHECK-NEXT: cmp r0, #0
546 ; CHECK-NEXT: it ne
547 ; CHECK-NEXT: movne r6, #0
548 ; CHECK-NEXT: vmov q0[2], q0[0], r6, r7
549 ; CHECK-NEXT: add sp, #24
550 ; CHECK-NEXT: vpop {d8, d9}
551 ; CHECK-NEXT: add sp, #4
552 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
553 ; CHECK-NEXT: .p2align 3
554 ; CHECK-NEXT: @ %bb.1:
555 ; CHECK-NEXT: .LCPI10_0:
556 ; CHECK-NEXT: .long 0 @ double -2147483648
557 ; CHECK-NEXT: .long 3252682752
558 ; CHECK-NEXT: .LCPI10_1:
559 ; CHECK-NEXT: .long 4290772992 @ double 2147483647
560 ; CHECK-NEXT: .long 1105199103
561 %x = call <3 x i32> @llvm.fptosi.sat.v3f64.v3i32(<3 x double> %f)
562 ret <3 x i32> %x
563 }
565 define arm_aapcs_vfpcc <4 x i32> @test_signed_v4f64_v4i32(<4 x double> %f) {
566 ; CHECK-LABEL: test_signed_v4f64_v4i32:
567 ; CHECK: @ %bb.0:
568 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
569 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
570 ; CHECK-NEXT: .pad #4
571 ; CHECK-NEXT: sub sp, #4
572 ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
573 ; CHECK-NEXT: vpush {d8, d9, d10, d11}
574 ; CHECK-NEXT: .pad #24
575 ; CHECK-NEXT: sub sp, #24
576 ; CHECK-NEXT: vmov q5, q1
577 ; CHECK-NEXT: vmov q4, q0
578 ; CHECK-NEXT: vldr d0, .LCPI11_0
579 ; CHECK-NEXT: vmov r5, r6, d10
580 ; CHECK-NEXT: vmov r2, r3, d0
581 ; CHECK-NEXT: mov r0, r5
582 ; CHECK-NEXT: mov r1, r6
583 ; CHECK-NEXT: str r2, [sp, #4] @ 4-byte Spill
584 ; CHECK-NEXT: mov r9, r3
585 ; CHECK-NEXT: bl __aeabi_dcmpge
586 ; CHECK-NEXT: mov r8, r0
587 ; CHECK-NEXT: mov r0, r5
588 ; CHECK-NEXT: mov r1, r6
589 ; CHECK-NEXT: bl __aeabi_d2lz
590 ; CHECK-NEXT: vldr d0, .LCPI11_1
591 ; CHECK-NEXT: mov r4, r0
592 ; CHECK-NEXT: vmov r11, r0, d11
593 ; CHECK-NEXT: mov r1, r6
594 ; CHECK-NEXT: vmov r2, r3, d0
595 ; CHECK-NEXT: cmp.w r8, #0
596 ; CHECK-NEXT: vmov r7, r10, d8
597 ; CHECK-NEXT: str r0, [sp, #8] @ 4-byte Spill
598 ; CHECK-NEXT: mov r0, r5
599 ; CHECK-NEXT: str r2, [sp, #16] @ 4-byte Spill
600 ; CHECK-NEXT: it eq
601 ; CHECK-NEXT: moveq.w r4, #-2147483648
602 ; CHECK-NEXT: str r3, [sp, #20] @ 4-byte Spill
603 ; CHECK-NEXT: mov r8, r3
604 ; CHECK-NEXT: bl __aeabi_dcmpgt
605 ; CHECK-NEXT: cmp r0, #0
606 ; CHECK-NEXT: mov r0, r5
607 ; CHECK-NEXT: mov r1, r6
608 ; CHECK-NEXT: mov r2, r5
609 ; CHECK-NEXT: mov r3, r6
610 ; CHECK-NEXT: it ne
611 ; CHECK-NEXT: mvnne r4, #-2147483648
612 ; CHECK-NEXT: bl __aeabi_dcmpun
613 ; CHECK-NEXT: cmp r0, #0
614 ; CHECK-NEXT: it ne
615 ; CHECK-NEXT: movne r4, #0
616 ; CHECK-NEXT: ldr r6, [sp, #4] @ 4-byte Reload
617 ; CHECK-NEXT: mov r0, r7
618 ; CHECK-NEXT: mov r1, r10
619 ; CHECK-NEXT: mov r3, r9
620 ; CHECK-NEXT: str r4, [sp, #12] @ 4-byte Spill
621 ; CHECK-NEXT: mov r4, r9
622 ; CHECK-NEXT: mov r2, r6
623 ; CHECK-NEXT: str.w r9, [sp] @ 4-byte Spill
624 ; CHECK-NEXT: bl __aeabi_dcmpge
625 ; CHECK-NEXT: mov r5, r0
626 ; CHECK-NEXT: mov r0, r7
627 ; CHECK-NEXT: mov r1, r10
628 ; CHECK-NEXT: bl __aeabi_d2lz
629 ; CHECK-NEXT: mov r9, r0
630 ; CHECK-NEXT: cmp r5, #0
631 ; CHECK-NEXT: it eq
632 ; CHECK-NEXT: moveq.w r9, #-2147483648
633 ; CHECK-NEXT: ldr r2, [sp, #16] @ 4-byte Reload
634 ; CHECK-NEXT: mov r0, r7
635 ; CHECK-NEXT: mov r1, r10
636 ; CHECK-NEXT: mov r3, r8
637 ; CHECK-NEXT: bl __aeabi_dcmpgt
638 ; CHECK-NEXT: cmp r0, #0
639 ; CHECK-NEXT: mov r0, r7
640 ; CHECK-NEXT: mov r1, r10
641 ; CHECK-NEXT: mov r2, r7
642 ; CHECK-NEXT: mov r3, r10
643 ; CHECK-NEXT: it ne
644 ; CHECK-NEXT: mvnne r9, #-2147483648
645 ; CHECK-NEXT: bl __aeabi_dcmpun
646 ; CHECK-NEXT: cmp r0, #0
647 ; CHECK-NEXT: it ne
648 ; CHECK-NEXT: movne.w r9, #0
649 ; CHECK-NEXT: ldr r5, [sp, #8] @ 4-byte Reload
650 ; CHECK-NEXT: mov r0, r11
651 ; CHECK-NEXT: mov r2, r6
652 ; CHECK-NEXT: mov r3, r4
653 ; CHECK-NEXT: mov r1, r5
654 ; CHECK-NEXT: bl __aeabi_dcmpge
655 ; CHECK-NEXT: mov r4, r0
656 ; CHECK-NEXT: mov r0, r11
657 ; CHECK-NEXT: mov r1, r5
658 ; CHECK-NEXT: bl __aeabi_d2lz
659 ; CHECK-NEXT: mov r8, r0
660 ; CHECK-NEXT: cmp r4, #0
661 ; CHECK-NEXT: it eq
662 ; CHECK-NEXT: moveq.w r8, #-2147483648
663 ; CHECK-NEXT: ldr.w r10, [sp, #16] @ 4-byte Reload
664 ; CHECK-NEXT: ldr r3, [sp, #20] @ 4-byte Reload
665 ; CHECK-NEXT: mov r0, r11
666 ; CHECK-NEXT: mov r1, r5
667 ; CHECK-NEXT: mov r2, r10
668 ; CHECK-NEXT: bl __aeabi_dcmpgt
669 ; CHECK-NEXT: cmp r0, #0
670 ; CHECK-NEXT: mov r0, r11
671 ; CHECK-NEXT: mov r1, r5
672 ; CHECK-NEXT: mov r2, r11
673 ; CHECK-NEXT: mov r3, r5
674 ; CHECK-NEXT: vmov r7, r4, d9
675 ; CHECK-NEXT: it ne
676 ; CHECK-NEXT: mvnne r8, #-2147483648
677 ; CHECK-NEXT: bl __aeabi_dcmpun
678 ; CHECK-NEXT: cmp r0, #0
679 ; CHECK-NEXT: it ne
680 ; CHECK-NEXT: movne.w r8, #0
681 ; CHECK-NEXT: ldr r3, [sp] @ 4-byte Reload
682 ; CHECK-NEXT: mov r0, r7
683 ; CHECK-NEXT: mov r1, r4
684 ; CHECK-NEXT: mov r2, r6
685 ; CHECK-NEXT: bl __aeabi_dcmpge
686 ; CHECK-NEXT: mov r5, r0
687 ; CHECK-NEXT: mov r0, r7
688 ; CHECK-NEXT: mov r1, r4
689 ; CHECK-NEXT: bl __aeabi_d2lz
690 ; CHECK-NEXT: mov r6, r0
691 ; CHECK-NEXT: cmp r5, #0
692 ; CHECK-NEXT: it eq
693 ; CHECK-NEXT: moveq.w r6, #-2147483648
694 ; CHECK-NEXT: ldr r3, [sp, #20] @ 4-byte Reload
695 ; CHECK-NEXT: mov r0, r7
696 ; CHECK-NEXT: mov r1, r4
697 ; CHECK-NEXT: mov r2, r10
698 ; CHECK-NEXT: bl __aeabi_dcmpgt
699 ; CHECK-NEXT: cmp r0, #0
700 ; CHECK-NEXT: mov r0, r7
701 ; CHECK-NEXT: mov r1, r4
702 ; CHECK-NEXT: mov r2, r7
703 ; CHECK-NEXT: mov r3, r4
704 ; CHECK-NEXT: it ne
705 ; CHECK-NEXT: mvnne r6, #-2147483648
706 ; CHECK-NEXT: bl __aeabi_dcmpun
707 ; CHECK-NEXT: cmp r0, #0
708 ; CHECK-NEXT: it ne
709 ; CHECK-NEXT: movne r6, #0
710 ; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
711 ; CHECK-NEXT: vmov q0[2], q0[0], r9, r0
712 ; CHECK-NEXT: vmov q0[3], q0[1], r6, r8
713 ; CHECK-NEXT: add sp, #24
714 ; CHECK-NEXT: vpop {d8, d9, d10, d11}
715 ; CHECK-NEXT: add sp, #4
716 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
717 ; CHECK-NEXT: .p2align 3
718 ; CHECK-NEXT: @ %bb.1:
719 ; CHECK-NEXT: .LCPI11_0:
720 ; CHECK-NEXT: .long 0 @ double -2147483648
721 ; CHECK-NEXT: .long 3252682752
722 ; CHECK-NEXT: .LCPI11_1:
723 ; CHECK-NEXT: .long 4290772992 @ double 2147483647
724 ; CHECK-NEXT: .long 1105199103
725 %x = call <4 x i32> @llvm.fptosi.sat.v4f64.v4i32(<4 x double> %f)
726 ret <4 x i32> %x
727 }
729 define arm_aapcs_vfpcc <5 x i32> @test_signed_v5f64_v5i32(<5 x double> %f) {
730 ; CHECK-LABEL: test_signed_v5f64_v5i32:
731 ; CHECK: @ %bb.0:
732 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
733 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
734 ; CHECK-NEXT: .pad #4
735 ; CHECK-NEXT: sub sp, #4
736 ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
737 ; CHECK-NEXT: vpush {d8, d9, d10, d11}
738 ; CHECK-NEXT: .pad #32
739 ; CHECK-NEXT: sub sp, #32
740 ; CHECK-NEXT: vmov.f32 s16, s0
741 ; CHECK-NEXT: str r0, [sp, #24] @ 4-byte Spill
742 ; CHECK-NEXT: vmov.f32 s17, s1
743 ; CHECK-NEXT: vldr d0, .LCPI12_0
744 ; CHECK-NEXT: vmov r7, r5, d4
745 ; CHECK-NEXT: vmov r2, r3, d0
746 ; CHECK-NEXT: vmov.f32 s18, s6
747 ; CHECK-NEXT: vmov.f32 s20, s4
748 ; CHECK-NEXT: vmov.f32 s22, s2
749 ; CHECK-NEXT: vmov.f32 s19, s7
750 ; CHECK-NEXT: vmov.f32 s21, s5
751 ; CHECK-NEXT: vmov.f32 s23, s3
752 ; CHECK-NEXT: str r2, [sp, #28] @ 4-byte Spill
753 ; CHECK-NEXT: mov r0, r7
754 ; CHECK-NEXT: mov r1, r5
755 ; CHECK-NEXT: str r3, [sp, #20] @ 4-byte Spill
756 ; CHECK-NEXT: bl __aeabi_dcmpge
757 ; CHECK-NEXT: mov r11, r0
758 ; CHECK-NEXT: mov r0, r7
759 ; CHECK-NEXT: mov r1, r5
760 ; CHECK-NEXT: bl __aeabi_d2lz
761 ; CHECK-NEXT: mov r4, r0
762 ; CHECK-NEXT: vmov r1, r0, d10
763 ; CHECK-NEXT: vldr d0, .LCPI12_1
764 ; CHECK-NEXT: vmov r6, r8, d9
765 ; CHECK-NEXT: cmp.w r11, #0
766 ; CHECK-NEXT: vmov r10, r3, d0
767 ; CHECK-NEXT: strd r1, r0, [sp, #8] @ 8-byte Folded Spill
768 ; CHECK-NEXT: vmov r9, r0, d11
769 ; CHECK-NEXT: mov r1, r5
770 ; CHECK-NEXT: mov r2, r10
771 ; CHECK-NEXT: mov r11, r3
772 ; CHECK-NEXT: str r0, [sp, #4] @ 4-byte Spill
773 ; CHECK-NEXT: mov r0, r7
774 ; CHECK-NEXT: it eq
775 ; CHECK-NEXT: moveq.w r4, #-2147483648
776 ; CHECK-NEXT: str.w r10, [sp] @ 4-byte Spill
777 ; CHECK-NEXT: bl __aeabi_dcmpgt
778 ; CHECK-NEXT: cmp r0, #0
779 ; CHECK-NEXT: mov r0, r7
780 ; CHECK-NEXT: mov r1, r5
781 ; CHECK-NEXT: mov r2, r7
782 ; CHECK-NEXT: mov r3, r5
783 ; CHECK-NEXT: it ne
784 ; CHECK-NEXT: mvnne r4, #-2147483648
785 ; CHECK-NEXT: bl __aeabi_dcmpun
786 ; CHECK-NEXT: cmp r0, #0
787 ; CHECK-NEXT: it ne
788 ; CHECK-NEXT: movne r4, #0
789 ; CHECK-NEXT: ldr r0, [sp, #24] @ 4-byte Reload
790 ; CHECK-NEXT: mov r1, r8
791 ; CHECK-NEXT: str r4, [r0, #16]
792 ; CHECK-NEXT: mov r0, r6
793 ; CHECK-NEXT: ldr r7, [sp, #28] @ 4-byte Reload
794 ; CHECK-NEXT: ldr r5, [sp, #20] @ 4-byte Reload
795 ; CHECK-NEXT: mov r2, r7
796 ; CHECK-NEXT: mov r3, r5
797 ; CHECK-NEXT: bl __aeabi_dcmpge
798 ; CHECK-NEXT: mov r4, r0
799 ; CHECK-NEXT: mov r0, r6
800 ; CHECK-NEXT: mov r1, r8
801 ; CHECK-NEXT: bl __aeabi_d2lz
802 ; CHECK-NEXT: cmp r4, #0
803 ; CHECK-NEXT: it eq
804 ; CHECK-NEXT: moveq.w r0, #-2147483648
805 ; CHECK-NEXT: mov r4, r0
806 ; CHECK-NEXT: mov r2, r10
807 ; CHECK-NEXT: mov r0, r6
808 ; CHECK-NEXT: mov r1, r8
809 ; CHECK-NEXT: mov r3, r11
810 ; CHECK-NEXT: mov r10, r11
811 ; CHECK-NEXT: bl __aeabi_dcmpgt
812 ; CHECK-NEXT: cmp r0, #0
813 ; CHECK-NEXT: mov r0, r6
814 ; CHECK-NEXT: mov r1, r8
815 ; CHECK-NEXT: mov r2, r6
816 ; CHECK-NEXT: mov r3, r8
817 ; CHECK-NEXT: it ne
818 ; CHECK-NEXT: mvnne r4, #-2147483648
819 ; CHECK-NEXT: bl __aeabi_dcmpun
820 ; CHECK-NEXT: cmp r0, #0
821 ; CHECK-NEXT: it ne
822 ; CHECK-NEXT: movne r4, #0
823 ; CHECK-NEXT: ldr r6, [sp, #4] @ 4-byte Reload
824 ; CHECK-NEXT: mov r0, r9
825 ; CHECK-NEXT: mov r2, r7
826 ; CHECK-NEXT: mov r3, r5
827 ; CHECK-NEXT: str r4, [sp, #16] @ 4-byte Spill
828 ; CHECK-NEXT: mov r1, r6
829 ; CHECK-NEXT: bl __aeabi_dcmpge
830 ; CHECK-NEXT: mov r4, r0
831 ; CHECK-NEXT: mov r0, r9
832 ; CHECK-NEXT: mov r1, r6
833 ; CHECK-NEXT: bl __aeabi_d2lz
834 ; CHECK-NEXT: mov r8, r0
835 ; CHECK-NEXT: cmp r4, #0
836 ; CHECK-NEXT: it eq
837 ; CHECK-NEXT: moveq.w r8, #-2147483648
838 ; CHECK-NEXT: ldr.w r11, [sp] @ 4-byte Reload
839 ; CHECK-NEXT: mov r0, r9
840 ; CHECK-NEXT: mov r1, r6
841 ; CHECK-NEXT: mov r3, r10
842 ; CHECK-NEXT: mov r2, r11
843 ; CHECK-NEXT: bl __aeabi_dcmpgt
844 ; CHECK-NEXT: cmp r0, #0
845 ; CHECK-NEXT: mov r0, r9
846 ; CHECK-NEXT: mov r1, r6
847 ; CHECK-NEXT: mov r2, r9
848 ; CHECK-NEXT: mov r3, r6
849 ; CHECK-NEXT: it ne
850 ; CHECK-NEXT: mvnne r8, #-2147483648
851 ; CHECK-NEXT: bl __aeabi_dcmpun
852 ; CHECK-NEXT: cmp r0, #0
853 ; CHECK-NEXT: it ne
854 ; CHECK-NEXT: movne.w r8, #0
855 ; CHECK-NEXT: ldr r7, [sp, #8] @ 4-byte Reload
856 ; CHECK-NEXT: ldr r5, [sp, #12] @ 4-byte Reload
857 ; CHECK-NEXT: ldr.w r9, [sp, #20] @ 4-byte Reload
858 ; CHECK-NEXT: ldr r2, [sp, #28] @ 4-byte Reload
859 ; CHECK-NEXT: mov r0, r7
860 ; CHECK-NEXT: mov r1, r5
861 ; CHECK-NEXT: mov r3, r9
862 ; CHECK-NEXT: bl __aeabi_dcmpge
863 ; CHECK-NEXT: mov r6, r0
864 ; CHECK-NEXT: mov r0, r7
865 ; CHECK-NEXT: mov r1, r5
866 ; CHECK-NEXT: bl __aeabi_d2lz
867 ; CHECK-NEXT: mov r4, r0
868 ; CHECK-NEXT: mov r0, r7
869 ; CHECK-NEXT: mov r1, r5
870 ; CHECK-NEXT: mov r2, r11
871 ; CHECK-NEXT: mov r3, r10
872 ; CHECK-NEXT: cmp r6, #0
873 ; CHECK-NEXT: it eq
874 ; CHECK-NEXT: moveq.w r4, #-2147483648
875 ; CHECK-NEXT: bl __aeabi_dcmpgt
876 ; CHECK-NEXT: cmp r0, #0
877 ; CHECK-NEXT: mov r0, r7
878 ; CHECK-NEXT: mov r1, r5
879 ; CHECK-NEXT: mov r2, r7
880 ; CHECK-NEXT: mov r3, r5
881 ; CHECK-NEXT: it ne
882 ; CHECK-NEXT: mvnne r4, #-2147483648
883 ; CHECK-NEXT: bl __aeabi_dcmpun
884 ; CHECK-NEXT: vmov r7, r6, d8
885 ; CHECK-NEXT: cmp r0, #0
886 ; CHECK-NEXT: it ne
887 ; CHECK-NEXT: movne r4, #0
888 ; CHECK-NEXT: ldr r2, [sp, #28] @ 4-byte Reload
889 ; CHECK-NEXT: mov r3, r9
890 ; CHECK-NEXT: mov r0, r7
891 ; CHECK-NEXT: mov r1, r6
892 ; CHECK-NEXT: bl __aeabi_dcmpge
893 ; CHECK-NEXT: mov r9, r0
894 ; CHECK-NEXT: mov r0, r7
895 ; CHECK-NEXT: mov r1, r6
896 ; CHECK-NEXT: bl __aeabi_d2lz
897 ; CHECK-NEXT: mov r5, r0
898 ; CHECK-NEXT: mov r0, r7
899 ; CHECK-NEXT: mov r1, r6
900 ; CHECK-NEXT: mov r2, r11
901 ; CHECK-NEXT: mov r3, r10
902 ; CHECK-NEXT: cmp.w r9, #0
903 ; CHECK-NEXT: it eq
904 ; CHECK-NEXT: moveq.w r5, #-2147483648
905 ; CHECK-NEXT: bl __aeabi_dcmpgt
906 ; CHECK-NEXT: cmp r0, #0
907 ; CHECK-NEXT: mov r0, r7
908 ; CHECK-NEXT: mov r1, r6
909 ; CHECK-NEXT: mov r2, r7
910 ; CHECK-NEXT: mov r3, r6
911 ; CHECK-NEXT: it ne
912 ; CHECK-NEXT: mvnne r5, #-2147483648
913 ; CHECK-NEXT: bl __aeabi_dcmpun
914 ; CHECK-NEXT: cmp r0, #0
915 ; CHECK-NEXT: it ne
916 ; CHECK-NEXT: movne r5, #0
917 ; CHECK-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
918 ; CHECK-NEXT: vmov q0[2], q0[0], r5, r4
919 ; CHECK-NEXT: vmov q0[3], q0[1], r8, r0
920 ; CHECK-NEXT: ldr r0, [sp, #24] @ 4-byte Reload
921 ; CHECK-NEXT: vstrw.32 q0, [r0]
922 ; CHECK-NEXT: add sp, #32
923 ; CHECK-NEXT: vpop {d8, d9, d10, d11}
924 ; CHECK-NEXT: add sp, #4
925 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
926 ; CHECK-NEXT: .p2align 3
927 ; CHECK-NEXT: @ %bb.1:
928 ; CHECK-NEXT: .LCPI12_0:
929 ; CHECK-NEXT: .long 0 @ double -2147483648
930 ; CHECK-NEXT: .long 3252682752
931 ; CHECK-NEXT: .LCPI12_1:
932 ; CHECK-NEXT: .long 4290772992 @ double 2147483647
933 ; CHECK-NEXT: .long 1105199103
934 %x = call <5 x i32> @llvm.fptosi.sat.v5f64.v5i32(<5 x double> %f)
935 ret <5 x i32> %x
936 }
938 define arm_aapcs_vfpcc <6 x i32> @test_signed_v6f64_v6i32(<6 x double> %f) {
939 ; CHECK-LABEL: test_signed_v6f64_v6i32:
940 ; CHECK: @ %bb.0:
941 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
942 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
943 ; CHECK-NEXT: .pad #4
944 ; CHECK-NEXT: sub sp, #4
945 ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12}
946 ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12}
947 ; CHECK-NEXT: .pad #40
948 ; CHECK-NEXT: sub sp, #40
949 ; CHECK-NEXT: vmov.f32 s16, s0
950 ; CHECK-NEXT: str r0, [sp, #28] @ 4-byte Spill
951 ; CHECK-NEXT: vmov.f32 s17, s1
952 ; CHECK-NEXT: vldr d0, .LCPI13_0
953 ; CHECK-NEXT: vmov r6, r4, d5
954 ; CHECK-NEXT: vmov r2, r3, d0
955 ; CHECK-NEXT: vmov.f32 s20, s8
956 ; CHECK-NEXT: vmov.f32 s22, s6
957 ; CHECK-NEXT: vmov.f32 s18, s4
958 ; CHECK-NEXT: vmov.f32 s24, s2
959 ; CHECK-NEXT: vmov.f32 s21, s9
960 ; CHECK-NEXT: vmov.f32 s23, s7
961 ; CHECK-NEXT: vmov.f32 s19, s5
962 ; CHECK-NEXT: vmov.f32 s25, s3
963 ; CHECK-NEXT: str r2, [sp, #36] @ 4-byte Spill
964 ; CHECK-NEXT: mov r0, r6
965 ; CHECK-NEXT: mov r1, r4
966 ; CHECK-NEXT: str r3, [sp, #24] @ 4-byte Spill
967 ; CHECK-NEXT: bl __aeabi_dcmpge
968 ; CHECK-NEXT: mov r9, r0
969 ; CHECK-NEXT: mov r0, r6
970 ; CHECK-NEXT: mov r1, r4
971 ; CHECK-NEXT: bl __aeabi_d2lz
972 ; CHECK-NEXT: vldr d0, .LCPI13_1
973 ; CHECK-NEXT: mov r5, r0
974 ; CHECK-NEXT: vmov r1, r0, d12
975 ; CHECK-NEXT: cmp.w r9, #0
976 ; CHECK-NEXT: vmov r2, r3, d0
977 ; CHECK-NEXT: vmov r7, r8, d10
978 ; CHECK-NEXT: vmov r11, r10, d11
979 ; CHECK-NEXT: str r3, [sp, #32] @ 4-byte Spill
980 ; CHECK-NEXT: strd r1, r0, [sp, #8] @ 8-byte Folded Spill
981 ; CHECK-NEXT: mov r0, r6
982 ; CHECK-NEXT: mov r1, r4
983 ; CHECK-NEXT: it eq
984 ; CHECK-NEXT: moveq.w r5, #-2147483648
985 ; CHECK-NEXT: mov r9, r2
986 ; CHECK-NEXT: str r2, [sp, #20] @ 4-byte Spill
987 ; CHECK-NEXT: bl __aeabi_dcmpgt
988 ; CHECK-NEXT: cmp r0, #0
989 ; CHECK-NEXT: mov r0, r6
990 ; CHECK-NEXT: mov r1, r4
991 ; CHECK-NEXT: mov r2, r6
992 ; CHECK-NEXT: mov r3, r4
993 ; CHECK-NEXT: it ne
994 ; CHECK-NEXT: mvnne r5, #-2147483648
995 ; CHECK-NEXT: bl __aeabi_dcmpun
996 ; CHECK-NEXT: cmp r0, #0
997 ; CHECK-NEXT: it ne
998 ; CHECK-NEXT: movne r5, #0
999 ; CHECK-NEXT: ldr r6, [sp, #28] @ 4-byte Reload
1000 ; CHECK-NEXT: mov r0, r7
1001 ; CHECK-NEXT: mov r1, r8
1002 ; CHECK-NEXT: str r5, [r6, #20]
1003 ; CHECK-NEXT: ldr r2, [sp, #36] @ 4-byte Reload
1004 ; CHECK-NEXT: ldr r3, [sp, #24] @ 4-byte Reload
1005 ; CHECK-NEXT: bl __aeabi_dcmpge
1006 ; CHECK-NEXT: mov r4, r0
1007 ; CHECK-NEXT: mov r0, r7
1008 ; CHECK-NEXT: mov r1, r8
1009 ; CHECK-NEXT: bl __aeabi_d2lz
1010 ; CHECK-NEXT: mov r5, r0
1011 ; CHECK-NEXT: cmp r4, #0
1012 ; CHECK-NEXT: it eq
1013 ; CHECK-NEXT: moveq.w r5, #-2147483648
1014 ; CHECK-NEXT: ldr r3, [sp, #32] @ 4-byte Reload
1015 ; CHECK-NEXT: mov r0, r7
1016 ; CHECK-NEXT: mov r1, r8
1017 ; CHECK-NEXT: mov r2, r9
1018 ; CHECK-NEXT: bl __aeabi_dcmpgt
1019 ; CHECK-NEXT: vmov r2, r1, d9
1020 ; CHECK-NEXT: cmp r0, #0
1021 ; CHECK-NEXT: mov r0, r7
1022 ; CHECK-NEXT: mov r3, r8
1023 ; CHECK-NEXT: strd r2, r1, [sp] @ 8-byte Folded Spill
1024 ; CHECK-NEXT: mov r1, r8
1025 ; CHECK-NEXT: mov r2, r7
1026 ; CHECK-NEXT: it ne
1027 ; CHECK-NEXT: mvnne r5, #-2147483648
1028 ; CHECK-NEXT: bl __aeabi_dcmpun
1029 ; CHECK-NEXT: cmp r0, #0
1030 ; CHECK-NEXT: it ne
1031 ; CHECK-NEXT: movne r5, #0
1032 ; CHECK-NEXT: str r5, [r6, #16]
1033 ; CHECK-NEXT: mov r0, r11
1034 ; CHECK-NEXT: ldr.w r8, [sp, #36] @ 4-byte Reload
1035 ; CHECK-NEXT: mov r1, r10
1036 ; CHECK-NEXT: ldr.w r9, [sp, #24] @ 4-byte Reload
1037 ; CHECK-NEXT: mov r2, r8
1038 ; CHECK-NEXT: mov r3, r9
1039 ; CHECK-NEXT: bl __aeabi_dcmpge
1040 ; CHECK-NEXT: mov r4, r0
1041 ; CHECK-NEXT: mov r0, r11
1042 ; CHECK-NEXT: mov r1, r10
1043 ; CHECK-NEXT: bl __aeabi_d2lz
1044 ; CHECK-NEXT: cmp r4, #0
1045 ; CHECK-NEXT: it eq
1046 ; CHECK-NEXT: moveq.w r0, #-2147483648
1047 ; CHECK-NEXT: ldr r7, [sp, #32] @ 4-byte Reload
1048 ; CHECK-NEXT: mov r4, r0
1049 ; CHECK-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
1050 ; CHECK-NEXT: mov r0, r11
1051 ; CHECK-NEXT: mov r1, r10
1052 ; CHECK-NEXT: mov r3, r7
1053 ; CHECK-NEXT: bl __aeabi_dcmpgt
1054 ; CHECK-NEXT: cmp r0, #0
1055 ; CHECK-NEXT: mov r0, r11
1056 ; CHECK-NEXT: mov r1, r10
1057 ; CHECK-NEXT: mov r2, r11
1058 ; CHECK-NEXT: mov r3, r10
1059 ; CHECK-NEXT: it ne
1060 ; CHECK-NEXT: mvnne r4, #-2147483648
1061 ; CHECK-NEXT: bl __aeabi_dcmpun
1062 ; CHECK-NEXT: cmp r0, #0
1063 ; CHECK-NEXT: it ne
1064 ; CHECK-NEXT: movne r4, #0
1065 ; CHECK-NEXT: ldr r6, [sp, #8] @ 4-byte Reload
1066 ; CHECK-NEXT: mov r2, r8
1067 ; CHECK-NEXT: ldr r5, [sp, #12] @ 4-byte Reload
1068 ; CHECK-NEXT: mov r3, r9
1069 ; CHECK-NEXT: str r4, [sp, #16] @ 4-byte Spill
1070 ; CHECK-NEXT: mov r0, r6
1071 ; CHECK-NEXT: mov r1, r5
1072 ; CHECK-NEXT: bl __aeabi_dcmpge
1073 ; CHECK-NEXT: mov r4, r0
1074 ; CHECK-NEXT: mov r0, r6
1075 ; CHECK-NEXT: mov r1, r5
1076 ; CHECK-NEXT: bl __aeabi_d2lz
1077 ; CHECK-NEXT: mov r10, r0
1078 ; CHECK-NEXT: cmp r4, #0
1079 ; CHECK-NEXT: it eq
1080 ; CHECK-NEXT: moveq.w r10, #-2147483648
1081 ; CHECK-NEXT: ldr.w r11, [sp, #20] @ 4-byte Reload
1082 ; CHECK-NEXT: mov r0, r6
1083 ; CHECK-NEXT: mov r1, r5
1084 ; CHECK-NEXT: mov r3, r7
1085 ; CHECK-NEXT: mov r2, r11
1086 ; CHECK-NEXT: bl __aeabi_dcmpgt
1087 ; CHECK-NEXT: cmp r0, #0
1088 ; CHECK-NEXT: mov r0, r6
1089 ; CHECK-NEXT: mov r1, r5
1090 ; CHECK-NEXT: mov r2, r6
1091 ; CHECK-NEXT: mov r3, r5
1092 ; CHECK-NEXT: it ne
1093 ; CHECK-NEXT: mvnne r10, #-2147483648
1094 ; CHECK-NEXT: bl __aeabi_dcmpun
1095 ; CHECK-NEXT: cmp r0, #0
1096 ; CHECK-NEXT: it ne
1097 ; CHECK-NEXT: movne.w r10, #0
1098 ; CHECK-NEXT: ldr r5, [sp] @ 4-byte Reload
1099 ; CHECK-NEXT: mov r2, r8
1100 ; CHECK-NEXT: ldr r6, [sp, #4] @ 4-byte Reload
1101 ; CHECK-NEXT: mov r3, r9
1102 ; CHECK-NEXT: mov r0, r5
1103 ; CHECK-NEXT: mov r1, r6
1104 ; CHECK-NEXT: bl __aeabi_dcmpge
1105 ; CHECK-NEXT: mov r7, r0
1106 ; CHECK-NEXT: mov r0, r5
1107 ; CHECK-NEXT: mov r1, r6
1108 ; CHECK-NEXT: bl __aeabi_d2lz
1109 ; CHECK-NEXT: mov r4, r0
1110 ; CHECK-NEXT: cmp r7, #0
1111 ; CHECK-NEXT: it eq
1112 ; CHECK-NEXT: moveq.w r4, #-2147483648
1113 ; CHECK-NEXT: ldr.w r8, [sp, #32] @ 4-byte Reload
1114 ; CHECK-NEXT: mov r0, r5
1115 ; CHECK-NEXT: mov r1, r6
1116 ; CHECK-NEXT: mov r2, r11
1117 ; CHECK-NEXT: mov r3, r8
1118 ; CHECK-NEXT: bl __aeabi_dcmpgt
1119 ; CHECK-NEXT: cmp r0, #0
1120 ; CHECK-NEXT: mov r0, r5
1121 ; CHECK-NEXT: mov r1, r6
1122 ; CHECK-NEXT: mov r2, r5
1123 ; CHECK-NEXT: mov r3, r6
1124 ; CHECK-NEXT: it ne
1125 ; CHECK-NEXT: mvnne r4, #-2147483648
1126 ; CHECK-NEXT: bl __aeabi_dcmpun
1127 ; CHECK-NEXT: vmov r7, r6, d8
1128 ; CHECK-NEXT: cmp r0, #0
1129 ; CHECK-NEXT: it ne
1130 ; CHECK-NEXT: movne r4, #0
1131 ; CHECK-NEXT: ldr r2, [sp, #36] @ 4-byte Reload
1132 ; CHECK-NEXT: mov r3, r9
1133 ; CHECK-NEXT: mov r0, r7
1134 ; CHECK-NEXT: mov r1, r6
1135 ; CHECK-NEXT: bl __aeabi_dcmpge
1136 ; CHECK-NEXT: mov r9, r0
1137 ; CHECK-NEXT: mov r0, r7
1138 ; CHECK-NEXT: mov r1, r6
1139 ; CHECK-NEXT: bl __aeabi_d2lz
1140 ; CHECK-NEXT: mov r5, r0
1141 ; CHECK-NEXT: mov r0, r7
1142 ; CHECK-NEXT: mov r1, r6
1143 ; CHECK-NEXT: mov r2, r11
1144 ; CHECK-NEXT: mov r3, r8
1145 ; CHECK-NEXT: cmp.w r9, #0
1146 ; CHECK-NEXT: it eq
1147 ; CHECK-NEXT: moveq.w r5, #-2147483648
1148 ; CHECK-NEXT: bl __aeabi_dcmpgt
1149 ; CHECK-NEXT: cmp r0, #0
1150 ; CHECK-NEXT: mov r0, r7
1151 ; CHECK-NEXT: mov r1, r6
1152 ; CHECK-NEXT: mov r2, r7
1153 ; CHECK-NEXT: mov r3, r6
1154 ; CHECK-NEXT: it ne
1155 ; CHECK-NEXT: mvnne r5, #-2147483648
1156 ; CHECK-NEXT: bl __aeabi_dcmpun
1157 ; CHECK-NEXT: cmp r0, #0
1158 ; CHECK-NEXT: it ne
1159 ; CHECK-NEXT: movne r5, #0
1160 ; CHECK-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
1161 ; CHECK-NEXT: vmov q0[2], q0[0], r5, r4
1162 ; CHECK-NEXT: vmov q0[3], q0[1], r10, r0
1163 ; CHECK-NEXT: ldr r0, [sp, #28] @ 4-byte Reload
1164 ; CHECK-NEXT: vstrw.32 q0, [r0]
1165 ; CHECK-NEXT: add sp, #40
1166 ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12}
1167 ; CHECK-NEXT: add sp, #4
1168 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
1169 ; CHECK-NEXT: .p2align 3
1170 ; CHECK-NEXT: @ %bb.1:
1171 ; CHECK-NEXT: .LCPI13_0:
1172 ; CHECK-NEXT: .long 0 @ double -2147483648
1173 ; CHECK-NEXT: .long 3252682752
1174 ; CHECK-NEXT: .LCPI13_1:
1175 ; CHECK-NEXT: .long 4290772992 @ double 2147483647
1176 ; CHECK-NEXT: .long 1105199103
1177 %x = call <6 x i32> @llvm.fptosi.sat.v6f64.v6i32(<6 x double> %f)
1178 ret <6 x i32> %x
1179 }
1181 ;
1182 ; FP16 to signed 32-bit -- Vector size variation
1183 ;
1185 declare <1 x i32> @llvm.fptosi.sat.v1f16.v1i32 (<1 x half>)
1186 declare <2 x i32> @llvm.fptosi.sat.v2f16.v2i32 (<2 x half>)
1187 declare <3 x i32> @llvm.fptosi.sat.v3f16.v3i32 (<3 x half>)
1188 declare <4 x i32> @llvm.fptosi.sat.v4f16.v4i32 (<4 x half>)
1189 declare <5 x i32> @llvm.fptosi.sat.v5f16.v5i32 (<5 x half>)
1190 declare <6 x i32> @llvm.fptosi.sat.v6f16.v6i32 (<6 x half>)
1191 declare <7 x i32> @llvm.fptosi.sat.v7f16.v7i32 (<7 x half>)
1192 declare <8 x i32> @llvm.fptosi.sat.v8f16.v8i32 (<8 x half>)
1194 define arm_aapcs_vfpcc <1 x i32> @test_signed_v1f16_v1i32(<1 x half> %f) {
1195 ; CHECK-LABEL: test_signed_v1f16_v1i32:
1196 ; CHECK: @ %bb.0:
1197 ; CHECK-NEXT: vcvt.s32.f16 s0, s0
1198 ; CHECK-NEXT: vmov r0, s0
1199 ; CHECK-NEXT: bx lr
1200 %x = call <1 x i32> @llvm.fptosi.sat.v1f16.v1i32(<1 x half> %f)
1201 ret <1 x i32> %x
1202 }
1204 define arm_aapcs_vfpcc <2 x i32> @test_signed_v2f16_v2i32(<2 x half> %f) {
1205 ; CHECK-LABEL: test_signed_v2f16_v2i32:
1206 ; CHECK: @ %bb.0:
1207 ; CHECK-NEXT: .save {r4, r5, r7, lr}
1208 ; CHECK-NEXT: push {r4, r5, r7, lr}
1209 ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
1210 ; CHECK-NEXT: vpush {d8, d9, d10, d11}
1211 ; CHECK-NEXT: vmov q4, q0
1212 ; CHECK-NEXT: vcvtt.f32.f16 s18, s16
1213 ; CHECK-NEXT: vmov r0, s18
1214 ; CHECK-NEXT: bl __aeabi_f2lz
1215 ; CHECK-NEXT: vcvtb.f32.f16 s16, s16
1216 ; CHECK-NEXT: mov r5, r0
1217 ; CHECK-NEXT: vmov r0, s16
1218 ; CHECK-NEXT: vldr s20, .LCPI15_0
1219 ; CHECK-NEXT: vldr s22, .LCPI15_1
1220 ; CHECK-NEXT: mov r4, r1
1221 ; CHECK-NEXT: vcmp.f32 s18, s20
1222 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1223 ; CHECK-NEXT: itt lt
1224 ; CHECK-NEXT: movlt.w r4, #-1
1225 ; CHECK-NEXT: movlt.w r5, #-2147483648
1226 ; CHECK-NEXT: vcmp.f32 s18, s22
1227 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1228 ; CHECK-NEXT: itt gt
1229 ; CHECK-NEXT: mvngt r5, #-2147483648
1230 ; CHECK-NEXT: movgt r4, #0
1231 ; CHECK-NEXT: vcmp.f32 s18, s18
1232 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1233 ; CHECK-NEXT: itt vs
1234 ; CHECK-NEXT: movvs r4, #0
1235 ; CHECK-NEXT: movvs r5, #0
1236 ; CHECK-NEXT: bl __aeabi_f2lz
1237 ; CHECK-NEXT: vcmp.f32 s16, s20
1238 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1239 ; CHECK-NEXT: itt lt
1240 ; CHECK-NEXT: movlt.w r0, #-2147483648
1241 ; CHECK-NEXT: movlt.w r1, #-1
1242 ; CHECK-NEXT: vcmp.f32 s16, s22
1243 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1244 ; CHECK-NEXT: itt gt
1245 ; CHECK-NEXT: movgt r1, #0
1246 ; CHECK-NEXT: mvngt r0, #-2147483648
1247 ; CHECK-NEXT: vcmp.f32 s16, s16
1248 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1249 ; CHECK-NEXT: itt vs
1250 ; CHECK-NEXT: movvs r0, #0
1251 ; CHECK-NEXT: movvs r1, #0
1252 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
1253 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r4
1254 ; CHECK-NEXT: vpop {d8, d9, d10, d11}
1255 ; CHECK-NEXT: pop {r4, r5, r7, pc}
1256 ; CHECK-NEXT: .p2align 2
1257 ; CHECK-NEXT: @ %bb.1:
1258 ; CHECK-NEXT: .LCPI15_0:
1259 ; CHECK-NEXT: .long 0xcf000000 @ float -2.14748365E+9
1260 ; CHECK-NEXT: .LCPI15_1:
1261 ; CHECK-NEXT: .long 0x4effffff @ float 2.14748352E+9
1262 %x = call <2 x i32> @llvm.fptosi.sat.v2f16.v2i32(<2 x half> %f)
1263 ret <2 x i32> %x
1264 }
1266 define arm_aapcs_vfpcc <3 x i32> @test_signed_v3f16_v3i32(<3 x half> %f) {
1267 ; CHECK-LABEL: test_signed_v3f16_v3i32:
1268 ; CHECK: @ %bb.0:
1269 ; CHECK-NEXT: vcvt.s32.f16 s6, s0
1270 ; CHECK-NEXT: vcvt.s32.f16 s0, s1
1271 ; CHECK-NEXT: vcvt.s32.f16 s4, s2
1272 ; CHECK-NEXT: vmov r0, s0
1273 ; CHECK-NEXT: vmov.32 q0[1], r0
1274 ; CHECK-NEXT: vmov r0, s4
1275 ; CHECK-NEXT: vmov r1, s6
1276 ; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
1277 ; CHECK-NEXT: bx lr
1278 %x = call <3 x i32> @llvm.fptosi.sat.v3f16.v3i32(<3 x half> %f)
1279 ret <3 x i32> %x
1280 }
1282 define arm_aapcs_vfpcc <4 x i32> @test_signed_v4f16_v4i32(<4 x half> %f) {
1283 ; CHECK-LABEL: test_signed_v4f16_v4i32:
1284 ; CHECK: @ %bb.0:
1285 ; CHECK-NEXT: vmovx.f16 s2, s1
1286 ; CHECK-NEXT: vcvt.s32.f16 s4, s2
1287 ; CHECK-NEXT: vmovx.f16 s2, s0
1288 ; CHECK-NEXT: vcvt.s32.f16 s6, s2
1289 ; CHECK-NEXT: vcvt.s32.f16 s2, s1
1290 ; CHECK-NEXT: vcvt.s32.f16 s0, s0
1291 ; CHECK-NEXT: vmov r0, s2
1292 ; CHECK-NEXT: vmov r1, s0
1293 ; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
1294 ; CHECK-NEXT: vmov r0, s4
1295 ; CHECK-NEXT: vmov r1, s6
1296 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
1297 ; CHECK-NEXT: bx lr
1298 %x = call <4 x i32> @llvm.fptosi.sat.v4f16.v4i32(<4 x half> %f)
1299 ret <4 x i32> %x
1300 }
1302 define arm_aapcs_vfpcc <5 x i32> @test_signed_v5f16_v5i32(<5 x half> %f) {
1303 ; CHECK-LABEL: test_signed_v5f16_v5i32:
1304 ; CHECK: @ %bb.0:
1305 ; CHECK-NEXT: vmovx.f16 s6, s0
1306 ; CHECK-NEXT: vmovx.f16 s4, s1
1307 ; CHECK-NEXT: vcvt.s32.f16 s8, s1
1308 ; CHECK-NEXT: vcvt.s32.f16 s0, s0
1309 ; CHECK-NEXT: vcvt.s32.f16 s4, s4
1310 ; CHECK-NEXT: vcvt.s32.f16 s6, s6
1311 ; CHECK-NEXT: vmov r1, s8
1312 ; CHECK-NEXT: vcvt.s32.f16 s2, s2
1313 ; CHECK-NEXT: vmov r2, s0
1314 ; CHECK-NEXT: vmov q2[2], q2[0], r2, r1
1315 ; CHECK-NEXT: vmov r1, s4
1316 ; CHECK-NEXT: vmov r2, s6
1317 ; CHECK-NEXT: vmov q2[3], q2[1], r2, r1
1318 ; CHECK-NEXT: vmov r1, s2
1319 ; CHECK-NEXT: str r1, [r0, #16]
1320 ; CHECK-NEXT: vstrw.32 q2, [r0]
1321 ; CHECK-NEXT: bx lr
1322 %x = call <5 x i32> @llvm.fptosi.sat.v5f16.v5i32(<5 x half> %f)
1323 ret <5 x i32> %x
1324 }
1326 define arm_aapcs_vfpcc <6 x i32> @test_signed_v6f16_v6i32(<6 x half> %f) {
1327 ; CHECK-LABEL: test_signed_v6f16_v6i32:
1328 ; CHECK: @ %bb.0:
1329 ; CHECK-NEXT: vmovx.f16 s8, s0
1330 ; CHECK-NEXT: vmovx.f16 s6, s1
1331 ; CHECK-NEXT: vcvt.s32.f16 s10, s1
1332 ; CHECK-NEXT: vcvt.s32.f16 s0, s0
1333 ; CHECK-NEXT: vcvt.s32.f16 s4, s2
1334 ; CHECK-NEXT: vmovx.f16 s2, s2
1335 ; CHECK-NEXT: vcvt.s32.f16 s6, s6
1336 ; CHECK-NEXT: vcvt.s32.f16 s8, s8
1337 ; CHECK-NEXT: vmov r1, s10
1338 ; CHECK-NEXT: vcvt.s32.f16 s2, s2
1339 ; CHECK-NEXT: vmov r2, s0
1340 ; CHECK-NEXT: vmov q3[2], q3[0], r2, r1
1341 ; CHECK-NEXT: vmov r1, s6
1342 ; CHECK-NEXT: vmov r2, s8
1343 ; CHECK-NEXT: vmov q3[3], q3[1], r2, r1
1344 ; CHECK-NEXT: vmov r1, s2
1345 ; CHECK-NEXT: vmov r2, s4
1346 ; CHECK-NEXT: strd r2, r1, [r0, #16]
1347 ; CHECK-NEXT: vstrw.32 q3, [r0]
1348 ; CHECK-NEXT: bx lr
1349 %x = call <6 x i32> @llvm.fptosi.sat.v6f16.v6i32(<6 x half> %f)
1350 ret <6 x i32> %x
1351 }
1353 define arm_aapcs_vfpcc <7 x i32> @test_signed_v7f16_v7i32(<7 x half> %f) {
1354 ; CHECK-LABEL: test_signed_v7f16_v7i32:
1355 ; CHECK: @ %bb.0:
1356 ; CHECK-NEXT: vmovx.f16 s10, s0
1357 ; CHECK-NEXT: vmovx.f16 s8, s1
1358 ; CHECK-NEXT: vcvt.s32.f16 s12, s1
1359 ; CHECK-NEXT: vcvt.s32.f16 s0, s0
1360 ; CHECK-NEXT: vcvt.s32.f16 s4, s2
1361 ; CHECK-NEXT: vmovx.f16 s2, s2
1362 ; CHECK-NEXT: vcvt.s32.f16 s8, s8
1363 ; CHECK-NEXT: vcvt.s32.f16 s10, s10
1364 ; CHECK-NEXT: vmov r1, s12
1365 ; CHECK-NEXT: vcvt.s32.f16 s2, s2
1366 ; CHECK-NEXT: vmov r2, s0
1367 ; CHECK-NEXT: vcvt.s32.f16 s6, s3
1368 ; CHECK-NEXT: vmov q3[2], q3[0], r2, r1
1369 ; CHECK-NEXT: vmov r1, s8
1370 ; CHECK-NEXT: vmov r2, s10
1371 ; CHECK-NEXT: vmov q3[3], q3[1], r2, r1
1372 ; CHECK-NEXT: vmov r1, s2
1373 ; CHECK-NEXT: vmov r2, s4
1374 ; CHECK-NEXT: vmov r3, s6
1375 ; CHECK-NEXT: strd r2, r1, [r0, #16]
1376 ; CHECK-NEXT: str r3, [r0, #24]
1377 ; CHECK-NEXT: vstrw.32 q3, [r0]
1378 ; CHECK-NEXT: bx lr
1379 %x = call <7 x i32> @llvm.fptosi.sat.v7f16.v7i32(<7 x half> %f)
1380 ret <7 x i32> %x
1381 }
1383 define arm_aapcs_vfpcc <8 x i32> @test_signed_v8f16_v8i32(<8 x half> %f) {
1384 ; CHECK-LABEL: test_signed_v8f16_v8i32:
1385 ; CHECK: @ %bb.0:
1386 ; CHECK-NEXT: vmovx.f16 s4, s3
1387 ; CHECK-NEXT: vmovx.f16 s6, s0
1388 ; CHECK-NEXT: vcvt.s32.f16 s8, s4
1389 ; CHECK-NEXT: vmovx.f16 s4, s2
1390 ; CHECK-NEXT: vcvt.s32.f16 s10, s4
1391 ; CHECK-NEXT: vmovx.f16 s4, s1
1392 ; CHECK-NEXT: vcvt.s32.f16 s14, s2
1393 ; CHECK-NEXT: vcvt.s32.f16 s2, s1
1394 ; CHECK-NEXT: vcvt.s32.f16 s0, s0
1395 ; CHECK-NEXT: vcvt.s32.f16 s4, s4
1396 ; CHECK-NEXT: vcvt.s32.f16 s6, s6
1397 ; CHECK-NEXT: vmov r0, s2
1398 ; CHECK-NEXT: vmov r1, s0
1399 ; CHECK-NEXT: vcvt.s32.f16 s12, s3
1400 ; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
1401 ; CHECK-NEXT: vmov r0, s4
1402 ; CHECK-NEXT: vmov r1, s6
1403 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
1404 ; CHECK-NEXT: vmov r0, s12
1405 ; CHECK-NEXT: vmov r1, s14
1406 ; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
1407 ; CHECK-NEXT: vmov r0, s8
1408 ; CHECK-NEXT: vmov r1, s10
1409 ; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
1410 ; CHECK-NEXT: bx lr
1411 %x = call <8 x i32> @llvm.fptosi.sat.v8f16.v8i32(<8 x half> %f)
1412 ret <8 x i32> %x
1413 }
1415 ;
1416 ; 2-Vector float to signed integer -- result size variation
1417 ;
1419 declare <4 x i1> @llvm.fptosi.sat.v4f32.v4i1 (<4 x float>)
1420 declare <4 x i8> @llvm.fptosi.sat.v4f32.v4i8 (<4 x float>)
1421 declare <4 x i13> @llvm.fptosi.sat.v4f32.v4i13 (<4 x float>)
1422 declare <4 x i16> @llvm.fptosi.sat.v4f32.v4i16 (<4 x float>)
1423 declare <4 x i19> @llvm.fptosi.sat.v4f32.v4i19 (<4 x float>)
1424 declare <4 x i50> @llvm.fptosi.sat.v4f32.v4i50 (<4 x float>)
1425 declare <4 x i64> @llvm.fptosi.sat.v4f32.v4i64 (<4 x float>)
1426 declare <4 x i100> @llvm.fptosi.sat.v4f32.v4i100(<4 x float>)
1427 declare <4 x i128> @llvm.fptosi.sat.v4f32.v4i128(<4 x float>)
1429 define arm_aapcs_vfpcc <4 x i1> @test_signed_v4f32_v4i1(<4 x float> %f) {
1430 ; CHECK-LABEL: test_signed_v4f32_v4i1:
1431 ; CHECK: @ %bb.0:
1432 ; CHECK-NEXT: vmov.f32 s4, #-1.000000e+00
1433 ; CHECK-NEXT: vldr s6, .LCPI22_0
1434 ; CHECK-NEXT: vmaxnm.f32 s12, s0, s4
1435 ; CHECK-NEXT: vmaxnm.f32 s8, s3, s4
1436 ; CHECK-NEXT: vminnm.f32 s12, s12, s6
1437 ; CHECK-NEXT: vmaxnm.f32 s10, s2, s4
1438 ; CHECK-NEXT: vcvt.s32.f32 s12, s12
1439 ; CHECK-NEXT: vmaxnm.f32 s4, s1, s4
1440 ; CHECK-NEXT: vminnm.f32 s4, s4, s6
1441 ; CHECK-NEXT: vminnm.f32 s10, s10, s6
1442 ; CHECK-NEXT: vcvt.s32.f32 s4, s4
1443 ; CHECK-NEXT: movs r1, #0
1444 ; CHECK-NEXT: vcmp.f32 s0, s0
1445 ; CHECK-NEXT: vminnm.f32 s8, s8, s6
1446 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1447 ; CHECK-NEXT: vcvt.s32.f32 s10, s10
1448 ; CHECK-NEXT: vcmp.f32 s1, s1
1449 ; CHECK-NEXT: vcvt.s32.f32 s8, s8
1450 ; CHECK-NEXT: vmov r2, s12
1451 ; CHECK-NEXT: it vs
1452 ; CHECK-NEXT: movvs r2, #0
1453 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1454 ; CHECK-NEXT: and r2, r2, #1
1455 ; CHECK-NEXT: vcmp.f32 s2, s2
1456 ; CHECK-NEXT: rsb.w r2, r2, #0
1457 ; CHECK-NEXT: bfi r1, r2, #0, #1
1458 ; CHECK-NEXT: vmov r2, s4
1459 ; CHECK-NEXT: it vs
1460 ; CHECK-NEXT: movvs r2, #0
1461 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1462 ; CHECK-NEXT: and r2, r2, #1
1463 ; CHECK-NEXT: vcmp.f32 s3, s3
1464 ; CHECK-NEXT: rsb.w r2, r2, #0
1465 ; CHECK-NEXT: bfi r1, r2, #1, #1
1466 ; CHECK-NEXT: vmov r2, s10
1467 ; CHECK-NEXT: it vs
1468 ; CHECK-NEXT: movvs r2, #0
1469 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1470 ; CHECK-NEXT: and r2, r2, #1
1471 ; CHECK-NEXT: rsb.w r2, r2, #0
1472 ; CHECK-NEXT: bfi r1, r2, #2, #1
1473 ; CHECK-NEXT: vmov r2, s8
1474 ; CHECK-NEXT: it vs
1475 ; CHECK-NEXT: movvs r2, #0
1476 ; CHECK-NEXT: and r2, r2, #1
1477 ; CHECK-NEXT: rsbs r2, r2, #0
1478 ; CHECK-NEXT: bfi r1, r2, #3, #1
1479 ; CHECK-NEXT: strb r1, [r0]
1480 ; CHECK-NEXT: bx lr
1481 ; CHECK-NEXT: .p2align 2
1482 ; CHECK-NEXT: @ %bb.1:
1483 ; CHECK-NEXT: .LCPI22_0:
1484 ; CHECK-NEXT: .long 0x00000000 @ float 0
1485 %x = call <4 x i1> @llvm.fptosi.sat.v4f32.v4i1(<4 x float> %f)
1486 ret <4 x i1> %x
1487 }
1489 define arm_aapcs_vfpcc <4 x i8> @test_signed_v4f32_v4i8(<4 x float> %f) {
1490 ; CHECK-MVE-LABEL: test_signed_v4f32_v4i8:
1491 ; CHECK-MVE: @ %bb.0:
1492 ; CHECK-MVE-NEXT: vldr s4, .LCPI23_0
1493 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
1494 ; CHECK-MVE-NEXT: vldr s6, .LCPI23_1
1495 ; CHECK-MVE-NEXT: vmaxnm.f32 s12, s2, s4
1496 ; CHECK-MVE-NEXT: vmaxnm.f32 s10, s0, s4
1497 ; CHECK-MVE-NEXT: vminnm.f32 s12, s12, s6
1498 ; CHECK-MVE-NEXT: vmaxnm.f32 s8, s3, s4
1499 ; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s6
1500 ; CHECK-MVE-NEXT: vmaxnm.f32 s4, s1, s4
1501 ; CHECK-MVE-NEXT: vcvt.s32.f32 s12, s12
1502 ; CHECK-MVE-NEXT: vminnm.f32 s8, s8, s6
1503 ; CHECK-MVE-NEXT: vminnm.f32 s4, s4, s6
1504 ; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s10
1505 ; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s8
1506 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1507 ; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s4
1508 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
1509 ; CHECK-MVE-NEXT: vmov r0, s12
1510 ; CHECK-MVE-NEXT: it vs
1511 ; CHECK-MVE-NEXT: movvs r0, #0
1512 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1513 ; CHECK-MVE-NEXT: vmov r1, s10
1514 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
1515 ; CHECK-MVE-NEXT: it vs
1516 ; CHECK-MVE-NEXT: movvs r1, #0
1517 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1518 ; CHECK-MVE-NEXT: vmov r2, s8
1519 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
1520 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
1521 ; CHECK-MVE-NEXT: vmov r3, s4
1522 ; CHECK-MVE-NEXT: it vs
1523 ; CHECK-MVE-NEXT: movvs r2, #0
1524 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1525 ; CHECK-MVE-NEXT: it vs
1526 ; CHECK-MVE-NEXT: movvs r3, #0
1527 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r3, r2
1528 ; CHECK-MVE-NEXT: bx lr
1529 ; CHECK-MVE-NEXT: .p2align 2
1530 ; CHECK-MVE-NEXT: @ %bb.1:
1531 ; CHECK-MVE-NEXT: .LCPI23_0:
1532 ; CHECK-MVE-NEXT: .long 0xc3000000 @ float -128
1533 ; CHECK-MVE-NEXT: .LCPI23_1:
1534 ; CHECK-MVE-NEXT: .long 0x42fe0000 @ float 127
1535 ;
1536 ; CHECK-MVEFP-LABEL: test_signed_v4f32_v4i8:
1537 ; CHECK-MVEFP: @ %bb.0:
1538 ; CHECK-MVEFP-NEXT: vmov.i32 q1, #0x7f
1539 ; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
1540 ; CHECK-MVEFP-NEXT: vmvn.i32 q2, #0x7f
1541 ; CHECK-MVEFP-NEXT: vmin.s32 q0, q0, q1
1542 ; CHECK-MVEFP-NEXT: vmax.s32 q0, q0, q2
1543 ; CHECK-MVEFP-NEXT: bx lr
1544 %x = call <4 x i8> @llvm.fptosi.sat.v4f32.v4i8(<4 x float> %f)
1545 ret <4 x i8> %x
1546 }
1548 define arm_aapcs_vfpcc <4 x i13> @test_signed_v4f32_v4i13(<4 x float> %f) {
1549 ; CHECK-MVE-LABEL: test_signed_v4f32_v4i13:
1550 ; CHECK-MVE: @ %bb.0:
1551 ; CHECK-MVE-NEXT: vldr s4, .LCPI24_0
1552 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
1553 ; CHECK-MVE-NEXT: vldr s6, .LCPI24_1
1554 ; CHECK-MVE-NEXT: vmaxnm.f32 s12, s2, s4
1555 ; CHECK-MVE-NEXT: vmaxnm.f32 s10, s0, s4
1556 ; CHECK-MVE-NEXT: vminnm.f32 s12, s12, s6
1557 ; CHECK-MVE-NEXT: vmaxnm.f32 s8, s3, s4
1558 ; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s6
1559 ; CHECK-MVE-NEXT: vmaxnm.f32 s4, s1, s4
1560 ; CHECK-MVE-NEXT: vcvt.s32.f32 s12, s12
1561 ; CHECK-MVE-NEXT: vminnm.f32 s8, s8, s6
1562 ; CHECK-MVE-NEXT: vminnm.f32 s4, s4, s6
1563 ; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s10
1564 ; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s8
1565 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1566 ; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s4
1567 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
1568 ; CHECK-MVE-NEXT: vmov r0, s12
1569 ; CHECK-MVE-NEXT: it vs
1570 ; CHECK-MVE-NEXT: movvs r0, #0
1571 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1572 ; CHECK-MVE-NEXT: vmov r1, s10
1573 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
1574 ; CHECK-MVE-NEXT: it vs
1575 ; CHECK-MVE-NEXT: movvs r1, #0
1576 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1577 ; CHECK-MVE-NEXT: vmov r2, s8
1578 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
1579 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
1580 ; CHECK-MVE-NEXT: vmov r3, s4
1581 ; CHECK-MVE-NEXT: it vs
1582 ; CHECK-MVE-NEXT: movvs r2, #0
1583 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1584 ; CHECK-MVE-NEXT: it vs
1585 ; CHECK-MVE-NEXT: movvs r3, #0
1586 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r3, r2
1587 ; CHECK-MVE-NEXT: bx lr
1588 ; CHECK-MVE-NEXT: .p2align 2
1589 ; CHECK-MVE-NEXT: @ %bb.1:
1590 ; CHECK-MVE-NEXT: .LCPI24_0:
1591 ; CHECK-MVE-NEXT: .long 0xc5800000 @ float -4096
1592 ; CHECK-MVE-NEXT: .LCPI24_1:
1593 ; CHECK-MVE-NEXT: .long 0x457ff000 @ float 4095
1594 ;
1595 ; CHECK-MVEFP-LABEL: test_signed_v4f32_v4i13:
1596 ; CHECK-MVEFP: @ %bb.0:
1597 ; CHECK-MVEFP-NEXT: vmov.i32 q1, #0xfff
1598 ; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
1599 ; CHECK-MVEFP-NEXT: vmvn.i32 q2, #0xfff
1600 ; CHECK-MVEFP-NEXT: vmin.s32 q0, q0, q1
1601 ; CHECK-MVEFP-NEXT: vmax.s32 q0, q0, q2
1602 ; CHECK-MVEFP-NEXT: bx lr
1603 %x = call <4 x i13> @llvm.fptosi.sat.v4f32.v4i13(<4 x float> %f)
1604 ret <4 x i13> %x
1605 }
1607 define arm_aapcs_vfpcc <4 x i16> @test_signed_v4f32_v4i16(<4 x float> %f) {
1608 ; CHECK-MVE-LABEL: test_signed_v4f32_v4i16:
1609 ; CHECK-MVE: @ %bb.0:
1610 ; CHECK-MVE-NEXT: vldr s4, .LCPI25_0
1611 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
1612 ; CHECK-MVE-NEXT: vldr s6, .LCPI25_1
1613 ; CHECK-MVE-NEXT: vmaxnm.f32 s12, s2, s4
1614 ; CHECK-MVE-NEXT: vmaxnm.f32 s10, s0, s4
1615 ; CHECK-MVE-NEXT: vminnm.f32 s12, s12, s6
1616 ; CHECK-MVE-NEXT: vmaxnm.f32 s8, s3, s4
1617 ; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s6
1618 ; CHECK-MVE-NEXT: vmaxnm.f32 s4, s1, s4
1619 ; CHECK-MVE-NEXT: vcvt.s32.f32 s12, s12
1620 ; CHECK-MVE-NEXT: vminnm.f32 s8, s8, s6
1621 ; CHECK-MVE-NEXT: vminnm.f32 s4, s4, s6
1622 ; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s10
1623 ; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s8
1624 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1625 ; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s4
1626 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
1627 ; CHECK-MVE-NEXT: vmov r0, s12
1628 ; CHECK-MVE-NEXT: it vs
1629 ; CHECK-MVE-NEXT: movvs r0, #0
1630 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1631 ; CHECK-MVE-NEXT: vmov r1, s10
1632 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
1633 ; CHECK-MVE-NEXT: it vs
1634 ; CHECK-MVE-NEXT: movvs r1, #0
1635 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1636 ; CHECK-MVE-NEXT: vmov r2, s8
1637 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
1638 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
1639 ; CHECK-MVE-NEXT: vmov r3, s4
1640 ; CHECK-MVE-NEXT: it vs
1641 ; CHECK-MVE-NEXT: movvs r2, #0
1642 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1643 ; CHECK-MVE-NEXT: it vs
1644 ; CHECK-MVE-NEXT: movvs r3, #0
1645 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r3, r2
1646 ; CHECK-MVE-NEXT: bx lr
1647 ; CHECK-MVE-NEXT: .p2align 2
1648 ; CHECK-MVE-NEXT: @ %bb.1:
1649 ; CHECK-MVE-NEXT: .LCPI25_0:
1650 ; CHECK-MVE-NEXT: .long 0xc7000000 @ float -32768
1651 ; CHECK-MVE-NEXT: .LCPI25_1:
1652 ; CHECK-MVE-NEXT: .long 0x46fffe00 @ float 32767
1653 ;
1654 ; CHECK-MVEFP-LABEL: test_signed_v4f32_v4i16:
1655 ; CHECK-MVEFP: @ %bb.0:
1656 ; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
1657 ; CHECK-MVEFP-NEXT: vqmovnb.s32 q0, q0
1658 ; CHECK-MVEFP-NEXT: vmovlb.s16 q0, q0
1659 ; CHECK-MVEFP-NEXT: bx lr
1660 %x = call <4 x i16> @llvm.fptosi.sat.v4f32.v4i16(<4 x float> %f)
1661 ret <4 x i16> %x
1662 }
1664 define arm_aapcs_vfpcc <4 x i19> @test_signed_v4f32_v4i19(<4 x float> %f) {
1665 ; CHECK-MVE-LABEL: test_signed_v4f32_v4i19:
1666 ; CHECK-MVE: @ %bb.0:
1667 ; CHECK-MVE-NEXT: vldr s4, .LCPI26_0
1668 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
1669 ; CHECK-MVE-NEXT: vldr s6, .LCPI26_1
1670 ; CHECK-MVE-NEXT: vmaxnm.f32 s12, s2, s4
1671 ; CHECK-MVE-NEXT: vmaxnm.f32 s10, s0, s4
1672 ; CHECK-MVE-NEXT: vminnm.f32 s12, s12, s6
1673 ; CHECK-MVE-NEXT: vmaxnm.f32 s8, s3, s4
1674 ; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s6
1675 ; CHECK-MVE-NEXT: vmaxnm.f32 s4, s1, s4
1676 ; CHECK-MVE-NEXT: vcvt.s32.f32 s12, s12
1677 ; CHECK-MVE-NEXT: vminnm.f32 s8, s8, s6
1678 ; CHECK-MVE-NEXT: vminnm.f32 s4, s4, s6
1679 ; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s10
1680 ; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s8
1681 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1682 ; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s4
1683 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
1684 ; CHECK-MVE-NEXT: vmov r0, s12
1685 ; CHECK-MVE-NEXT: it vs
1686 ; CHECK-MVE-NEXT: movvs r0, #0
1687 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1688 ; CHECK-MVE-NEXT: vmov r1, s10
1689 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
1690 ; CHECK-MVE-NEXT: it vs
1691 ; CHECK-MVE-NEXT: movvs r1, #0
1692 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1693 ; CHECK-MVE-NEXT: vmov r2, s8
1694 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
1695 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
1696 ; CHECK-MVE-NEXT: vmov r3, s4
1697 ; CHECK-MVE-NEXT: it vs
1698 ; CHECK-MVE-NEXT: movvs r2, #0
1699 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1700 ; CHECK-MVE-NEXT: it vs
1701 ; CHECK-MVE-NEXT: movvs r3, #0
1702 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r3, r2
1703 ; CHECK-MVE-NEXT: bx lr
1704 ; CHECK-MVE-NEXT: .p2align 2
1705 ; CHECK-MVE-NEXT: @ %bb.1:
1706 ; CHECK-MVE-NEXT: .LCPI26_0:
1707 ; CHECK-MVE-NEXT: .long 0xc8800000 @ float -262144
1708 ; CHECK-MVE-NEXT: .LCPI26_1:
1709 ; CHECK-MVE-NEXT: .long 0x487fffc0 @ float 262143
1710 ;
1711 ; CHECK-MVEFP-LABEL: test_signed_v4f32_v4i19:
1712 ; CHECK-MVEFP: @ %bb.0:
1713 ; CHECK-MVEFP-NEXT: movs r0, #0
1714 ; CHECK-MVEFP-NEXT: vmov.i32 q1, #0x3ffff
1715 ; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
1716 ; CHECK-MVEFP-NEXT: movt r0, #65532
1717 ; CHECK-MVEFP-NEXT: vmin.s32 q0, q0, q1
1718 ; CHECK-MVEFP-NEXT: vdup.32 q1, r0
1719 ; CHECK-MVEFP-NEXT: vmax.s32 q0, q0, q1
1720 ; CHECK-MVEFP-NEXT: bx lr
1721 %x = call <4 x i19> @llvm.fptosi.sat.v4f32.v4i19(<4 x float> %f)
1722 ret <4 x i19> %x
1723 }
1725 define arm_aapcs_vfpcc <4 x i32> @test_signed_v4f32_v4i32_duplicate(<4 x float> %f) {
1726 ; CHECK-MVE-LABEL: test_signed_v4f32_v4i32_duplicate:
1727 ; CHECK-MVE: @ %bb.0:
1728 ; CHECK-MVE-NEXT: vcvt.s32.f32 s2, s2
1729 ; CHECK-MVE-NEXT: vcvt.s32.f32 s0, s0
1730 ; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s3
1731 ; CHECK-MVE-NEXT: vcvt.s32.f32 s6, s1
1732 ; CHECK-MVE-NEXT: vmov r0, s2
1733 ; CHECK-MVE-NEXT: vmov r1, s0
1734 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
1735 ; CHECK-MVE-NEXT: vmov r0, s4
1736 ; CHECK-MVE-NEXT: vmov r1, s6
1737 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r1, r0
1738 ; CHECK-MVE-NEXT: bx lr
1739 ;
1740 ; CHECK-MVEFP-LABEL: test_signed_v4f32_v4i32_duplicate:
1741 ; CHECK-MVEFP: @ %bb.0:
1742 ; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
1743 ; CHECK-MVEFP-NEXT: bx lr
1744 %x = call <4 x i32> @llvm.fptosi.sat.v4f32.v4i32(<4 x float> %f)
1745 ret <4 x i32> %x
1746 }
1748 define arm_aapcs_vfpcc <4 x i50> @test_signed_v4f32_v4i50(<4 x float> %f) {
1749 ; CHECK-LABEL: test_signed_v4f32_v4i50:
1750 ; CHECK: @ %bb.0:
1751 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
1752 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r11, lr}
1753 ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
1754 ; CHECK-NEXT: vpush {d8, d9, d10, d11}
1755 ; CHECK-NEXT: vmov q4, q0
1756 ; CHECK-NEXT: mov r8, r0
1757 ; CHECK-NEXT: vmov r0, s17
1758 ; CHECK-NEXT: bl __aeabi_f2lz
1759 ; CHECK-NEXT: mov r9, r0
1760 ; CHECK-NEXT: vmov r0, s18
1761 ; CHECK-NEXT: vldr s22, .LCPI28_0
1762 ; CHECK-NEXT: mov r11, r1
1763 ; CHECK-NEXT: vldr s20, .LCPI28_1
1764 ; CHECK-NEXT: vcmp.f32 s17, s22
1765 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1766 ; CHECK-NEXT: itt lt
1767 ; CHECK-NEXT: movwlt r11, #0
1768 ; CHECK-NEXT: movtlt r11, #65534
1769 ; CHECK-NEXT: it lt
1770 ; CHECK-NEXT: movlt.w r9, #0
1771 ; CHECK-NEXT: vcmp.f32 s17, s20
1772 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1773 ; CHECK-NEXT: it gt
1774 ; CHECK-NEXT: movgt.w r9, #-1
1775 ; CHECK-NEXT: vcmp.f32 s17, s17
1776 ; CHECK-NEXT: itt gt
1777 ; CHECK-NEXT: movwgt r11, #65535
1778 ; CHECK-NEXT: movtgt r11, #1
1779 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1780 ; CHECK-NEXT: itt vs
1781 ; CHECK-NEXT: movvs.w r9, #0
1782 ; CHECK-NEXT: movvs.w r11, #0
1783 ; CHECK-NEXT: bl __aeabi_f2lz
1784 ; CHECK-NEXT: mov r6, r0
1785 ; CHECK-NEXT: vmov r0, s19
1786 ; CHECK-NEXT: vcmp.f32 s18, s22
1787 ; CHECK-NEXT: mov r5, r1
1788 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1789 ; CHECK-NEXT: itt lt
1790 ; CHECK-NEXT: movlt r5, #0
1791 ; CHECK-NEXT: movtlt r5, #65534
1792 ; CHECK-NEXT: vcmp.f32 s18, s20
1793 ; CHECK-NEXT: it lt
1794 ; CHECK-NEXT: movlt r6, #0
1795 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1796 ; CHECK-NEXT: itt gt
1797 ; CHECK-NEXT: movwgt r5, #65535
1798 ; CHECK-NEXT: movtgt r5, #1
1799 ; CHECK-NEXT: it gt
1800 ; CHECK-NEXT: movgt.w r6, #-1
1801 ; CHECK-NEXT: vcmp.f32 s18, s18
1802 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1803 ; CHECK-NEXT: itt vs
1804 ; CHECK-NEXT: movvs r6, #0
1805 ; CHECK-NEXT: movvs r5, #0
1806 ; CHECK-NEXT: bl __aeabi_f2lz
1807 ; CHECK-NEXT: mov r4, r0
1808 ; CHECK-NEXT: vmov r0, s16
1809 ; CHECK-NEXT: vcmp.f32 s19, s22
1810 ; CHECK-NEXT: mov r7, r1
1811 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1812 ; CHECK-NEXT: itt lt
1813 ; CHECK-NEXT: movlt r7, #0
1814 ; CHECK-NEXT: movtlt r7, #65534
1815 ; CHECK-NEXT: vcmp.f32 s19, s20
1816 ; CHECK-NEXT: it lt
1817 ; CHECK-NEXT: movlt r4, #0
1818 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1819 ; CHECK-NEXT: itt gt
1820 ; CHECK-NEXT: movwgt r7, #65535
1821 ; CHECK-NEXT: movtgt r7, #1
1822 ; CHECK-NEXT: it gt
1823 ; CHECK-NEXT: movgt.w r4, #-1
1824 ; CHECK-NEXT: vcmp.f32 s19, s19
1825 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1826 ; CHECK-NEXT: itt vs
1827 ; CHECK-NEXT: movvs r4, #0
1828 ; CHECK-NEXT: movvs r7, #0
1829 ; CHECK-NEXT: bl __aeabi_f2lz
1830 ; CHECK-NEXT: vcmp.f32 s16, s22
1831 ; CHECK-NEXT: bfc r5, #18, #14
1832 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1833 ; CHECK-NEXT: ittt lt
1834 ; CHECK-NEXT: movlt r0, #0
1835 ; CHECK-NEXT: movlt r1, #0
1836 ; CHECK-NEXT: movtlt r1, #65534
1837 ; CHECK-NEXT: vcmp.f32 s16, s20
1838 ; CHECK-NEXT: mov r2, r6
1839 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1840 ; CHECK-NEXT: ittt gt
1841 ; CHECK-NEXT: movwgt r1, #65535
1842 ; CHECK-NEXT: movtgt r1, #1
1843 ; CHECK-NEXT: movgt.w r0, #-1
1844 ; CHECK-NEXT: vcmp.f32 s16, s16
1845 ; CHECK-NEXT: lsrl r2, r5, #28
1846 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1847 ; CHECK-NEXT: it vs
1848 ; CHECK-NEXT: movvs r0, #0
1849 ; CHECK-NEXT: str.w r0, [r8]
1850 ; CHECK-NEXT: lsr.w r0, r7, #10
1851 ; CHECK-NEXT: bfc r7, #18, #14
1852 ; CHECK-NEXT: bfc r11, #18, #14
1853 ; CHECK-NEXT: lsll r4, r7, #22
1854 ; CHECK-NEXT: orr.w r3, r5, r7
1855 ; CHECK-NEXT: str.w r3, [r8, #20]
1856 ; CHECK-NEXT: orr.w r2, r2, r4
1857 ; CHECK-NEXT: str.w r2, [r8, #16]
1858 ; CHECK-NEXT: strb.w r0, [r8, #24]
1859 ; CHECK-NEXT: mov r0, r9
1860 ; CHECK-NEXT: lsrl r0, r11, #14
1861 ; CHECK-NEXT: orr.w r2, r11, r6, lsl #4
1862 ; CHECK-NEXT: strd r0, r2, [r8, #8]
1863 ; CHECK-NEXT: it vs
1864 ; CHECK-NEXT: movvs r1, #0
1865 ; CHECK-NEXT: bfc r1, #18, #14
1866 ; CHECK-NEXT: orr.w r0, r1, r9, lsl #18
1867 ; CHECK-NEXT: str.w r0, [r8, #4]
1868 ; CHECK-NEXT: vpop {d8, d9, d10, d11}
1869 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r11, pc}
1870 ; CHECK-NEXT: .p2align 2
1871 ; CHECK-NEXT: @ %bb.1:
1872 ; CHECK-NEXT: .LCPI28_0:
1873 ; CHECK-NEXT: .long 0xd8000000 @ float -5.62949953E+14
1874 ; CHECK-NEXT: .LCPI28_1:
1875 ; CHECK-NEXT: .long 0x57ffffff @ float 5.6294992E+14
1876 %x = call <4 x i50> @llvm.fptosi.sat.v4f32.v4i50(<4 x float> %f)
1877 ret <4 x i50> %x
1878 }
1880 define arm_aapcs_vfpcc <4 x i64> @test_signed_v4f32_v4i64(<4 x float> %f) {
1881 ; CHECK-LABEL: test_signed_v4f32_v4i64:
1882 ; CHECK: @ %bb.0:
1883 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
1884 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
1885 ; CHECK-NEXT: .pad #4
1886 ; CHECK-NEXT: sub sp, #4
1887 ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
1888 ; CHECK-NEXT: vpush {d8, d9, d10, d11}
1889 ; CHECK-NEXT: vmov q4, q0
1890 ; CHECK-NEXT: vmov r0, s19
1891 ; CHECK-NEXT: bl __aeabi_f2lz
1892 ; CHECK-NEXT: mov r11, r0
1893 ; CHECK-NEXT: vmov r0, s18
1894 ; CHECK-NEXT: vldr s22, .LCPI29_0
1895 ; CHECK-NEXT: mov r10, r1
1896 ; CHECK-NEXT: vldr s20, .LCPI29_1
1897 ; CHECK-NEXT: vmov r9, s17
1898 ; CHECK-NEXT: vcmp.f32 s19, s22
1899 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1900 ; CHECK-NEXT: itt lt
1901 ; CHECK-NEXT: movlt.w r10, #-2147483648
1902 ; CHECK-NEXT: movlt.w r11, #0
1903 ; CHECK-NEXT: vcmp.f32 s19, s20
1904 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1905 ; CHECK-NEXT: itt gt
1906 ; CHECK-NEXT: movgt.w r11, #-1
1907 ; CHECK-NEXT: mvngt r10, #-2147483648
1908 ; CHECK-NEXT: vcmp.f32 s19, s19
1909 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1910 ; CHECK-NEXT: vmov r8, s16
1911 ; CHECK-NEXT: itt vs
1912 ; CHECK-NEXT: movvs.w r10, #0
1913 ; CHECK-NEXT: movvs.w r11, #0
1914 ; CHECK-NEXT: bl __aeabi_f2lz
1915 ; CHECK-NEXT: mov r7, r0
1916 ; CHECK-NEXT: vcmp.f32 s18, s22
1917 ; CHECK-NEXT: mov r6, r1
1918 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1919 ; CHECK-NEXT: itt lt
1920 ; CHECK-NEXT: movlt r7, #0
1921 ; CHECK-NEXT: movlt.w r6, #-2147483648
1922 ; CHECK-NEXT: vcmp.f32 s18, s20
1923 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1924 ; CHECK-NEXT: mov r0, r9
1925 ; CHECK-NEXT: itt gt
1926 ; CHECK-NEXT: mvngt r6, #-2147483648
1927 ; CHECK-NEXT: movgt.w r7, #-1
1928 ; CHECK-NEXT: vcmp.f32 s18, s18
1929 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1930 ; CHECK-NEXT: itt vs
1931 ; CHECK-NEXT: movvs r7, #0
1932 ; CHECK-NEXT: movvs r6, #0
1933 ; CHECK-NEXT: bl __aeabi_f2lz
1934 ; CHECK-NEXT: mov r5, r0
1935 ; CHECK-NEXT: vcmp.f32 s17, s22
1936 ; CHECK-NEXT: mov r4, r1
1937 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1938 ; CHECK-NEXT: itt lt
1939 ; CHECK-NEXT: movlt.w r4, #-2147483648
1940 ; CHECK-NEXT: movlt r5, #0
1941 ; CHECK-NEXT: vcmp.f32 s17, s20
1942 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1943 ; CHECK-NEXT: mov r0, r8
1944 ; CHECK-NEXT: itt gt
1945 ; CHECK-NEXT: movgt.w r5, #-1
1946 ; CHECK-NEXT: mvngt r4, #-2147483648
1947 ; CHECK-NEXT: vcmp.f32 s17, s17
1948 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1949 ; CHECK-NEXT: itt vs
1950 ; CHECK-NEXT: movvs r4, #0
1951 ; CHECK-NEXT: movvs r5, #0
1952 ; CHECK-NEXT: bl __aeabi_f2lz
1953 ; CHECK-NEXT: vcmp.f32 s16, s22
1954 ; CHECK-NEXT: vmov q1[2], q1[0], r7, r11
1955 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1956 ; CHECK-NEXT: itt lt
1957 ; CHECK-NEXT: movlt r0, #0
1958 ; CHECK-NEXT: movlt.w r1, #-2147483648
1959 ; CHECK-NEXT: vcmp.f32 s16, s20
1960 ; CHECK-NEXT: vmov q1[3], q1[1], r6, r10
1961 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1962 ; CHECK-NEXT: itt gt
1963 ; CHECK-NEXT: mvngt r1, #-2147483648
1964 ; CHECK-NEXT: movgt.w r0, #-1
1965 ; CHECK-NEXT: vcmp.f32 s16, s16
1966 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
1967 ; CHECK-NEXT: itt vs
1968 ; CHECK-NEXT: movvs r0, #0
1969 ; CHECK-NEXT: movvs r1, #0
1970 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
1971 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r4
1972 ; CHECK-NEXT: vpop {d8, d9, d10, d11}
1973 ; CHECK-NEXT: add sp, #4
1974 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
1975 ; CHECK-NEXT: .p2align 2
1976 ; CHECK-NEXT: @ %bb.1:
1977 ; CHECK-NEXT: .LCPI29_0:
1978 ; CHECK-NEXT: .long 0xdf000000 @ float -9.22337203E+18
1979 ; CHECK-NEXT: .LCPI29_1:
1980 ; CHECK-NEXT: .long 0x5effffff @ float 9.22337149E+18
1981 %x = call <4 x i64> @llvm.fptosi.sat.v4f32.v4i64(<4 x float> %f)
1982 ret <4 x i64> %x
1983 }
1985 define arm_aapcs_vfpcc <4 x i100> @test_signed_v4f32_v4i100(<4 x float> %f) {
1986 ; CHECK-LABEL: test_signed_v4f32_v4i100:
1987 ; CHECK: @ %bb.0:
1988 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
1989 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
1990 ; CHECK-NEXT: .pad #4
1991 ; CHECK-NEXT: sub sp, #4
1992 ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
1993 ; CHECK-NEXT: vpush {d8, d9, d10, d11}
1994 ; CHECK-NEXT: .pad #8
1995 ; CHECK-NEXT: sub sp, #8
1996 ; CHECK-NEXT: vmov q4, q0
1997 ; CHECK-NEXT: mov r4, r0
1998 ; CHECK-NEXT: vmov r0, s18
1999 ; CHECK-NEXT: bl __fixsfti
2000 ; CHECK-NEXT: vmov r6, s17
2001 ; CHECK-NEXT: vldr s22, .LCPI30_0
2002 ; CHECK-NEXT: vldr s20, .LCPI30_1
2003 ; CHECK-NEXT: vmov r7, s19
2004 ; CHECK-NEXT: vcmp.f32 s18, s22
2005 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
2006 ; CHECK-NEXT: itttt lt
2007 ; CHECK-NEXT: movlt r2, #0
2008 ; CHECK-NEXT: movlt r1, #0
2009 ; CHECK-NEXT: movlt r0, #0
2010 ; CHECK-NEXT: mvnlt r3, #7
2011 ; CHECK-NEXT: vcmp.f32 s18, s20
2012 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
2013 ; CHECK-NEXT: itttt gt
2014 ; CHECK-NEXT: movgt r3, #7
2015 ; CHECK-NEXT: movgt.w r0, #-1
2016 ; CHECK-NEXT: movgt.w r1, #-1
2017 ; CHECK-NEXT: movgt.w r2, #-1
2018 ; CHECK-NEXT: vcmp.f32 s18, s18
2019 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
2020 ; CHECK-NEXT: it vs
2021 ; CHECK-NEXT: movvs r2, #0
2022 ; CHECK-NEXT: str.w r2, [r4, #33]
2023 ; CHECK-NEXT: it vs
2024 ; CHECK-NEXT: movvs r1, #0
2025 ; CHECK-NEXT: str.w r1, [r4, #29]
2026 ; CHECK-NEXT: it vs
2027 ; CHECK-NEXT: movvs r0, #0
2028 ; CHECK-NEXT: str.w r0, [r4, #25]
2029 ; CHECK-NEXT: it vs
2030 ; CHECK-NEXT: movvs r3, #0
2031 ; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill
2032 ; CHECK-NEXT: mov r0, r6
2033 ; CHECK-NEXT: bl __fixsfti
2034 ; CHECK-NEXT: mov r10, r0
2035 ; CHECK-NEXT: vcmp.f32 s17, s22
2036 ; CHECK-NEXT: mov r5, r1
2037 ; CHECK-NEXT: mov r6, r2
2038 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
2039 ; CHECK-NEXT: itttt lt
2040 ; CHECK-NEXT: mvnlt r3, #7
2041 ; CHECK-NEXT: movlt r6, #0
2042 ; CHECK-NEXT: movlt.w r10, #0
2043 ; CHECK-NEXT: movlt r5, #0
2044 ; CHECK-NEXT: vcmp.f32 s17, s20
2045 ; CHECK-NEXT: mov r0, r7
2046 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
2047 ; CHECK-NEXT: itttt gt
2048 ; CHECK-NEXT: movgt.w r5, #-1
2049 ; CHECK-NEXT: movgt.w r10, #-1
2050 ; CHECK-NEXT: movgt.w r6, #-1
2051 ; CHECK-NEXT: movgt r3, #7
2052 ; CHECK-NEXT: vcmp.f32 s17, s17
2053 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
2054 ; CHECK-NEXT: it vs
2055 ; CHECK-NEXT: movvs r3, #0
2056 ; CHECK-NEXT: str r3, [sp] @ 4-byte Spill
2057 ; CHECK-NEXT: ittt vs
2058 ; CHECK-NEXT: movvs r6, #0
2059 ; CHECK-NEXT: movvs.w r10, #0
2060 ; CHECK-NEXT: movvs r5, #0
2061 ; CHECK-NEXT: bl __fixsfti
2062 ; CHECK-NEXT: mov r7, r0
2063 ; CHECK-NEXT: vmov r0, s16
2064 ; CHECK-NEXT: vcmp.f32 s19, s22
2065 ; CHECK-NEXT: mov r11, r1
2066 ; CHECK-NEXT: mov r8, r2
2067 ; CHECK-NEXT: mov r9, r3
2068 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
2069 ; CHECK-NEXT: itttt lt
2070 ; CHECK-NEXT: mvnlt r9, #7
2071 ; CHECK-NEXT: movlt.w r8, #0
2072 ; CHECK-NEXT: movlt.w r11, #0
2073 ; CHECK-NEXT: movlt r7, #0
2074 ; CHECK-NEXT: vcmp.f32 s19, s20
2075 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
2076 ; CHECK-NEXT: itttt gt
2077 ; CHECK-NEXT: movgt.w r7, #-1
2078 ; CHECK-NEXT: movgt.w r11, #-1
2079 ; CHECK-NEXT: movgt.w r8, #-1
2080 ; CHECK-NEXT: movgt.w r9, #7
2081 ; CHECK-NEXT: vcmp.f32 s19, s19
2082 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
2083 ; CHECK-NEXT: itttt vs
2084 ; CHECK-NEXT: movvs.w r9, #0
2085 ; CHECK-NEXT: movvs.w r8, #0
2086 ; CHECK-NEXT: movvs.w r11, #0
2087 ; CHECK-NEXT: movvs r7, #0
2088 ; CHECK-NEXT: bl __fixsfti
2089 ; CHECK-NEXT: vcmp.f32 s16, s22
2090 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
2091 ; CHECK-NEXT: itttt lt
2092 ; CHECK-NEXT: movlt r2, #0
2093 ; CHECK-NEXT: movlt r1, #0
2094 ; CHECK-NEXT: movlt r0, #0
2095 ; CHECK-NEXT: mvnlt r3, #7
2096 ; CHECK-NEXT: vcmp.f32 s16, s20
2097 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
2098 ; CHECK-NEXT: itttt gt
2099 ; CHECK-NEXT: movgt r3, #7
2100 ; CHECK-NEXT: movgt.w r0, #-1
2101 ; CHECK-NEXT: movgt.w r1, #-1
2102 ; CHECK-NEXT: movgt.w r2, #-1
2103 ; CHECK-NEXT: vcmp.f32 s16, s16
2104 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
2105 ; CHECK-NEXT: it vs
2106 ; CHECK-NEXT: movvs r2, #0
2107 ; CHECK-NEXT: str r2, [r4, #8]
2108 ; CHECK-NEXT: it vs
2109 ; CHECK-NEXT: movvs r1, #0
2110 ; CHECK-NEXT: str r1, [r4, #4]
2111 ; CHECK-NEXT: it vs
2112 ; CHECK-NEXT: movvs r0, #0
2113 ; CHECK-NEXT: str r0, [r4]
2114 ; CHECK-NEXT: mov r0, r7
2115 ; CHECK-NEXT: lsrl r0, r11, #28
2116 ; CHECK-NEXT: and r1, r9, #15
2117 ; CHECK-NEXT: str.w r0, [r4, #41]
2118 ; CHECK-NEXT: mov r0, r10
2119 ; CHECK-NEXT: lsrl r0, r5, #28
2120 ; CHECK-NEXT: str r0, [r4, #16]
2121 ; CHECK-NEXT: orr.w r0, r11, r8, lsl #4
2122 ; CHECK-NEXT: lsrl r8, r1, #28
2123 ; CHECK-NEXT: str.w r0, [r4, #45]
2124 ; CHECK-NEXT: strb.w r8, [r4, #49]
2125 ; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
2126 ; CHECK-NEXT: and r0, r0, #15
2127 ; CHECK-NEXT: orr.w r0, r0, r7, lsl #4
2128 ; CHECK-NEXT: str.w r0, [r4, #37]
2129 ; CHECK-NEXT: orr.w r0, r5, r6, lsl #4
2130 ; CHECK-NEXT: str r0, [r4, #20]
2131 ; CHECK-NEXT: ldr r0, [sp] @ 4-byte Reload
2132 ; CHECK-NEXT: and r1, r0, #15
2133 ; CHECK-NEXT: lsrl r6, r1, #28
2134 ; CHECK-NEXT: strb r6, [r4, #24]
2135 ; CHECK-NEXT: it vs
2136 ; CHECK-NEXT: movvs r3, #0
2137 ; CHECK-NEXT: and r0, r3, #15
2138 ; CHECK-NEXT: orr.w r0, r0, r10, lsl #4
2139 ; CHECK-NEXT: str r0, [r4, #12]
2140 ; CHECK-NEXT: add sp, #8
2141 ; CHECK-NEXT: vpop {d8, d9, d10, d11}
2142 ; CHECK-NEXT: add sp, #4
2143 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
2144 ; CHECK-NEXT: .p2align 2
2145 ; CHECK-NEXT: @ %bb.1:
2146 ; CHECK-NEXT: .LCPI30_0:
2147 ; CHECK-NEXT: .long 0xf1000000 @ float -6.338253E+29
2148 ; CHECK-NEXT: .LCPI30_1:
2149 ; CHECK-NEXT: .long 0x70ffffff @ float 6.33825262E+29
2150 %x = call <4 x i100> @llvm.fptosi.sat.v4f32.v4i100(<4 x float> %f)
2151 ret <4 x i100> %x
2152 }
2154 define arm_aapcs_vfpcc <4 x i128> @test_signed_v4f32_v4i128(<4 x float> %f) {
2155 ; CHECK-LABEL: test_signed_v4f32_v4i128:
2156 ; CHECK: @ %bb.0:
2157 ; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
2158 ; CHECK-NEXT: push {r4, r5, r6, r7, lr}
2159 ; CHECK-NEXT: .pad #4
2160 ; CHECK-NEXT: sub sp, #4
2161 ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
2162 ; CHECK-NEXT: vpush {d8, d9, d10, d11}
2163 ; CHECK-NEXT: vmov q4, q0
2164 ; CHECK-NEXT: mov r4, r0
2165 ; CHECK-NEXT: vmov r0, s19
2166 ; CHECK-NEXT: bl __fixsfti
2167 ; CHECK-NEXT: vmov r5, s18
2168 ; CHECK-NEXT: vldr s22, .LCPI31_0
2169 ; CHECK-NEXT: vldr s20, .LCPI31_1
2170 ; CHECK-NEXT: add.w r12, r4, #48
2171 ; CHECK-NEXT: vcmp.f32 s19, s22
2172 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
2173 ; CHECK-NEXT: itttt lt
2174 ; CHECK-NEXT: movlt.w r3, #-2147483648
2175 ; CHECK-NEXT: movlt r2, #0
2176 ; CHECK-NEXT: movlt r1, #0
2177 ; CHECK-NEXT: movlt r0, #0
2178 ; CHECK-NEXT: vcmp.f32 s19, s20
2179 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
2180 ; CHECK-NEXT: itttt gt
2181 ; CHECK-NEXT: movgt.w r0, #-1
2182 ; CHECK-NEXT: movgt.w r1, #-1
2183 ; CHECK-NEXT: movgt.w r2, #-1
2184 ; CHECK-NEXT: mvngt r3, #-2147483648
2185 ; CHECK-NEXT: vcmp.f32 s19, s19
2186 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
2187 ; CHECK-NEXT: it vs
2188 ; CHECK-NEXT: movvs r3, #0
2189 ; CHECK-NEXT: ittt vs
2190 ; CHECK-NEXT: movvs r2, #0
2191 ; CHECK-NEXT: movvs r1, #0
2192 ; CHECK-NEXT: movvs r0, #0
2193 ; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
2194 ; CHECK-NEXT: vmov r7, s16
2195 ; CHECK-NEXT: vmov r6, s17
2196 ; CHECK-NEXT: mov r0, r5
2197 ; CHECK-NEXT: bl __fixsfti
2198 ; CHECK-NEXT: vcmp.f32 s18, s22
2199 ; CHECK-NEXT: add.w r12, r4, #32
2200 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
2201 ; CHECK-NEXT: itttt lt
2202 ; CHECK-NEXT: movlt.w r3, #-2147483648
2203 ; CHECK-NEXT: movlt r2, #0
2204 ; CHECK-NEXT: movlt r1, #0
2205 ; CHECK-NEXT: movlt r0, #0
2206 ; CHECK-NEXT: vcmp.f32 s18, s20
2207 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
2208 ; CHECK-NEXT: itttt gt
2209 ; CHECK-NEXT: movgt.w r0, #-1
2210 ; CHECK-NEXT: movgt.w r1, #-1
2211 ; CHECK-NEXT: movgt.w r2, #-1
2212 ; CHECK-NEXT: mvngt r3, #-2147483648
2213 ; CHECK-NEXT: vcmp.f32 s18, s18
2214 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
2215 ; CHECK-NEXT: itttt vs
2216 ; CHECK-NEXT: movvs r3, #0
2217 ; CHECK-NEXT: movvs r2, #0
2218 ; CHECK-NEXT: movvs r1, #0
2219 ; CHECK-NEXT: movvs r0, #0
2220 ; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
2221 ; CHECK-NEXT: mov r0, r6
2222 ; CHECK-NEXT: bl __fixsfti
2223 ; CHECK-NEXT: vcmp.f32 s17, s22
2224 ; CHECK-NEXT: add.w r12, r4, #16
2225 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
2226 ; CHECK-NEXT: itttt lt
2227 ; CHECK-NEXT: movlt.w r3, #-2147483648
2228 ; CHECK-NEXT: movlt r2, #0
2229 ; CHECK-NEXT: movlt r1, #0
2230 ; CHECK-NEXT: movlt r0, #0
2231 ; CHECK-NEXT: vcmp.f32 s17, s20
2232 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
2233 ; CHECK-NEXT: itttt gt
2234 ; CHECK-NEXT: movgt.w r0, #-1
2235 ; CHECK-NEXT: movgt.w r1, #-1
2236 ; CHECK-NEXT: movgt.w r2, #-1
2237 ; CHECK-NEXT: mvngt r3, #-2147483648
2238 ; CHECK-NEXT: vcmp.f32 s17, s17
2239 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
2240 ; CHECK-NEXT: itttt vs
2241 ; CHECK-NEXT: movvs r3, #0
2242 ; CHECK-NEXT: movvs r2, #0
2243 ; CHECK-NEXT: movvs r1, #0
2244 ; CHECK-NEXT: movvs r0, #0
2245 ; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
2246 ; CHECK-NEXT: mov r0, r7
2247 ; CHECK-NEXT: bl __fixsfti
2248 ; CHECK-NEXT: vcmp.f32 s16, s22
2249 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
2250 ; CHECK-NEXT: itttt lt
2251 ; CHECK-NEXT: movlt.w r3, #-2147483648
2252 ; CHECK-NEXT: movlt r2, #0
2253 ; CHECK-NEXT: movlt r1, #0
2254 ; CHECK-NEXT: movlt r0, #0
2255 ; CHECK-NEXT: vcmp.f32 s16, s20
2256 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
2257 ; CHECK-NEXT: itttt gt
2258 ; CHECK-NEXT: movgt.w r0, #-1
2259 ; CHECK-NEXT: movgt.w r1, #-1
2260 ; CHECK-NEXT: movgt.w r2, #-1
2261 ; CHECK-NEXT: mvngt r3, #-2147483648
2262 ; CHECK-NEXT: vcmp.f32 s16, s16
2263 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
2264 ; CHECK-NEXT: itttt vs
2265 ; CHECK-NEXT: movvs r3, #0
2266 ; CHECK-NEXT: movvs r2, #0
2267 ; CHECK-NEXT: movvs r1, #0
2268 ; CHECK-NEXT: movvs r0, #0
2269 ; CHECK-NEXT: stm r4!, {r0, r1, r2, r3}
2270 ; CHECK-NEXT: vpop {d8, d9, d10, d11}
2271 ; CHECK-NEXT: add sp, #4
2272 ; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
2273 ; CHECK-NEXT: .p2align 2
2274 ; CHECK-NEXT: @ %bb.1:
2275 ; CHECK-NEXT: .LCPI31_0:
2276 ; CHECK-NEXT: .long 0xff000000 @ float -1.70141183E+38
2277 ; CHECK-NEXT: .LCPI31_1:
2278 ; CHECK-NEXT: .long 0x7effffff @ float 1.70141173E+38
2279 %x = call <4 x i128> @llvm.fptosi.sat.v4f32.v4i128(<4 x float> %f)
2280 ret <4 x i128> %x
2281 }
2283 ;
2284 ; 2-Vector double to signed integer -- result size variation
2285 ;
2287 declare <2 x i1> @llvm.fptosi.sat.v2f64.v2i1 (<2 x double>)
2288 declare <2 x i8> @llvm.fptosi.sat.v2f64.v2i8 (<2 x double>)
2289 declare <2 x i13> @llvm.fptosi.sat.v2f64.v2i13 (<2 x double>)
2290 declare <2 x i16> @llvm.fptosi.sat.v2f64.v2i16 (<2 x double>)
2291 declare <2 x i19> @llvm.fptosi.sat.v2f64.v2i19 (<2 x double>)
2292 declare <2 x i50> @llvm.fptosi.sat.v2f64.v2i50 (<2 x double>)
2293 declare <2 x i64> @llvm.fptosi.sat.v2f64.v2i64 (<2 x double>)
2294 declare <2 x i100> @llvm.fptosi.sat.v2f64.v2i100(<2 x double>)
2295 declare <2 x i128> @llvm.fptosi.sat.v2f64.v2i128(<2 x double>)
2297 define arm_aapcs_vfpcc <2 x i1> @test_signed_v2f64_v2i1(<2 x double> %f) {
2298 ; CHECK-LABEL: test_signed_v2f64_v2i1:
2299 ; CHECK: @ %bb.0:
2300 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
2301 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
2302 ; CHECK-NEXT: .pad #4
2303 ; CHECK-NEXT: sub sp, #4
2304 ; CHECK-NEXT: .vsave {d8, d9}
2305 ; CHECK-NEXT: vpush {d8, d9}
2306 ; CHECK-NEXT: .pad #16
2307 ; CHECK-NEXT: sub sp, #16
2308 ; CHECK-NEXT: vmov q4, q0
2309 ; CHECK-NEXT: vldr d0, .LCPI32_0
2310 ; CHECK-NEXT: vmov r8, r7, d8
2311 ; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
2312 ; CHECK-NEXT: vmov r11, r3, d0
2313 ; CHECK-NEXT: str r3, [sp, #8] @ 4-byte Spill
2314 ; CHECK-NEXT: mov r0, r8
2315 ; CHECK-NEXT: mov r1, r7
2316 ; CHECK-NEXT: mov r2, r11
2317 ; CHECK-NEXT: bl __aeabi_dcmpge
2318 ; CHECK-NEXT: mov r10, r0
2319 ; CHECK-NEXT: mov r0, r8
2320 ; CHECK-NEXT: mov r1, r7
2321 ; CHECK-NEXT: bl __aeabi_d2iz
2322 ; CHECK-NEXT: vldr d0, .LCPI32_1
2323 ; CHECK-NEXT: mov r9, r0
2324 ; CHECK-NEXT: mov r0, r8
2325 ; CHECK-NEXT: mov r1, r7
2326 ; CHECK-NEXT: vmov r2, r3, d0
2327 ; CHECK-NEXT: cmp.w r10, #0
2328 ; CHECK-NEXT: vmov r6, r5, d9
2329 ; CHECK-NEXT: str r2, [sp, #4] @ 4-byte Spill
2330 ; CHECK-NEXT: it eq
2331 ; CHECK-NEXT: moveq.w r9, #-1
2332 ; CHECK-NEXT: mov r10, r3
2333 ; CHECK-NEXT: bl __aeabi_dcmpgt
2334 ; CHECK-NEXT: cmp r0, #0
2335 ; CHECK-NEXT: mov r0, r8
2336 ; CHECK-NEXT: mov r1, r7
2337 ; CHECK-NEXT: mov r2, r8
2338 ; CHECK-NEXT: mov r3, r7
2339 ; CHECK-NEXT: it ne
2340 ; CHECK-NEXT: movne.w r9, #0
2341 ; CHECK-NEXT: bl __aeabi_dcmpun
2342 ; CHECK-NEXT: cmp r0, #0
2343 ; CHECK-NEXT: it ne
2344 ; CHECK-NEXT: movne.w r9, #0
2345 ; CHECK-NEXT: and r0, r9, #1
2346 ; CHECK-NEXT: ldr r3, [sp, #8] @ 4-byte Reload
2347 ; CHECK-NEXT: rsbs r0, r0, #0
2348 ; CHECK-NEXT: movs r4, #0
2349 ; CHECK-NEXT: bfi r4, r0, #0, #1
2350 ; CHECK-NEXT: mov r0, r6
2351 ; CHECK-NEXT: mov r1, r5
2352 ; CHECK-NEXT: mov r2, r11
2353 ; CHECK-NEXT: bl __aeabi_dcmpge
2354 ; CHECK-NEXT: mov r8, r0
2355 ; CHECK-NEXT: mov r0, r6
2356 ; CHECK-NEXT: mov r1, r5
2357 ; CHECK-NEXT: bl __aeabi_d2iz
2358 ; CHECK-NEXT: mov r7, r0
2359 ; CHECK-NEXT: cmp.w r8, #0
2360 ; CHECK-NEXT: it eq
2361 ; CHECK-NEXT: moveq.w r7, #-1
2362 ; CHECK-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
2363 ; CHECK-NEXT: mov r0, r6
2364 ; CHECK-NEXT: mov r1, r5
2365 ; CHECK-NEXT: mov r3, r10
2366 ; CHECK-NEXT: bl __aeabi_dcmpgt
2367 ; CHECK-NEXT: cmp r0, #0
2368 ; CHECK-NEXT: mov r0, r6
2369 ; CHECK-NEXT: mov r1, r5
2370 ; CHECK-NEXT: mov r2, r6
2371 ; CHECK-NEXT: mov r3, r5
2372 ; CHECK-NEXT: it ne
2373 ; CHECK-NEXT: movne r7, #0
2374 ; CHECK-NEXT: bl __aeabi_dcmpun
2375 ; CHECK-NEXT: cmp r0, #0
2376 ; CHECK-NEXT: it ne
2377 ; CHECK-NEXT: movne r7, #0
2378 ; CHECK-NEXT: and r0, r7, #1
2379 ; CHECK-NEXT: rsbs r0, r0, #0
2380 ; CHECK-NEXT: bfi r4, r0, #1, #1
2381 ; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
2382 ; CHECK-NEXT: strb r4, [r0]
2383 ; CHECK-NEXT: add sp, #16
2384 ; CHECK-NEXT: vpop {d8, d9}
2385 ; CHECK-NEXT: add sp, #4
2386 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
2387 ; CHECK-NEXT: .p2align 3
2388 ; CHECK-NEXT: @ %bb.1:
2389 ; CHECK-NEXT: .LCPI32_0:
2390 ; CHECK-NEXT: .long 0 @ double -1
2391 ; CHECK-NEXT: .long 3220176896
2392 ; CHECK-NEXT: .LCPI32_1:
2393 ; CHECK-NEXT: .long 0 @ double 0
2394 ; CHECK-NEXT: .long 0
2395 %x = call <2 x i1> @llvm.fptosi.sat.v2f64.v2i1(<2 x double> %f)
2396 ret <2 x i1> %x
2397 }
2399 define arm_aapcs_vfpcc <2 x i8> @test_signed_v2f64_v2i8(<2 x double> %f) {
2400 ; CHECK-LABEL: test_signed_v2f64_v2i8:
2401 ; CHECK: @ %bb.0:
2402 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
2403 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
2404 ; CHECK-NEXT: .pad #4
2405 ; CHECK-NEXT: sub sp, #4
2406 ; CHECK-NEXT: .vsave {d8, d9}
2407 ; CHECK-NEXT: vpush {d8, d9}
2408 ; CHECK-NEXT: .pad #16
2409 ; CHECK-NEXT: sub sp, #16
2410 ; CHECK-NEXT: vmov q4, q0
2411 ; CHECK-NEXT: vldr d0, .LCPI33_0
2412 ; CHECK-NEXT: vmov r9, r8, d9
2413 ; CHECK-NEXT: vmov r7, r3, d0
2414 ; CHECK-NEXT: str r3, [sp, #12] @ 4-byte Spill
2415 ; CHECK-NEXT: mov r0, r9
2416 ; CHECK-NEXT: mov r1, r8
2417 ; CHECK-NEXT: mov r2, r7
2418 ; CHECK-NEXT: bl __aeabi_dcmpge
2419 ; CHECK-NEXT: mov r6, r0
2420 ; CHECK-NEXT: mov r0, r9
2421 ; CHECK-NEXT: mov r1, r8
2422 ; CHECK-NEXT: bl __aeabi_d2lz
2423 ; CHECK-NEXT: vldr d0, .LCPI33_1
2424 ; CHECK-NEXT: mov r5, r0
2425 ; CHECK-NEXT: mov r4, r1
2426 ; CHECK-NEXT: mov r0, r9
2427 ; CHECK-NEXT: vmov r2, r3, d0
2428 ; CHECK-NEXT: mov r1, r8
2429 ; CHECK-NEXT: vmov r11, r10, d8
2430 ; CHECK-NEXT: cmp r6, #0
2431 ; CHECK-NEXT: strd r2, r3, [sp, #4] @ 8-byte Folded Spill
2432 ; CHECK-NEXT: itt eq
2433 ; CHECK-NEXT: moveq.w r4, #-1
2434 ; CHECK-NEXT: mvneq r5, #127
2435 ; CHECK-NEXT: bl __aeabi_dcmpgt
2436 ; CHECK-NEXT: cmp r0, #0
2437 ; CHECK-NEXT: mov r0, r9
2438 ; CHECK-NEXT: mov r1, r8
2439 ; CHECK-NEXT: mov r2, r9
2440 ; CHECK-NEXT: mov r3, r8
2441 ; CHECK-NEXT: itt ne
2442 ; CHECK-NEXT: movne r5, #127
2443 ; CHECK-NEXT: movne r4, #0
2444 ; CHECK-NEXT: bl __aeabi_dcmpun
2445 ; CHECK-NEXT: cmp r0, #0
2446 ; CHECK-NEXT: itt ne
2447 ; CHECK-NEXT: movne r4, #0
2448 ; CHECK-NEXT: movne r5, #0
2449 ; CHECK-NEXT: ldr r3, [sp, #12] @ 4-byte Reload
2450 ; CHECK-NEXT: mov r0, r11
2451 ; CHECK-NEXT: mov r1, r10
2452 ; CHECK-NEXT: mov r2, r7
2453 ; CHECK-NEXT: bl __aeabi_dcmpge
2454 ; CHECK-NEXT: mov r8, r0
2455 ; CHECK-NEXT: mov r0, r11
2456 ; CHECK-NEXT: mov r1, r10
2457 ; CHECK-NEXT: bl __aeabi_d2lz
2458 ; CHECK-NEXT: mov r7, r0
2459 ; CHECK-NEXT: mov r6, r1
2460 ; CHECK-NEXT: cmp.w r8, #0
2461 ; CHECK-NEXT: itt eq
2462 ; CHECK-NEXT: mvneq r7, #127
2463 ; CHECK-NEXT: moveq.w r6, #-1
2464 ; CHECK-NEXT: ldrd r2, r3, [sp, #4] @ 8-byte Folded Reload
2465 ; CHECK-NEXT: mov r0, r11
2466 ; CHECK-NEXT: mov r1, r10
2467 ; CHECK-NEXT: bl __aeabi_dcmpgt
2468 ; CHECK-NEXT: cmp r0, #0
2469 ; CHECK-NEXT: mov r0, r11
2470 ; CHECK-NEXT: mov r1, r10
2471 ; CHECK-NEXT: mov r2, r11
2472 ; CHECK-NEXT: mov r3, r10
2473 ; CHECK-NEXT: itt ne
2474 ; CHECK-NEXT: movne r6, #0
2475 ; CHECK-NEXT: movne r7, #127
2476 ; CHECK-NEXT: bl __aeabi_dcmpun
2477 ; CHECK-NEXT: cmp r0, #0
2478 ; CHECK-NEXT: itt ne
2479 ; CHECK-NEXT: movne r7, #0
2480 ; CHECK-NEXT: movne r6, #0
2481 ; CHECK-NEXT: vmov q0[2], q0[0], r7, r5
2482 ; CHECK-NEXT: vmov q0[3], q0[1], r6, r4
2483 ; CHECK-NEXT: add sp, #16
2484 ; CHECK-NEXT: vpop {d8, d9}
2485 ; CHECK-NEXT: add sp, #4
2486 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
2487 ; CHECK-NEXT: .p2align 3
2488 ; CHECK-NEXT: @ %bb.1:
2489 ; CHECK-NEXT: .LCPI33_0:
2490 ; CHECK-NEXT: .long 0 @ double -128
2491 ; CHECK-NEXT: .long 3227516928
2492 ; CHECK-NEXT: .LCPI33_1:
2493 ; CHECK-NEXT: .long 0 @ double 127
2494 ; CHECK-NEXT: .long 1080016896
2495 %x = call <2 x i8> @llvm.fptosi.sat.v2f64.v2i8(<2 x double> %f)
2496 ret <2 x i8> %x
2497 }
2499 define arm_aapcs_vfpcc <2 x i13> @test_signed_v2f64_v2i13(<2 x double> %f) {
2500 ; CHECK-LABEL: test_signed_v2f64_v2i13:
2501 ; CHECK: @ %bb.0:
2502 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
2503 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
2504 ; CHECK-NEXT: .pad #4
2505 ; CHECK-NEXT: sub sp, #4
2506 ; CHECK-NEXT: .vsave {d8, d9}
2507 ; CHECK-NEXT: vpush {d8, d9}
2508 ; CHECK-NEXT: .pad #16
2509 ; CHECK-NEXT: sub sp, #16
2510 ; CHECK-NEXT: vmov q4, q0
2511 ; CHECK-NEXT: vldr d0, .LCPI34_0
2512 ; CHECK-NEXT: vmov r9, r8, d9
2513 ; CHECK-NEXT: vmov r7, r3, d0
2514 ; CHECK-NEXT: str r3, [sp, #12] @ 4-byte Spill
2515 ; CHECK-NEXT: mov r0, r9
2516 ; CHECK-NEXT: mov r1, r8
2517 ; CHECK-NEXT: mov r2, r7
2518 ; CHECK-NEXT: bl __aeabi_dcmpge
2519 ; CHECK-NEXT: mov r6, r0
2520 ; CHECK-NEXT: mov r0, r9
2521 ; CHECK-NEXT: mov r1, r8
2522 ; CHECK-NEXT: bl __aeabi_d2lz
2523 ; CHECK-NEXT: vldr d0, .LCPI34_1
2524 ; CHECK-NEXT: mov r5, r0
2525 ; CHECK-NEXT: mov r4, r1
2526 ; CHECK-NEXT: mov r0, r9
2527 ; CHECK-NEXT: vmov r2, r3, d0
2528 ; CHECK-NEXT: mov r1, r8
2529 ; CHECK-NEXT: vmov r11, r10, d8
2530 ; CHECK-NEXT: cmp r6, #0
2531 ; CHECK-NEXT: strd r2, r3, [sp, #4] @ 8-byte Folded Spill
2532 ; CHECK-NEXT: ittt eq
2533 ; CHECK-NEXT: movweq r5, #61440
2534 ; CHECK-NEXT: movteq r5, #65535
2535 ; CHECK-NEXT: moveq.w r4, #-1
2536 ; CHECK-NEXT: bl __aeabi_dcmpgt
2537 ; CHECK-NEXT: cmp r0, #0
2538 ; CHECK-NEXT: mov r0, r9
2539 ; CHECK-NEXT: mov r1, r8
2540 ; CHECK-NEXT: mov r2, r9
2541 ; CHECK-NEXT: mov r3, r8
2542 ; CHECK-NEXT: itt ne
2543 ; CHECK-NEXT: movwne r5, #4095
2544 ; CHECK-NEXT: movne r4, #0
2545 ; CHECK-NEXT: bl __aeabi_dcmpun
2546 ; CHECK-NEXT: cmp r0, #0
2547 ; CHECK-NEXT: itt ne
2548 ; CHECK-NEXT: movne r4, #0
2549 ; CHECK-NEXT: movne r5, #0
2550 ; CHECK-NEXT: ldr r3, [sp, #12] @ 4-byte Reload
2551 ; CHECK-NEXT: mov r0, r11
2552 ; CHECK-NEXT: mov r1, r10
2553 ; CHECK-NEXT: mov r2, r7
2554 ; CHECK-NEXT: bl __aeabi_dcmpge
2555 ; CHECK-NEXT: mov r8, r0
2556 ; CHECK-NEXT: mov r0, r11
2557 ; CHECK-NEXT: mov r1, r10
2558 ; CHECK-NEXT: bl __aeabi_d2lz
2559 ; CHECK-NEXT: mov r7, r0
2560 ; CHECK-NEXT: mov r6, r1
2561 ; CHECK-NEXT: cmp.w r8, #0
2562 ; CHECK-NEXT: ittt eq
2563 ; CHECK-NEXT: movweq r7, #61440
2564 ; CHECK-NEXT: movteq r7, #65535
2565 ; CHECK-NEXT: moveq.w r6, #-1
2566 ; CHECK-NEXT: ldrd r2, r3, [sp, #4] @ 8-byte Folded Reload
2567 ; CHECK-NEXT: mov r0, r11
2568 ; CHECK-NEXT: mov r1, r10
2569 ; CHECK-NEXT: bl __aeabi_dcmpgt
2570 ; CHECK-NEXT: cmp r0, #0
2571 ; CHECK-NEXT: mov r0, r11
2572 ; CHECK-NEXT: mov r1, r10
2573 ; CHECK-NEXT: mov r2, r11
2574 ; CHECK-NEXT: mov r3, r10
2575 ; CHECK-NEXT: itt ne
2576 ; CHECK-NEXT: movne r6, #0
2577 ; CHECK-NEXT: movwne r7, #4095
2578 ; CHECK-NEXT: bl __aeabi_dcmpun
2579 ; CHECK-NEXT: cmp r0, #0
2580 ; CHECK-NEXT: itt ne
2581 ; CHECK-NEXT: movne r6, #0
2582 ; CHECK-NEXT: movne r7, #0
2583 ; CHECK-NEXT: vmov q0[2], q0[0], r7, r5
2584 ; CHECK-NEXT: vmov q0[3], q0[1], r6, r4
2585 ; CHECK-NEXT: add sp, #16
2586 ; CHECK-NEXT: vpop {d8, d9}
2587 ; CHECK-NEXT: add sp, #4
2588 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
2589 ; CHECK-NEXT: .p2align 3
2590 ; CHECK-NEXT: @ %bb.1:
2591 ; CHECK-NEXT: .LCPI34_0:
2592 ; CHECK-NEXT: .long 0 @ double -4096
2593 ; CHECK-NEXT: .long 3232759808
2594 ; CHECK-NEXT: .LCPI34_1:
2595 ; CHECK-NEXT: .long 0 @ double 4095
2596 ; CHECK-NEXT: .long 1085275648
2597 %x = call <2 x i13> @llvm.fptosi.sat.v2f64.v2i13(<2 x double> %f)
2598 ret <2 x i13> %x
2599 }
2601 define arm_aapcs_vfpcc <2 x i16> @test_signed_v2f64_v2i16(<2 x double> %f) {
2602 ; CHECK-LABEL: test_signed_v2f64_v2i16:
2603 ; CHECK: @ %bb.0:
2604 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
2605 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
2606 ; CHECK-NEXT: .pad #4
2607 ; CHECK-NEXT: sub sp, #4
2608 ; CHECK-NEXT: .vsave {d8, d9}
2609 ; CHECK-NEXT: vpush {d8, d9}
2610 ; CHECK-NEXT: .pad #16
2611 ; CHECK-NEXT: sub sp, #16
2612 ; CHECK-NEXT: vmov q4, q0
2613 ; CHECK-NEXT: vldr d0, .LCPI35_0
2614 ; CHECK-NEXT: vmov r9, r8, d9
2615 ; CHECK-NEXT: vmov r7, r3, d0
2616 ; CHECK-NEXT: str r3, [sp, #12] @ 4-byte Spill
2617 ; CHECK-NEXT: mov r0, r9
2618 ; CHECK-NEXT: mov r1, r8
2619 ; CHECK-NEXT: mov r2, r7
2620 ; CHECK-NEXT: bl __aeabi_dcmpge
2621 ; CHECK-NEXT: mov r6, r0
2622 ; CHECK-NEXT: mov r0, r9
2623 ; CHECK-NEXT: mov r1, r8
2624 ; CHECK-NEXT: bl __aeabi_d2lz
2625 ; CHECK-NEXT: vldr d0, .LCPI35_1
2626 ; CHECK-NEXT: mov r5, r0
2627 ; CHECK-NEXT: mov r4, r1
2628 ; CHECK-NEXT: mov r0, r9
2629 ; CHECK-NEXT: vmov r2, r3, d0
2630 ; CHECK-NEXT: mov r1, r8
2631 ; CHECK-NEXT: vmov r11, r10, d8
2632 ; CHECK-NEXT: cmp r6, #0
2633 ; CHECK-NEXT: strd r2, r3, [sp, #4] @ 8-byte Folded Spill
2634 ; CHECK-NEXT: ittt eq
2635 ; CHECK-NEXT: movweq r5, #32768
2636 ; CHECK-NEXT: movteq r5, #65535
2637 ; CHECK-NEXT: moveq.w r4, #-1
2638 ; CHECK-NEXT: bl __aeabi_dcmpgt
2639 ; CHECK-NEXT: cmp r0, #0
2640 ; CHECK-NEXT: mov r0, r9
2641 ; CHECK-NEXT: mov r1, r8
2642 ; CHECK-NEXT: mov r2, r9
2643 ; CHECK-NEXT: mov r3, r8
2644 ; CHECK-NEXT: itt ne
2645 ; CHECK-NEXT: movwne r5, #32767
2646 ; CHECK-NEXT: movne r4, #0
2647 ; CHECK-NEXT: bl __aeabi_dcmpun
2648 ; CHECK-NEXT: cmp r0, #0
2649 ; CHECK-NEXT: itt ne
2650 ; CHECK-NEXT: movne r4, #0
2651 ; CHECK-NEXT: movne r5, #0
2652 ; CHECK-NEXT: ldr r3, [sp, #12] @ 4-byte Reload
2653 ; CHECK-NEXT: mov r0, r11
2654 ; CHECK-NEXT: mov r1, r10
2655 ; CHECK-NEXT: mov r2, r7
2656 ; CHECK-NEXT: bl __aeabi_dcmpge
2657 ; CHECK-NEXT: mov r8, r0
2658 ; CHECK-NEXT: mov r0, r11
2659 ; CHECK-NEXT: mov r1, r10
2660 ; CHECK-NEXT: bl __aeabi_d2lz
2661 ; CHECK-NEXT: mov r7, r0
2662 ; CHECK-NEXT: mov r6, r1
2663 ; CHECK-NEXT: cmp.w r8, #0
2664 ; CHECK-NEXT: ittt eq
2665 ; CHECK-NEXT: movweq r7, #32768
2666 ; CHECK-NEXT: movteq r7, #65535
2667 ; CHECK-NEXT: moveq.w r6, #-1
2668 ; CHECK-NEXT: ldrd r2, r3, [sp, #4] @ 8-byte Folded Reload
2669 ; CHECK-NEXT: mov r0, r11
2670 ; CHECK-NEXT: mov r1, r10
2671 ; CHECK-NEXT: bl __aeabi_dcmpgt
2672 ; CHECK-NEXT: cmp r0, #0
2673 ; CHECK-NEXT: mov r0, r11
2674 ; CHECK-NEXT: mov r1, r10
2675 ; CHECK-NEXT: mov r2, r11
2676 ; CHECK-NEXT: mov r3, r10
2677 ; CHECK-NEXT: itt ne
2678 ; CHECK-NEXT: movne r6, #0
2679 ; CHECK-NEXT: movwne r7, #32767
2680 ; CHECK-NEXT: bl __aeabi_dcmpun
2681 ; CHECK-NEXT: cmp r0, #0
2682 ; CHECK-NEXT: itt ne
2683 ; CHECK-NEXT: movne r6, #0
2684 ; CHECK-NEXT: movne r7, #0
2685 ; CHECK-NEXT: vmov q0[2], q0[0], r7, r5
2686 ; CHECK-NEXT: vmov q0[3], q0[1], r6, r4
2687 ; CHECK-NEXT: add sp, #16
2688 ; CHECK-NEXT: vpop {d8, d9}
2689 ; CHECK-NEXT: add sp, #4
2690 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
2691 ; CHECK-NEXT: .p2align 3
2692 ; CHECK-NEXT: @ %bb.1:
2693 ; CHECK-NEXT: .LCPI35_0:
2694 ; CHECK-NEXT: .long 0 @ double -32768
2695 ; CHECK-NEXT: .long 3235905536
2696 ; CHECK-NEXT: .LCPI35_1:
2697 ; CHECK-NEXT: .long 0 @ double 32767
2698 ; CHECK-NEXT: .long 1088421824
2699 %x = call <2 x i16> @llvm.fptosi.sat.v2f64.v2i16(<2 x double> %f)
2700 ret <2 x i16> %x
2701 }
2703 define arm_aapcs_vfpcc <2 x i19> @test_signed_v2f64_v2i19(<2 x double> %f) {
2704 ; CHECK-LABEL: test_signed_v2f64_v2i19:
2705 ; CHECK: @ %bb.0:
2706 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
2707 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
2708 ; CHECK-NEXT: .pad #4
2709 ; CHECK-NEXT: sub sp, #4
2710 ; CHECK-NEXT: .vsave {d8, d9}
2711 ; CHECK-NEXT: vpush {d8, d9}
2712 ; CHECK-NEXT: .pad #24
2713 ; CHECK-NEXT: sub sp, #24
2714 ; CHECK-NEXT: vmov q4, q0
2715 ; CHECK-NEXT: vldr d0, .LCPI36_0
2716 ; CHECK-NEXT: vmov r5, r4, d9
2717 ; CHECK-NEXT: vmov r7, r6, d0
2718 ; CHECK-NEXT: mov r0, r5
2719 ; CHECK-NEXT: mov r1, r4
2720 ; CHECK-NEXT: mov r2, r7
2721 ; CHECK-NEXT: mov r3, r6
2722 ; CHECK-NEXT: strd r5, r4, [sp, #12] @ 8-byte Folded Spill
2723 ; CHECK-NEXT: bl __aeabi_dcmpge
2724 ; CHECK-NEXT: str r0, [sp, #4] @ 4-byte Spill
2725 ; CHECK-NEXT: mov r0, r5
2726 ; CHECK-NEXT: mov r1, r4
2727 ; CHECK-NEXT: bl __aeabi_d2lz
2728 ; CHECK-NEXT: vldr d0, .LCPI36_1
2729 ; CHECK-NEXT: mov r8, r0
2730 ; CHECK-NEXT: vmov r11, r5, d8
2731 ; CHECK-NEXT: mov r9, r1
2732 ; CHECK-NEXT: vmov r10, r0, d0
2733 ; CHECK-NEXT: mov r2, r7
2734 ; CHECK-NEXT: mov r3, r6
2735 ; CHECK-NEXT: str r0, [sp, #20] @ 4-byte Spill
2736 ; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
2737 ; CHECK-NEXT: mov r1, r5
2738 ; CHECK-NEXT: cmp r0, #0
2739 ; CHECK-NEXT: mov r0, r11
2740 ; CHECK-NEXT: ittt eq
2741 ; CHECK-NEXT: movweq r8, #0
2742 ; CHECK-NEXT: movteq r8, #65532
2743 ; CHECK-NEXT: moveq.w r9, #-1
2744 ; CHECK-NEXT: bl __aeabi_dcmpge
2745 ; CHECK-NEXT: mov r4, r0
2746 ; CHECK-NEXT: mov r0, r11
2747 ; CHECK-NEXT: mov r1, r5
2748 ; CHECK-NEXT: str r5, [sp, #8] @ 4-byte Spill
2749 ; CHECK-NEXT: bl __aeabi_d2lz
2750 ; CHECK-NEXT: mov r7, r0
2751 ; CHECK-NEXT: mov r6, r1
2752 ; CHECK-NEXT: cmp r4, #0
2753 ; CHECK-NEXT: ittt eq
2754 ; CHECK-NEXT: moveq r7, #0
2755 ; CHECK-NEXT: movteq r7, #65532
2756 ; CHECK-NEXT: moveq.w r6, #-1
2757 ; CHECK-NEXT: ldr r3, [sp, #20] @ 4-byte Reload
2758 ; CHECK-NEXT: mov r0, r11
2759 ; CHECK-NEXT: mov r1, r5
2760 ; CHECK-NEXT: mov r2, r10
2761 ; CHECK-NEXT: bl __aeabi_dcmpgt
2762 ; CHECK-NEXT: cmp r0, #0
2763 ; CHECK-NEXT: ittt ne
2764 ; CHECK-NEXT: movne r6, #0
2765 ; CHECK-NEXT: movwne r7, #65535
2766 ; CHECK-NEXT: movtne r7, #3
2767 ; CHECK-NEXT: ldr r5, [sp, #12] @ 4-byte Reload
2768 ; CHECK-NEXT: mov r2, r10
2769 ; CHECK-NEXT: ldr r4, [sp, #16] @ 4-byte Reload
2770 ; CHECK-NEXT: ldr r3, [sp, #20] @ 4-byte Reload
2771 ; CHECK-NEXT: mov r0, r5
2772 ; CHECK-NEXT: mov r1, r4
2773 ; CHECK-NEXT: bl __aeabi_dcmpgt
2774 ; CHECK-NEXT: cmp r0, #0
2775 ; CHECK-NEXT: mov r0, r5
2776 ; CHECK-NEXT: mov r1, r4
2777 ; CHECK-NEXT: mov r2, r5
2778 ; CHECK-NEXT: mov r3, r4
2779 ; CHECK-NEXT: ittt ne
2780 ; CHECK-NEXT: movne.w r9, #0
2781 ; CHECK-NEXT: movwne r8, #65535
2782 ; CHECK-NEXT: movtne r8, #3
2783 ; CHECK-NEXT: bl __aeabi_dcmpun
2784 ; CHECK-NEXT: cmp r0, #0
2785 ; CHECK-NEXT: itt ne
2786 ; CHECK-NEXT: movne.w r9, #0
2787 ; CHECK-NEXT: movne.w r8, #0
2788 ; CHECK-NEXT: ldr r1, [sp, #8] @ 4-byte Reload
2789 ; CHECK-NEXT: mov r0, r11
2790 ; CHECK-NEXT: mov r2, r11
2791 ; CHECK-NEXT: mov r3, r1
2792 ; CHECK-NEXT: bl __aeabi_dcmpun
2793 ; CHECK-NEXT: cmp r0, #0
2794 ; CHECK-NEXT: itt ne
2795 ; CHECK-NEXT: movne r6, #0
2796 ; CHECK-NEXT: movne r7, #0
2797 ; CHECK-NEXT: vmov q0[2], q0[0], r7, r8
2798 ; CHECK-NEXT: vmov q0[3], q0[1], r6, r9
2799 ; CHECK-NEXT: add sp, #24
2800 ; CHECK-NEXT: vpop {d8, d9}
2801 ; CHECK-NEXT: add sp, #4
2802 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
2803 ; CHECK-NEXT: .p2align 3
2804 ; CHECK-NEXT: @ %bb.1:
2805 ; CHECK-NEXT: .LCPI36_0:
2806 ; CHECK-NEXT: .long 0 @ double -262144
2807 ; CHECK-NEXT: .long 3239051264
2808 ; CHECK-NEXT: .LCPI36_1:
2809 ; CHECK-NEXT: .long 0 @ double 262143
2810 ; CHECK-NEXT: .long 1091567608
2811 %x = call <2 x i19> @llvm.fptosi.sat.v2f64.v2i19(<2 x double> %f)
2812 ret <2 x i19> %x
2813 }
2815 define arm_aapcs_vfpcc <2 x i32> @test_signed_v2f64_v2i32_duplicate(<2 x double> %f) {
2816 ; CHECK-LABEL: test_signed_v2f64_v2i32_duplicate:
2817 ; CHECK: @ %bb.0:
2818 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
2819 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
2820 ; CHECK-NEXT: .pad #4
2821 ; CHECK-NEXT: sub sp, #4
2822 ; CHECK-NEXT: .vsave {d8, d9}
2823 ; CHECK-NEXT: vpush {d8, d9}
2824 ; CHECK-NEXT: .pad #16
2825 ; CHECK-NEXT: sub sp, #16
2826 ; CHECK-NEXT: vmov q4, q0
2827 ; CHECK-NEXT: vldr d0, .LCPI37_0
2828 ; CHECK-NEXT: vmov r9, r8, d9
2829 ; CHECK-NEXT: vmov r7, r3, d0
2830 ; CHECK-NEXT: str r3, [sp, #12] @ 4-byte Spill
2831 ; CHECK-NEXT: mov r0, r9
2832 ; CHECK-NEXT: mov r1, r8
2833 ; CHECK-NEXT: mov r2, r7
2834 ; CHECK-NEXT: bl __aeabi_dcmpge
2835 ; CHECK-NEXT: mov r6, r0
2836 ; CHECK-NEXT: mov r0, r9
2837 ; CHECK-NEXT: mov r1, r8
2838 ; CHECK-NEXT: bl __aeabi_d2lz
2839 ; CHECK-NEXT: vldr d0, .LCPI37_1
2840 ; CHECK-NEXT: mov r5, r0
2841 ; CHECK-NEXT: mov r4, r1
2842 ; CHECK-NEXT: mov r0, r9
2843 ; CHECK-NEXT: vmov r2, r3, d0
2844 ; CHECK-NEXT: mov r1, r8
2845 ; CHECK-NEXT: vmov r11, r10, d8
2846 ; CHECK-NEXT: cmp r6, #0
2847 ; CHECK-NEXT: strd r2, r3, [sp, #4] @ 8-byte Folded Spill
2848 ; CHECK-NEXT: itt eq
2849 ; CHECK-NEXT: moveq.w r4, #-1
2850 ; CHECK-NEXT: moveq.w r5, #-2147483648
2851 ; CHECK-NEXT: bl __aeabi_dcmpgt
2852 ; CHECK-NEXT: cmp r0, #0
2853 ; CHECK-NEXT: mov r0, r9
2854 ; CHECK-NEXT: mov r1, r8
2855 ; CHECK-NEXT: mov r2, r9
2856 ; CHECK-NEXT: mov r3, r8
2857 ; CHECK-NEXT: itt ne
2858 ; CHECK-NEXT: mvnne r5, #-2147483648
2859 ; CHECK-NEXT: movne r4, #0
2860 ; CHECK-NEXT: bl __aeabi_dcmpun
2861 ; CHECK-NEXT: cmp r0, #0
2862 ; CHECK-NEXT: itt ne
2863 ; CHECK-NEXT: movne r4, #0
2864 ; CHECK-NEXT: movne r5, #0
2865 ; CHECK-NEXT: ldr r3, [sp, #12] @ 4-byte Reload
2866 ; CHECK-NEXT: mov r0, r11
2867 ; CHECK-NEXT: mov r1, r10
2868 ; CHECK-NEXT: mov r2, r7
2869 ; CHECK-NEXT: bl __aeabi_dcmpge
2870 ; CHECK-NEXT: mov r8, r0
2871 ; CHECK-NEXT: mov r0, r11
2872 ; CHECK-NEXT: mov r1, r10
2873 ; CHECK-NEXT: bl __aeabi_d2lz
2874 ; CHECK-NEXT: mov r7, r0
2875 ; CHECK-NEXT: mov r6, r1
2876 ; CHECK-NEXT: cmp.w r8, #0
2877 ; CHECK-NEXT: itt eq
2878 ; CHECK-NEXT: moveq.w r7, #-2147483648
2879 ; CHECK-NEXT: moveq.w r6, #-1
2880 ; CHECK-NEXT: ldrd r2, r3, [sp, #4] @ 8-byte Folded Reload
2881 ; CHECK-NEXT: mov r0, r11
2882 ; CHECK-NEXT: mov r1, r10
2883 ; CHECK-NEXT: bl __aeabi_dcmpgt
2884 ; CHECK-NEXT: cmp r0, #0
2885 ; CHECK-NEXT: mov r0, r11
2886 ; CHECK-NEXT: mov r1, r10
2887 ; CHECK-NEXT: mov r2, r11
2888 ; CHECK-NEXT: mov r3, r10
2889 ; CHECK-NEXT: itt ne
2890 ; CHECK-NEXT: movne r6, #0
2891 ; CHECK-NEXT: mvnne r7, #-2147483648
2892 ; CHECK-NEXT: bl __aeabi_dcmpun
2893 ; CHECK-NEXT: cmp r0, #0
2894 ; CHECK-NEXT: itt ne
2895 ; CHECK-NEXT: movne r7, #0
2896 ; CHECK-NEXT: movne r6, #0
2897 ; CHECK-NEXT: vmov q0[2], q0[0], r7, r5
2898 ; CHECK-NEXT: vmov q0[3], q0[1], r6, r4
2899 ; CHECK-NEXT: add sp, #16
2900 ; CHECK-NEXT: vpop {d8, d9}
2901 ; CHECK-NEXT: add sp, #4
2902 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
2903 ; CHECK-NEXT: .p2align 3
2904 ; CHECK-NEXT: @ %bb.1:
2905 ; CHECK-NEXT: .LCPI37_0:
2906 ; CHECK-NEXT: .long 0 @ double -2147483648
2907 ; CHECK-NEXT: .long 3252682752
2908 ; CHECK-NEXT: .LCPI37_1:
2909 ; CHECK-NEXT: .long 4290772992 @ double 2147483647
2910 ; CHECK-NEXT: .long 1105199103
2911 %x = call <2 x i32> @llvm.fptosi.sat.v2f64.v2i32(<2 x double> %f)
2912 ret <2 x i32> %x
2913 }
2915 define arm_aapcs_vfpcc <2 x i50> @test_signed_v2f64_v2i50(<2 x double> %f) {
2916 ; CHECK-LABEL: test_signed_v2f64_v2i50:
2917 ; CHECK: @ %bb.0:
2918 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
2919 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
2920 ; CHECK-NEXT: .pad #4
2921 ; CHECK-NEXT: sub sp, #4
2922 ; CHECK-NEXT: .vsave {d8, d9}
2923 ; CHECK-NEXT: vpush {d8, d9}
2924 ; CHECK-NEXT: .pad #16
2925 ; CHECK-NEXT: sub sp, #16
2926 ; CHECK-NEXT: vmov q4, q0
2927 ; CHECK-NEXT: vldr d0, .LCPI38_0
2928 ; CHECK-NEXT: vmov r5, r4, d9
2929 ; CHECK-NEXT: vmov r6, r7, d0
2930 ; CHECK-NEXT: mov r0, r5
2931 ; CHECK-NEXT: mov r1, r4
2932 ; CHECK-NEXT: mov r2, r6
2933 ; CHECK-NEXT: mov r3, r7
2934 ; CHECK-NEXT: strd r4, r5, [sp, #8] @ 8-byte Folded Spill
2935 ; CHECK-NEXT: bl __aeabi_dcmpge
2936 ; CHECK-NEXT: mov r11, r0
2937 ; CHECK-NEXT: mov r0, r5
2938 ; CHECK-NEXT: mov r1, r4
2939 ; CHECK-NEXT: bl __aeabi_d2lz
2940 ; CHECK-NEXT: vmov r5, r10, d8
2941 ; CHECK-NEXT: vldr d0, .LCPI38_1
2942 ; CHECK-NEXT: cmp.w r11, #0
2943 ; CHECK-NEXT: mov r4, r1
2944 ; CHECK-NEXT: vmov r9, r8, d0
2945 ; CHECK-NEXT: csel r11, r0, r11, ne
2946 ; CHECK-NEXT: mov r2, r6
2947 ; CHECK-NEXT: mov r3, r7
2948 ; CHECK-NEXT: mov r0, r5
2949 ; CHECK-NEXT: mov r1, r10
2950 ; CHECK-NEXT: str.w r9, [sp, #4] @ 4-byte Spill
2951 ; CHECK-NEXT: itt eq
2952 ; CHECK-NEXT: moveq r4, #0
2953 ; CHECK-NEXT: movteq r4, #65534
2954 ; CHECK-NEXT: bl __aeabi_dcmpge
2955 ; CHECK-NEXT: mov r7, r0
2956 ; CHECK-NEXT: mov r0, r5
2957 ; CHECK-NEXT: mov r1, r10
2958 ; CHECK-NEXT: bl __aeabi_d2lz
2959 ; CHECK-NEXT: cmp r7, #0
2960 ; CHECK-NEXT: mov r6, r1
2961 ; CHECK-NEXT: csel r7, r0, r7, ne
2962 ; CHECK-NEXT: mov r0, r5
2963 ; CHECK-NEXT: mov r1, r10
2964 ; CHECK-NEXT: mov r2, r9
2965 ; CHECK-NEXT: mov r3, r8
2966 ; CHECK-NEXT: itt eq
2967 ; CHECK-NEXT: moveq r6, #0
2968 ; CHECK-NEXT: movteq r6, #65534
2969 ; CHECK-NEXT: bl __aeabi_dcmpgt
2970 ; CHECK-NEXT: cmp r0, #0
2971 ; CHECK-NEXT: ittt ne
2972 ; CHECK-NEXT: movne.w r7, #-1
2973 ; CHECK-NEXT: movwne r6, #65535
2974 ; CHECK-NEXT: movtne r6, #1
2975 ; CHECK-NEXT: ldrd r9, r0, [sp, #8] @ 8-byte Folded Reload
2976 ; CHECK-NEXT: mov r3, r8
2977 ; CHECK-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
2978 ; CHECK-NEXT: mov r1, r9
2979 ; CHECK-NEXT: bl __aeabi_dcmpgt
2980 ; CHECK-NEXT: cmp r0, #0
2981 ; CHECK-NEXT: ittt ne
2982 ; CHECK-NEXT: movne.w r11, #-1
2983 ; CHECK-NEXT: movwne r4, #65535
2984 ; CHECK-NEXT: movtne r4, #1
2985 ; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
2986 ; CHECK-NEXT: mov r1, r9
2987 ; CHECK-NEXT: mov r3, r9
2988 ; CHECK-NEXT: mov r2, r0
2989 ; CHECK-NEXT: bl __aeabi_dcmpun
2990 ; CHECK-NEXT: cmp r0, #0
2991 ; CHECK-NEXT: mov r0, r5
2992 ; CHECK-NEXT: mov r1, r10
2993 ; CHECK-NEXT: mov r2, r5
2994 ; CHECK-NEXT: mov r3, r10
2995 ; CHECK-NEXT: itt ne
2996 ; CHECK-NEXT: movne.w r11, #0
2997 ; CHECK-NEXT: movne r4, #0
2998 ; CHECK-NEXT: bl __aeabi_dcmpun
2999 ; CHECK-NEXT: cmp r0, #0
3000 ; CHECK-NEXT: it ne
3001 ; CHECK-NEXT: movne r7, #0
3002 ; CHECK-NEXT: vmov q0[2], q0[0], r7, r11
3003 ; CHECK-NEXT: it ne
3004 ; CHECK-NEXT: movne r6, #0
3005 ; CHECK-NEXT: vmov q0[3], q0[1], r6, r4
3006 ; CHECK-NEXT: add sp, #16
3007 ; CHECK-NEXT: vpop {d8, d9}
3008 ; CHECK-NEXT: add sp, #4
3009 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
3010 ; CHECK-NEXT: .p2align 3
3011 ; CHECK-NEXT: @ %bb.1:
3012 ; CHECK-NEXT: .LCPI38_0:
3013 ; CHECK-NEXT: .long 0 @ double -562949953421312
3014 ; CHECK-NEXT: .long 3271557120
3015 ; CHECK-NEXT: .LCPI38_1:
3016 ; CHECK-NEXT: .long 4294967280 @ double 562949953421311
3017 ; CHECK-NEXT: .long 1124073471
3018 %x = call <2 x i50> @llvm.fptosi.sat.v2f64.v2i50(<2 x double> %f)
3019 ret <2 x i50> %x
3020 }
3022 define arm_aapcs_vfpcc <2 x i64> @test_signed_v2f64_v2i64(<2 x double> %f) {
3023 ; CHECK-LABEL: test_signed_v2f64_v2i64:
3024 ; CHECK: @ %bb.0:
3025 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
3026 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
3027 ; CHECK-NEXT: .pad #4
3028 ; CHECK-NEXT: sub sp, #4
3029 ; CHECK-NEXT: .vsave {d8, d9}
3030 ; CHECK-NEXT: vpush {d8, d9}
3031 ; CHECK-NEXT: .pad #8
3032 ; CHECK-NEXT: sub sp, #8
3033 ; CHECK-NEXT: vmov q4, q0
3034 ; CHECK-NEXT: vldr d0, .LCPI39_0
3035 ; CHECK-NEXT: vmov r8, r7, d9
3036 ; CHECK-NEXT: vmov r11, r5, d0
3037 ; CHECK-NEXT: mov r0, r8
3038 ; CHECK-NEXT: mov r1, r7
3039 ; CHECK-NEXT: mov r2, r11
3040 ; CHECK-NEXT: mov r3, r5
3041 ; CHECK-NEXT: bl __aeabi_dcmpge
3042 ; CHECK-NEXT: mov r9, r0
3043 ; CHECK-NEXT: mov r0, r8
3044 ; CHECK-NEXT: mov r1, r7
3045 ; CHECK-NEXT: bl __aeabi_d2lz
3046 ; CHECK-NEXT: vldr d0, .LCPI39_1
3047 ; CHECK-NEXT: cmp.w r9, #0
3048 ; CHECK-NEXT: mov r4, r1
3049 ; CHECK-NEXT: csel r9, r0, r9, ne
3050 ; CHECK-NEXT: vmov r2, r3, d0
3051 ; CHECK-NEXT: mov r0, r8
3052 ; CHECK-NEXT: mov r1, r7
3053 ; CHECK-NEXT: vmov r6, r10, d8
3054 ; CHECK-NEXT: strd r2, r3, [sp] @ 8-byte Folded Spill
3055 ; CHECK-NEXT: it eq
3056 ; CHECK-NEXT: moveq.w r4, #-2147483648
3057 ; CHECK-NEXT: bl __aeabi_dcmpgt
3058 ; CHECK-NEXT: cmp r0, #0
3059 ; CHECK-NEXT: mov r0, r8
3060 ; CHECK-NEXT: mov r1, r7
3061 ; CHECK-NEXT: mov r2, r8
3062 ; CHECK-NEXT: mov r3, r7
3063 ; CHECK-NEXT: itt ne
3064 ; CHECK-NEXT: movne.w r9, #-1
3065 ; CHECK-NEXT: mvnne r4, #-2147483648
3066 ; CHECK-NEXT: bl __aeabi_dcmpun
3067 ; CHECK-NEXT: cmp r0, #0
3068 ; CHECK-NEXT: mov r0, r6
3069 ; CHECK-NEXT: mov r1, r10
3070 ; CHECK-NEXT: mov r2, r11
3071 ; CHECK-NEXT: mov r3, r5
3072 ; CHECK-NEXT: itt ne
3073 ; CHECK-NEXT: movne r4, #0
3074 ; CHECK-NEXT: movne.w r9, #0
3075 ; CHECK-NEXT: bl __aeabi_dcmpge
3076 ; CHECK-NEXT: mov r5, r0
3077 ; CHECK-NEXT: mov r0, r6
3078 ; CHECK-NEXT: mov r1, r10
3079 ; CHECK-NEXT: bl __aeabi_d2lz
3080 ; CHECK-NEXT: mov r7, r1
3081 ; CHECK-NEXT: cmp r5, #0
3082 ; CHECK-NEXT: it eq
3083 ; CHECK-NEXT: moveq.w r7, #-2147483648
3084 ; CHECK-NEXT: ldrd r2, r3, [sp] @ 8-byte Folded Reload
3085 ; CHECK-NEXT: csel r5, r0, r5, ne
3086 ; CHECK-NEXT: mov r0, r6
3087 ; CHECK-NEXT: mov r1, r10
3088 ; CHECK-NEXT: bl __aeabi_dcmpgt
3089 ; CHECK-NEXT: cmp r0, #0
3090 ; CHECK-NEXT: mov r0, r6
3091 ; CHECK-NEXT: mov r1, r10
3092 ; CHECK-NEXT: mov r2, r6
3093 ; CHECK-NEXT: mov r3, r10
3094 ; CHECK-NEXT: itt ne
3095 ; CHECK-NEXT: mvnne r7, #-2147483648
3096 ; CHECK-NEXT: movne.w r5, #-1
3097 ; CHECK-NEXT: bl __aeabi_dcmpun
3098 ; CHECK-NEXT: cmp r0, #0
3099 ; CHECK-NEXT: itt ne
3100 ; CHECK-NEXT: movne r5, #0
3101 ; CHECK-NEXT: movne r7, #0
3102 ; CHECK-NEXT: vmov q0[2], q0[0], r5, r9
3103 ; CHECK-NEXT: vmov q0[3], q0[1], r7, r4
3104 ; CHECK-NEXT: add sp, #8
3105 ; CHECK-NEXT: vpop {d8, d9}
3106 ; CHECK-NEXT: add sp, #4
3107 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
3108 ; CHECK-NEXT: .p2align 3
3109 ; CHECK-NEXT: @ %bb.1:
3110 ; CHECK-NEXT: .LCPI39_0:
3111 ; CHECK-NEXT: .long 0 @ double -9.2233720368547758E+18
3112 ; CHECK-NEXT: .long 3286237184
3113 ; CHECK-NEXT: .LCPI39_1:
3114 ; CHECK-NEXT: .long 4294967295 @ double 9.2233720368547748E+18
3115 ; CHECK-NEXT: .long 1138753535
3116 %x = call <2 x i64> @llvm.fptosi.sat.v2f64.v2i64(<2 x double> %f)
3117 ret <2 x i64> %x
3118 }
3120 define arm_aapcs_vfpcc <2 x i100> @test_signed_v2f64_v2i100(<2 x double> %f) {
3121 ; CHECK-LABEL: test_signed_v2f64_v2i100:
3122 ; CHECK: @ %bb.0:
3123 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
3124 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
3125 ; CHECK-NEXT: .pad #4
3126 ; CHECK-NEXT: sub sp, #4
3127 ; CHECK-NEXT: .vsave {d8, d9}
3128 ; CHECK-NEXT: vpush {d8, d9}
3129 ; CHECK-NEXT: .pad #48
3130 ; CHECK-NEXT: sub sp, #48
3131 ; CHECK-NEXT: vmov q4, q0
3132 ; CHECK-NEXT: vldr d0, .LCPI40_0
3133 ; CHECK-NEXT: vmov r7, r6, d8
3134 ; CHECK-NEXT: mov r8, r0
3135 ; CHECK-NEXT: vmov r10, r9, d0
3136 ; CHECK-NEXT: mov r0, r7
3137 ; CHECK-NEXT: mov r1, r6
3138 ; CHECK-NEXT: mov r2, r10
3139 ; CHECK-NEXT: mov r3, r9
3140 ; CHECK-NEXT: bl __aeabi_dcmpge
3141 ; CHECK-NEXT: mov r4, r0
3142 ; CHECK-NEXT: mov r0, r7
3143 ; CHECK-NEXT: mov r1, r6
3144 ; CHECK-NEXT: bl __fixdfti
3145 ; CHECK-NEXT: vldr d0, .LCPI40_1
3146 ; CHECK-NEXT: cmp r4, #0
3147 ; CHECK-NEXT: strd r1, r0, [sp, #16] @ 8-byte Folded Spill
3148 ; CHECK-NEXT: csel r4, r2, r4, ne
3149 ; CHECK-NEXT: vmov r5, r11, d0
3150 ; CHECK-NEXT: str r3, [sp, #32] @ 4-byte Spill
3151 ; CHECK-NEXT: mov r0, r7
3152 ; CHECK-NEXT: mov r1, r6
3153 ; CHECK-NEXT: mov r2, r5
3154 ; CHECK-NEXT: mov r3, r11
3155 ; CHECK-NEXT: bl __aeabi_dcmpgt
3156 ; CHECK-NEXT: cmp r0, #0
3157 ; CHECK-NEXT: mov r0, r7
3158 ; CHECK-NEXT: mov r1, r6
3159 ; CHECK-NEXT: mov r2, r7
3160 ; CHECK-NEXT: mov r3, r6
3161 ; CHECK-NEXT: it ne
3162 ; CHECK-NEXT: movne.w r4, #-1
3163 ; CHECK-NEXT: bl __aeabi_dcmpun
3164 ; CHECK-NEXT: cmp r0, #0
3165 ; CHECK-NEXT: mov r0, r7
3166 ; CHECK-NEXT: mov r1, r6
3167 ; CHECK-NEXT: mov r2, r10
3168 ; CHECK-NEXT: mov r3, r9
3169 ; CHECK-NEXT: it ne
3170 ; CHECK-NEXT: movne r4, #0
3171 ; CHECK-NEXT: str.w r8, [sp, #44] @ 4-byte Spill
3172 ; CHECK-NEXT: str.w r4, [r8, #8]
3173 ; CHECK-NEXT: str.w r9, [sp, #36] @ 4-byte Spill
3174 ; CHECK-NEXT: bl __aeabi_dcmpge
3175 ; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload
3176 ; CHECK-NEXT: cmp r0, #0
3177 ; CHECK-NEXT: mov r2, r5
3178 ; CHECK-NEXT: mov r3, r11
3179 ; CHECK-NEXT: csel r4, r1, r0, ne
3180 ; CHECK-NEXT: mov r0, r7
3181 ; CHECK-NEXT: mov r1, r6
3182 ; CHECK-NEXT: str.w r11, [sp, #40] @ 4-byte Spill
3183 ; CHECK-NEXT: bl __aeabi_dcmpgt
3184 ; CHECK-NEXT: cmp r0, #0
3185 ; CHECK-NEXT: mov r0, r7
3186 ; CHECK-NEXT: mov r1, r6
3187 ; CHECK-NEXT: mov r2, r7
3188 ; CHECK-NEXT: mov r3, r6
3189 ; CHECK-NEXT: it ne
3190 ; CHECK-NEXT: movne.w r4, #-1
3191 ; CHECK-NEXT: bl __aeabi_dcmpun
3192 ; CHECK-NEXT: cmp r0, #0
3193 ; CHECK-NEXT: mov r0, r7
3194 ; CHECK-NEXT: mov r1, r6
3195 ; CHECK-NEXT: mov r2, r10
3196 ; CHECK-NEXT: mov r3, r9
3197 ; CHECK-NEXT: it ne
3198 ; CHECK-NEXT: movne r4, #0
3199 ; CHECK-NEXT: str.w r4, [r8, #4]
3200 ; CHECK-NEXT: bl __aeabi_dcmpge
3201 ; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
3202 ; CHECK-NEXT: cmp r0, #0
3203 ; CHECK-NEXT: mov r2, r5
3204 ; CHECK-NEXT: mov r3, r11
3205 ; CHECK-NEXT: csel r4, r1, r0, ne
3206 ; CHECK-NEXT: mov r0, r7
3207 ; CHECK-NEXT: mov r1, r6
3208 ; CHECK-NEXT: bl __aeabi_dcmpgt
3209 ; CHECK-NEXT: cmp r0, #0
3210 ; CHECK-NEXT: mov r0, r7
3211 ; CHECK-NEXT: mov r1, r6
3212 ; CHECK-NEXT: mov r2, r7
3213 ; CHECK-NEXT: mov r3, r6
3214 ; CHECK-NEXT: it ne
3215 ; CHECK-NEXT: movne.w r4, #-1
3216 ; CHECK-NEXT: str r7, [sp, #24] @ 4-byte Spill
3217 ; CHECK-NEXT: str r6, [sp, #28] @ 4-byte Spill
3218 ; CHECK-NEXT: bl __aeabi_dcmpun
3219 ; CHECK-NEXT: vmov r9, r8, d9
3220 ; CHECK-NEXT: cmp r0, #0
3221 ; CHECK-NEXT: it ne
3222 ; CHECK-NEXT: movne r4, #0
3223 ; CHECK-NEXT: ldr r0, [sp, #44] @ 4-byte Reload
3224 ; CHECK-NEXT: mov r2, r10
3225 ; CHECK-NEXT: str r4, [r0]
3226 ; CHECK-NEXT: ldr.w r11, [sp, #36] @ 4-byte Reload
3227 ; CHECK-NEXT: mov r3, r11
3228 ; CHECK-NEXT: mov r0, r9
3229 ; CHECK-NEXT: mov r1, r8
3230 ; CHECK-NEXT: bl __aeabi_dcmpge
3231 ; CHECK-NEXT: mov r4, r0
3232 ; CHECK-NEXT: mov r0, r9
3233 ; CHECK-NEXT: mov r1, r8
3234 ; CHECK-NEXT: bl __fixdfti
3235 ; CHECK-NEXT: cmp r4, #0
3236 ; CHECK-NEXT: strd r2, r3, [sp, #12] @ 8-byte Folded Spill
3237 ; CHECK-NEXT: csel r7, r1, r4, ne
3238 ; CHECK-NEXT: mov r4, r5
3239 ; CHECK-NEXT: str r5, [sp, #4] @ 4-byte Spill
3240 ; CHECK-NEXT: mov r2, r5
3241 ; CHECK-NEXT: ldr r5, [sp, #40] @ 4-byte Reload
3242 ; CHECK-NEXT: mov r6, r0
3243 ; CHECK-NEXT: mov r0, r9
3244 ; CHECK-NEXT: mov r1, r8
3245 ; CHECK-NEXT: mov r3, r5
3246 ; CHECK-NEXT: bl __aeabi_dcmpgt
3247 ; CHECK-NEXT: cmp r0, #0
3248 ; CHECK-NEXT: mov r0, r9
3249 ; CHECK-NEXT: mov r1, r8
3250 ; CHECK-NEXT: mov r2, r9
3251 ; CHECK-NEXT: mov r3, r8
3252 ; CHECK-NEXT: it ne
3253 ; CHECK-NEXT: movne.w r7, #-1
3254 ; CHECK-NEXT: bl __aeabi_dcmpun
3255 ; CHECK-NEXT: cmp r0, #0
3256 ; CHECK-NEXT: mov r0, r9
3257 ; CHECK-NEXT: mov r1, r8
3258 ; CHECK-NEXT: mov r2, r10
3259 ; CHECK-NEXT: mov r3, r11
3260 ; CHECK-NEXT: it ne
3261 ; CHECK-NEXT: movne r7, #0
3262 ; CHECK-NEXT: bl __aeabi_dcmpge
3263 ; CHECK-NEXT: cmp r0, #0
3264 ; CHECK-NEXT: mov r1, r8
3265 ; CHECK-NEXT: csel r6, r6, r0, ne
3266 ; CHECK-NEXT: mov r0, r9
3267 ; CHECK-NEXT: mov r2, r4
3268 ; CHECK-NEXT: mov r3, r5
3269 ; CHECK-NEXT: bl __aeabi_dcmpgt
3270 ; CHECK-NEXT: cmp r0, #0
3271 ; CHECK-NEXT: mov r0, r9
3272 ; CHECK-NEXT: mov r1, r8
3273 ; CHECK-NEXT: mov r2, r9
3274 ; CHECK-NEXT: mov r3, r8
3275 ; CHECK-NEXT: it ne
3276 ; CHECK-NEXT: movne.w r6, #-1
3277 ; CHECK-NEXT: bl __aeabi_dcmpun
3278 ; CHECK-NEXT: cmp r0, #0
3279 ; CHECK-NEXT: mov r0, r6
3280 ; CHECK-NEXT: it ne
3281 ; CHECK-NEXT: movne r0, #0
3282 ; CHECK-NEXT: ldr r1, [sp, #44] @ 4-byte Reload
3283 ; CHECK-NEXT: str r0, [sp, #20] @ 4-byte Spill
3284 ; CHECK-NEXT: lsrl r0, r7, #28
3285 ; CHECK-NEXT: mov r2, r10
3286 ; CHECK-NEXT: mov r3, r11
3287 ; CHECK-NEXT: str r0, [r1, #16]
3288 ; CHECK-NEXT: mov r0, r9
3289 ; CHECK-NEXT: mov r1, r8
3290 ; CHECK-NEXT: str.w r10, [sp, #8] @ 4-byte Spill
3291 ; CHECK-NEXT: mov r6, r11
3292 ; CHECK-NEXT: bl __aeabi_dcmpge
3293 ; CHECK-NEXT: ldr r5, [sp, #4] @ 4-byte Reload
3294 ; CHECK-NEXT: cmp r0, #0
3295 ; CHECK-NEXT: ldr.w r11, [sp, #40] @ 4-byte Reload
3296 ; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
3297 ; CHECK-NEXT: mov r2, r5
3298 ; CHECK-NEXT: csel r4, r1, r0, ne
3299 ; CHECK-NEXT: mov r0, r9
3300 ; CHECK-NEXT: mov r1, r8
3301 ; CHECK-NEXT: mov r3, r11
3302 ; CHECK-NEXT: bl __aeabi_dcmpgt
3303 ; CHECK-NEXT: cmp r0, #0
3304 ; CHECK-NEXT: mov r0, r9
3305 ; CHECK-NEXT: mov r1, r8
3306 ; CHECK-NEXT: mov r2, r9
3307 ; CHECK-NEXT: mov r3, r8
3308 ; CHECK-NEXT: it ne
3309 ; CHECK-NEXT: movne.w r4, #-1
3310 ; CHECK-NEXT: bl __aeabi_dcmpun
3311 ; CHECK-NEXT: cmp r0, #0
3312 ; CHECK-NEXT: it ne
3313 ; CHECK-NEXT: movne r4, #0
3314 ; CHECK-NEXT: orr.w r0, r7, r4, lsl #4
3315 ; CHECK-NEXT: ldr r7, [sp, #44] @ 4-byte Reload
3316 ; CHECK-NEXT: mov r1, r8
3317 ; CHECK-NEXT: mov r2, r10
3318 ; CHECK-NEXT: mov r3, r6
3319 ; CHECK-NEXT: str r0, [r7, #20]
3320 ; CHECK-NEXT: mov r0, r9
3321 ; CHECK-NEXT: bl __aeabi_dcmpge
3322 ; CHECK-NEXT: cmp r0, #0
3323 ; CHECK-NEXT: ldr r6, [sp, #16] @ 4-byte Reload
3324 ; CHECK-NEXT: mov r0, r9
3325 ; CHECK-NEXT: mov r1, r8
3326 ; CHECK-NEXT: mov r2, r5
3327 ; CHECK-NEXT: mov r3, r11
3328 ; CHECK-NEXT: it eq
3329 ; CHECK-NEXT: mvneq r6, #7
3330 ; CHECK-NEXT: mov r10, r5
3331 ; CHECK-NEXT: bl __aeabi_dcmpgt
3332 ; CHECK-NEXT: cmp r0, #0
3333 ; CHECK-NEXT: mov r0, r9
3334 ; CHECK-NEXT: mov r1, r8
3335 ; CHECK-NEXT: mov r2, r9
3336 ; CHECK-NEXT: mov r3, r8
3337 ; CHECK-NEXT: it ne
3338 ; CHECK-NEXT: movne r6, #7
3339 ; CHECK-NEXT: bl __aeabi_dcmpun
3340 ; CHECK-NEXT: cmp r0, #0
3341 ; CHECK-NEXT: mov r0, r6
3342 ; CHECK-NEXT: it ne
3343 ; CHECK-NEXT: movne r0, #0
3344 ; CHECK-NEXT: and r1, r0, #15
3345 ; CHECK-NEXT: lsrl r4, r1, #28
3346 ; CHECK-NEXT: strb r4, [r7, #24]
3347 ; CHECK-NEXT: ldr r5, [sp, #24] @ 4-byte Reload
3348 ; CHECK-NEXT: ldr r6, [sp, #28] @ 4-byte Reload
3349 ; CHECK-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
3350 ; CHECK-NEXT: ldr r3, [sp, #36] @ 4-byte Reload
3351 ; CHECK-NEXT: mov r0, r5
3352 ; CHECK-NEXT: mov r1, r6
3353 ; CHECK-NEXT: bl __aeabi_dcmpge
3354 ; CHECK-NEXT: cmp r0, #0
3355 ; CHECK-NEXT: ldr r4, [sp, #32] @ 4-byte Reload
3356 ; CHECK-NEXT: mov r0, r5
3357 ; CHECK-NEXT: mov r1, r6
3358 ; CHECK-NEXT: mov r2, r10
3359 ; CHECK-NEXT: mov r3, r11
3360 ; CHECK-NEXT: it eq
3361 ; CHECK-NEXT: mvneq r4, #7
3362 ; CHECK-NEXT: bl __aeabi_dcmpgt
3363 ; CHECK-NEXT: cmp r0, #0
3364 ; CHECK-NEXT: mov r0, r5
3365 ; CHECK-NEXT: mov r1, r6
3366 ; CHECK-NEXT: mov r2, r5
3367 ; CHECK-NEXT: mov r3, r6
3368 ; CHECK-NEXT: it ne
3369 ; CHECK-NEXT: movne r4, #7
3370 ; CHECK-NEXT: bl __aeabi_dcmpun
3371 ; CHECK-NEXT: cmp r0, #0
3372 ; CHECK-NEXT: mov r0, r4
3373 ; CHECK-NEXT: it ne
3374 ; CHECK-NEXT: movne r0, #0
3375 ; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
3376 ; CHECK-NEXT: and r0, r0, #15
3377 ; CHECK-NEXT: orr.w r0, r0, r1, lsl #4
3378 ; CHECK-NEXT: str r0, [r7, #12]
3379 ; CHECK-NEXT: add sp, #48
3380 ; CHECK-NEXT: vpop {d8, d9}
3381 ; CHECK-NEXT: add sp, #4
3382 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
3383 ; CHECK-NEXT: .p2align 3
3384 ; CHECK-NEXT: @ %bb.1:
3385 ; CHECK-NEXT: .LCPI40_0:
3386 ; CHECK-NEXT: .long 0 @ double -6.338253001141147E+29
3387 ; CHECK-NEXT: .long 3323985920
3388 ; CHECK-NEXT: .LCPI40_1:
3389 ; CHECK-NEXT: .long 4294967295 @ double 6.3382530011411463E+29
3390 ; CHECK-NEXT: .long 1176502271
3391 %x = call <2 x i100> @llvm.fptosi.sat.v2f64.v2i100(<2 x double> %f)
3392 ret <2 x i100> %x
3393 }
3395 define arm_aapcs_vfpcc <2 x i128> @test_signed_v2f64_v2i128(<2 x double> %f) {
3396 ; CHECK-LABEL: test_signed_v2f64_v2i128:
3397 ; CHECK: @ %bb.0:
3398 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
3399 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
3400 ; CHECK-NEXT: .pad #4
3401 ; CHECK-NEXT: sub sp, #4
3402 ; CHECK-NEXT: .vsave {d8, d9}
3403 ; CHECK-NEXT: vpush {d8, d9}
3404 ; CHECK-NEXT: .pad #32
3405 ; CHECK-NEXT: sub sp, #32
3406 ; CHECK-NEXT: vmov q4, q0
3407 ; CHECK-NEXT: vldr d0, .LCPI41_0
3408 ; CHECK-NEXT: vmov r8, r7, d9
3409 ; CHECK-NEXT: mov r9, r0
3410 ; CHECK-NEXT: vmov r2, r3, d0
3411 ; CHECK-NEXT: str r3, [sp, #16] @ 4-byte Spill
3412 ; CHECK-NEXT: mov r0, r8
3413 ; CHECK-NEXT: mov r1, r7
3414 ; CHECK-NEXT: mov r4, r2
3415 ; CHECK-NEXT: bl __aeabi_dcmpge
3416 ; CHECK-NEXT: mov r6, r0
3417 ; CHECK-NEXT: mov r0, r8
3418 ; CHECK-NEXT: mov r1, r7
3419 ; CHECK-NEXT: bl __fixdfti
3420 ; CHECK-NEXT: vldr d0, .LCPI41_1
3421 ; CHECK-NEXT: mov r5, r3
3422 ; CHECK-NEXT: strd r1, r0, [sp, #8] @ 8-byte Folded Spill
3423 ; CHECK-NEXT: mov r0, r8
3424 ; CHECK-NEXT: vmov r10, r11, d0
3425 ; CHECK-NEXT: str r2, [sp] @ 4-byte Spill
3426 ; CHECK-NEXT: mov r1, r7
3427 ; CHECK-NEXT: cmp r6, #0
3428 ; CHECK-NEXT: it eq
3429 ; CHECK-NEXT: moveq.w r5, #-2147483648
3430 ; CHECK-NEXT: str.w r11, [sp, #20] @ 4-byte Spill
3431 ; CHECK-NEXT: mov r2, r10
3432 ; CHECK-NEXT: mov r3, r11
3433 ; CHECK-NEXT: bl __aeabi_dcmpgt
3434 ; CHECK-NEXT: cmp r0, #0
3435 ; CHECK-NEXT: mov r0, r8
3436 ; CHECK-NEXT: mov r1, r7
3437 ; CHECK-NEXT: mov r2, r8
3438 ; CHECK-NEXT: mov r3, r7
3439 ; CHECK-NEXT: it ne
3440 ; CHECK-NEXT: mvnne r5, #-2147483648
3441 ; CHECK-NEXT: bl __aeabi_dcmpun
3442 ; CHECK-NEXT: cmp r0, #0
3443 ; CHECK-NEXT: it ne
3444 ; CHECK-NEXT: movne r5, #0
3445 ; CHECK-NEXT: str.w r5, [r9, #28]
3446 ; CHECK-NEXT: mov r0, r8
3447 ; CHECK-NEXT: ldr r6, [sp, #16] @ 4-byte Reload
3448 ; CHECK-NEXT: mov r1, r7
3449 ; CHECK-NEXT: mov r2, r4
3450 ; CHECK-NEXT: str r4, [sp, #24] @ 4-byte Spill
3451 ; CHECK-NEXT: mov r3, r6
3452 ; CHECK-NEXT: bl __aeabi_dcmpge
3453 ; CHECK-NEXT: ldr r1, [sp] @ 4-byte Reload
3454 ; CHECK-NEXT: cmp r0, #0
3455 ; CHECK-NEXT: mov r2, r10
3456 ; CHECK-NEXT: mov r3, r11
3457 ; CHECK-NEXT: csel r5, r1, r0, ne
3458 ; CHECK-NEXT: mov r0, r8
3459 ; CHECK-NEXT: mov r1, r7
3460 ; CHECK-NEXT: str.w r10, [sp, #28] @ 4-byte Spill
3461 ; CHECK-NEXT: bl __aeabi_dcmpgt
3462 ; CHECK-NEXT: cmp r0, #0
3463 ; CHECK-NEXT: mov r0, r8
3464 ; CHECK-NEXT: mov r1, r7
3465 ; CHECK-NEXT: mov r2, r8
3466 ; CHECK-NEXT: mov r3, r7
3467 ; CHECK-NEXT: it ne
3468 ; CHECK-NEXT: movne.w r5, #-1
3469 ; CHECK-NEXT: bl __aeabi_dcmpun
3470 ; CHECK-NEXT: cmp r0, #0
3471 ; CHECK-NEXT: mov r0, r8
3472 ; CHECK-NEXT: mov r1, r7
3473 ; CHECK-NEXT: mov r2, r4
3474 ; CHECK-NEXT: mov r3, r6
3475 ; CHECK-NEXT: it ne
3476 ; CHECK-NEXT: movne r5, #0
3477 ; CHECK-NEXT: str.w r5, [r9, #24]
3478 ; CHECK-NEXT: mov r11, r6
3479 ; CHECK-NEXT: bl __aeabi_dcmpge
3480 ; CHECK-NEXT: ldr r1, [sp, #8] @ 4-byte Reload
3481 ; CHECK-NEXT: cmp r0, #0
3482 ; CHECK-NEXT: ldr r3, [sp, #20] @ 4-byte Reload
3483 ; CHECK-NEXT: mov r2, r10
3484 ; CHECK-NEXT: csel r4, r1, r0, ne
3485 ; CHECK-NEXT: mov r0, r8
3486 ; CHECK-NEXT: mov r1, r7
3487 ; CHECK-NEXT: bl __aeabi_dcmpgt
3488 ; CHECK-NEXT: cmp r0, #0
3489 ; CHECK-NEXT: mov r0, r8
3490 ; CHECK-NEXT: mov r1, r7
3491 ; CHECK-NEXT: mov r2, r8
3492 ; CHECK-NEXT: mov r3, r7
3493 ; CHECK-NEXT: it ne
3494 ; CHECK-NEXT: movne.w r4, #-1
3495 ; CHECK-NEXT: bl __aeabi_dcmpun
3496 ; CHECK-NEXT: cmp r0, #0
3497 ; CHECK-NEXT: it ne
3498 ; CHECK-NEXT: movne r4, #0
3499 ; CHECK-NEXT: str.w r4, [r9, #20]
3500 ; CHECK-NEXT: mov r0, r8
3501 ; CHECK-NEXT: ldr r2, [sp, #24] @ 4-byte Reload
3502 ; CHECK-NEXT: mov r1, r7
3503 ; CHECK-NEXT: mov r3, r11
3504 ; CHECK-NEXT: vmov r6, r5, d8
3505 ; CHECK-NEXT: mov r10, r9
3506 ; CHECK-NEXT: str.w r9, [sp, #4] @ 4-byte Spill
3507 ; CHECK-NEXT: mov r9, r11
3508 ; CHECK-NEXT: bl __aeabi_dcmpge
3509 ; CHECK-NEXT: ldr.w r11, [sp, #20] @ 4-byte Reload
3510 ; CHECK-NEXT: cmp r0, #0
3511 ; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
3512 ; CHECK-NEXT: ldr r2, [sp, #28] @ 4-byte Reload
3513 ; CHECK-NEXT: csel r4, r1, r0, ne
3514 ; CHECK-NEXT: mov r0, r8
3515 ; CHECK-NEXT: mov r1, r7
3516 ; CHECK-NEXT: mov r3, r11
3517 ; CHECK-NEXT: bl __aeabi_dcmpgt
3518 ; CHECK-NEXT: cmp r0, #0
3519 ; CHECK-NEXT: mov r0, r8
3520 ; CHECK-NEXT: mov r1, r7
3521 ; CHECK-NEXT: mov r2, r8
3522 ; CHECK-NEXT: mov r3, r7
3523 ; CHECK-NEXT: it ne
3524 ; CHECK-NEXT: movne.w r4, #-1
3525 ; CHECK-NEXT: bl __aeabi_dcmpun
3526 ; CHECK-NEXT: cmp r0, #0
3527 ; CHECK-NEXT: it ne
3528 ; CHECK-NEXT: movne r4, #0
3529 ; CHECK-NEXT: str.w r4, [r10, #16]
3530 ; CHECK-NEXT: mov r0, r6
3531 ; CHECK-NEXT: ldr.w r8, [sp, #24] @ 4-byte Reload
3532 ; CHECK-NEXT: mov r1, r5
3533 ; CHECK-NEXT: mov r3, r9
3534 ; CHECK-NEXT: mov r2, r8
3535 ; CHECK-NEXT: bl __aeabi_dcmpge
3536 ; CHECK-NEXT: mov r7, r0
3537 ; CHECK-NEXT: mov r0, r6
3538 ; CHECK-NEXT: mov r1, r5
3539 ; CHECK-NEXT: bl __fixdfti
3540 ; CHECK-NEXT: mov r9, r3
3541 ; CHECK-NEXT: strd r1, r0, [sp, #8] @ 8-byte Folded Spill
3542 ; CHECK-NEXT: cmp r7, #0
3543 ; CHECK-NEXT: it eq
3544 ; CHECK-NEXT: moveq.w r9, #-2147483648
3545 ; CHECK-NEXT: ldr.w r10, [sp, #28] @ 4-byte Reload
3546 ; CHECK-NEXT: mov r4, r2
3547 ; CHECK-NEXT: mov r0, r6
3548 ; CHECK-NEXT: mov r1, r5
3549 ; CHECK-NEXT: mov r3, r11
3550 ; CHECK-NEXT: mov r2, r10
3551 ; CHECK-NEXT: bl __aeabi_dcmpgt
3552 ; CHECK-NEXT: cmp r0, #0
3553 ; CHECK-NEXT: mov r0, r6
3554 ; CHECK-NEXT: mov r1, r5
3555 ; CHECK-NEXT: mov r2, r6
3556 ; CHECK-NEXT: mov r3, r5
3557 ; CHECK-NEXT: it ne
3558 ; CHECK-NEXT: mvnne r9, #-2147483648
3559 ; CHECK-NEXT: bl __aeabi_dcmpun
3560 ; CHECK-NEXT: cmp r0, #0
3561 ; CHECK-NEXT: it ne
3562 ; CHECK-NEXT: movne.w r9, #0
3563 ; CHECK-NEXT: ldr r7, [sp, #4] @ 4-byte Reload
3564 ; CHECK-NEXT: mov r0, r6
3565 ; CHECK-NEXT: mov r1, r5
3566 ; CHECK-NEXT: mov r2, r8
3567 ; CHECK-NEXT: str.w r9, [r7, #12]
3568 ; CHECK-NEXT: ldr.w r9, [sp, #16] @ 4-byte Reload
3569 ; CHECK-NEXT: mov r3, r9
3570 ; CHECK-NEXT: bl __aeabi_dcmpge
3571 ; CHECK-NEXT: cmp r0, #0
3572 ; CHECK-NEXT: mov r1, r5
3573 ; CHECK-NEXT: csel r4, r4, r0, ne
3574 ; CHECK-NEXT: mov r0, r6
3575 ; CHECK-NEXT: mov r2, r10
3576 ; CHECK-NEXT: mov r3, r11
3577 ; CHECK-NEXT: bl __aeabi_dcmpgt
3578 ; CHECK-NEXT: cmp r0, #0
3579 ; CHECK-NEXT: mov r0, r6
3580 ; CHECK-NEXT: mov r1, r5
3581 ; CHECK-NEXT: mov r2, r6
3582 ; CHECK-NEXT: mov r3, r5
3583 ; CHECK-NEXT: it ne
3584 ; CHECK-NEXT: movne.w r4, #-1
3585 ; CHECK-NEXT: bl __aeabi_dcmpun
3586 ; CHECK-NEXT: cmp r0, #0
3587 ; CHECK-NEXT: mov r0, r6
3588 ; CHECK-NEXT: mov r1, r5
3589 ; CHECK-NEXT: mov r2, r8
3590 ; CHECK-NEXT: mov r3, r9
3591 ; CHECK-NEXT: it ne
3592 ; CHECK-NEXT: movne r4, #0
3593 ; CHECK-NEXT: str r4, [r7, #8]
3594 ; CHECK-NEXT: bl __aeabi_dcmpge
3595 ; CHECK-NEXT: ldr r1, [sp, #8] @ 4-byte Reload
3596 ; CHECK-NEXT: cmp r0, #0
3597 ; CHECK-NEXT: mov r2, r10
3598 ; CHECK-NEXT: mov r3, r11
3599 ; CHECK-NEXT: csel r4, r1, r0, ne
3600 ; CHECK-NEXT: mov r0, r6
3601 ; CHECK-NEXT: mov r1, r5
3602 ; CHECK-NEXT: bl __aeabi_dcmpgt
3603 ; CHECK-NEXT: cmp r0, #0
3604 ; CHECK-NEXT: mov r0, r6
3605 ; CHECK-NEXT: mov r1, r5
3606 ; CHECK-NEXT: mov r2, r6
3607 ; CHECK-NEXT: mov r3, r5
3608 ; CHECK-NEXT: it ne
3609 ; CHECK-NEXT: movne.w r4, #-1
3610 ; CHECK-NEXT: bl __aeabi_dcmpun
3611 ; CHECK-NEXT: cmp r0, #0
3612 ; CHECK-NEXT: mov r0, r6
3613 ; CHECK-NEXT: mov r1, r5
3614 ; CHECK-NEXT: mov r2, r8
3615 ; CHECK-NEXT: mov r3, r9
3616 ; CHECK-NEXT: it ne
3617 ; CHECK-NEXT: movne r4, #0
3618 ; CHECK-NEXT: str r4, [r7, #4]
3619 ; CHECK-NEXT: bl __aeabi_dcmpge
3620 ; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
3621 ; CHECK-NEXT: cmp r0, #0
3622 ; CHECK-NEXT: mov r2, r10
3623 ; CHECK-NEXT: mov r3, r11
3624 ; CHECK-NEXT: csel r4, r1, r0, ne
3625 ; CHECK-NEXT: mov r0, r6
3626 ; CHECK-NEXT: mov r1, r5
3627 ; CHECK-NEXT: bl __aeabi_dcmpgt
3628 ; CHECK-NEXT: cmp r0, #0
3629 ; CHECK-NEXT: mov r0, r6
3630 ; CHECK-NEXT: mov r1, r5
3631 ; CHECK-NEXT: mov r2, r6
3632 ; CHECK-NEXT: mov r3, r5
3633 ; CHECK-NEXT: it ne
3634 ; CHECK-NEXT: movne.w r4, #-1
3635 ; CHECK-NEXT: bl __aeabi_dcmpun
3636 ; CHECK-NEXT: cmp r0, #0
3637 ; CHECK-NEXT: it ne
3638 ; CHECK-NEXT: movne r4, #0
3639 ; CHECK-NEXT: str r4, [r7]
3640 ; CHECK-NEXT: add sp, #32
3641 ; CHECK-NEXT: vpop {d8, d9}
3642 ; CHECK-NEXT: add sp, #4
3643 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
3644 ; CHECK-NEXT: .p2align 3
3645 ; CHECK-NEXT: @ %bb.1:
3646 ; CHECK-NEXT: .LCPI41_0:
3647 ; CHECK-NEXT: .long 0 @ double -1.7014118346046923E+38
3648 ; CHECK-NEXT: .long 3353346048
3649 ; CHECK-NEXT: .LCPI41_1:
3650 ; CHECK-NEXT: .long 4294967295 @ double 1.7014118346046921E+38
3651 ; CHECK-NEXT: .long 1205862399
3652 %x = call <2 x i128> @llvm.fptosi.sat.v2f64.v2i128(<2 x double> %f)
3653 ret <2 x i128> %x
3654 }
3656 ;
3657 ; 4-Vector half to signed integer -- result size variation
3658 ;
3660 declare <8 x i1> @llvm.fptosi.sat.v8f16.v8i1 (<8 x half>)
3661 declare <8 x i8> @llvm.fptosi.sat.v8f16.v8i8 (<8 x half>)
3662 declare <8 x i13> @llvm.fptosi.sat.v8f16.v8i13 (<8 x half>)
3663 declare <8 x i16> @llvm.fptosi.sat.v8f16.v8i16 (<8 x half>)
3664 declare <8 x i19> @llvm.fptosi.sat.v8f16.v8i19 (<8 x half>)
3665 declare <8 x i50> @llvm.fptosi.sat.v8f16.v8i50 (<8 x half>)
3666 declare <8 x i64> @llvm.fptosi.sat.v8f16.v8i64 (<8 x half>)
3667 declare <8 x i100> @llvm.fptosi.sat.v8f16.v8i100(<8 x half>)
3668 declare <8 x i128> @llvm.fptosi.sat.v8f16.v8i128(<8 x half>)
3670 define arm_aapcs_vfpcc <8 x i1> @test_signed_v8f16_v8i1(<8 x half> %f) {
3671 ; CHECK-LABEL: test_signed_v8f16_v8i1:
3672 ; CHECK: @ %bb.0:
3673 ; CHECK-NEXT: .vsave {d8}
3674 ; CHECK-NEXT: vpush {d8}
3675 ; CHECK-NEXT: vcvtb.f32.f16 s15, s0
3676 ; CHECK-NEXT: vmov.f32 s7, #-1.000000e+00
3677 ; CHECK-NEXT: vldr s5, .LCPI42_0
3678 ; CHECK-NEXT: vmaxnm.f32 s16, s15, s7
3679 ; CHECK-NEXT: vcvtt.f32.f16 s12, s2
3680 ; CHECK-NEXT: vcvtt.f32.f16 s9, s1
3681 ; CHECK-NEXT: vminnm.f32 s16, s16, s5
3682 ; CHECK-NEXT: vcvtt.f32.f16 s4, s3
3683 ; CHECK-NEXT: vcvt.s32.f32 s16, s16
3684 ; CHECK-NEXT: vcvtb.f32.f16 s8, s3
3685 ; CHECK-NEXT: vcvtb.f32.f16 s2, s2
3686 ; CHECK-NEXT: vcvtb.f32.f16 s1, s1
3687 ; CHECK-NEXT: vcvtt.f32.f16 s0, s0
3688 ; CHECK-NEXT: vmaxnm.f32 s6, s4, s7
3689 ; CHECK-NEXT: vmaxnm.f32 s10, s8, s7
3690 ; CHECK-NEXT: vmaxnm.f32 s14, s12, s7
3691 ; CHECK-NEXT: vmaxnm.f32 s3, s2, s7
3692 ; CHECK-NEXT: vmaxnm.f32 s11, s9, s7
3693 ; CHECK-NEXT: vmaxnm.f32 s13, s1, s7
3694 ; CHECK-NEXT: vmaxnm.f32 s7, s0, s7
3695 ; CHECK-NEXT: vminnm.f32 s6, s6, s5
3696 ; CHECK-NEXT: vminnm.f32 s10, s10, s5
3697 ; CHECK-NEXT: vminnm.f32 s14, s14, s5
3698 ; CHECK-NEXT: vminnm.f32 s3, s3, s5
3699 ; CHECK-NEXT: vminnm.f32 s11, s11, s5
3700 ; CHECK-NEXT: vminnm.f32 s13, s13, s5
3701 ; CHECK-NEXT: vminnm.f32 s5, s7, s5
3702 ; CHECK-NEXT: vcmp.f32 s15, s15
3703 ; CHECK-NEXT: vcvt.s32.f32 s5, s5
3704 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
3705 ; CHECK-NEXT: vmov r2, s16
3706 ; CHECK-NEXT: mov.w r1, #0
3707 ; CHECK-NEXT: it vs
3708 ; CHECK-NEXT: movvs r2, #0
3709 ; CHECK-NEXT: vcvt.s32.f32 s13, s13
3710 ; CHECK-NEXT: and r2, r2, #1
3711 ; CHECK-NEXT: vcmp.f32 s0, s0
3712 ; CHECK-NEXT: rsbs r2, r2, #0
3713 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
3714 ; CHECK-NEXT: bfi r1, r2, #0, #1
3715 ; CHECK-NEXT: vcvt.s32.f32 s11, s11
3716 ; CHECK-NEXT: vcmp.f32 s1, s1
3717 ; CHECK-NEXT: vmov r2, s5
3718 ; CHECK-NEXT: it vs
3719 ; CHECK-NEXT: movvs r2, #0
3720 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
3721 ; CHECK-NEXT: and r2, r2, #1
3722 ; CHECK-NEXT: vcvt.s32.f32 s3, s3
3723 ; CHECK-NEXT: rsb.w r2, r2, #0
3724 ; CHECK-NEXT: vcmp.f32 s9, s9
3725 ; CHECK-NEXT: bfi r1, r2, #1, #1
3726 ; CHECK-NEXT: vmov r2, s13
3727 ; CHECK-NEXT: it vs
3728 ; CHECK-NEXT: movvs r2, #0
3729 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
3730 ; CHECK-NEXT: and r2, r2, #1
3731 ; CHECK-NEXT: vcvt.s32.f32 s14, s14
3732 ; CHECK-NEXT: rsb.w r2, r2, #0
3733 ; CHECK-NEXT: vcmp.f32 s2, s2
3734 ; CHECK-NEXT: bfi r1, r2, #2, #1
3735 ; CHECK-NEXT: vmov r2, s11
3736 ; CHECK-NEXT: it vs
3737 ; CHECK-NEXT: movvs r2, #0
3738 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
3739 ; CHECK-NEXT: and r2, r2, #1
3740 ; CHECK-NEXT: vcvt.s32.f32 s10, s10
3741 ; CHECK-NEXT: rsb.w r2, r2, #0
3742 ; CHECK-NEXT: vcmp.f32 s12, s12
3743 ; CHECK-NEXT: bfi r1, r2, #3, #1
3744 ; CHECK-NEXT: vmov r2, s3
3745 ; CHECK-NEXT: it vs
3746 ; CHECK-NEXT: movvs r2, #0
3747 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
3748 ; CHECK-NEXT: and r2, r2, #1
3749 ; CHECK-NEXT: vcvt.s32.f32 s6, s6
3750 ; CHECK-NEXT: rsb.w r2, r2, #0
3751 ; CHECK-NEXT: vcmp.f32 s8, s8
3752 ; CHECK-NEXT: bfi r1, r2, #4, #1
3753 ; CHECK-NEXT: vmov r2, s14
3754 ; CHECK-NEXT: it vs
3755 ; CHECK-NEXT: movvs r2, #0
3756 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
3757 ; CHECK-NEXT: and r2, r2, #1
3758 ; CHECK-NEXT: vcmp.f32 s4, s4
3759 ; CHECK-NEXT: rsb.w r2, r2, #0
3760 ; CHECK-NEXT: bfi r1, r2, #5, #1
3761 ; CHECK-NEXT: vmov r2, s10
3762 ; CHECK-NEXT: it vs
3763 ; CHECK-NEXT: movvs r2, #0
3764 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
3765 ; CHECK-NEXT: and r2, r2, #1
3766 ; CHECK-NEXT: rsb.w r2, r2, #0
3767 ; CHECK-NEXT: bfi r1, r2, #6, #1
3768 ; CHECK-NEXT: vmov r2, s6
3769 ; CHECK-NEXT: it vs
3770 ; CHECK-NEXT: movvs r2, #0
3771 ; CHECK-NEXT: and r2, r2, #1
3772 ; CHECK-NEXT: rsbs r2, r2, #0
3773 ; CHECK-NEXT: bfi r1, r2, #7, #1
3774 ; CHECK-NEXT: strb r1, [r0]
3775 ; CHECK-NEXT: vpop {d8}
3776 ; CHECK-NEXT: bx lr
3777 ; CHECK-NEXT: .p2align 2
3778 ; CHECK-NEXT: @ %bb.1:
3779 ; CHECK-NEXT: .LCPI42_0:
3780 ; CHECK-NEXT: .long 0x00000000 @ float 0
3781 %x = call <8 x i1> @llvm.fptosi.sat.v8f16.v8i1(<8 x half> %f)
3782 ret <8 x i1> %x
3783 }
3785 define arm_aapcs_vfpcc <8 x i8> @test_signed_v8f16_v8i8(<8 x half> %f) {
3786 ; CHECK-MVE-LABEL: test_signed_v8f16_v8i8:
3787 ; CHECK-MVE: @ %bb.0:
3788 ; CHECK-MVE-NEXT: .save {r4, r5, r7, lr}
3789 ; CHECK-MVE-NEXT: push {r4, r5, r7, lr}
3790 ; CHECK-MVE-NEXT: .vsave {d8}
3791 ; CHECK-MVE-NEXT: vpush {d8}
3792 ; CHECK-MVE-NEXT: vldr s6, .LCPI43_1
3793 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s13, s3
3794 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s3, s3
3795 ; CHECK-MVE-NEXT: vldr s4, .LCPI43_0
3796 ; CHECK-MVE-NEXT: vmaxnm.f32 s16, s3, s6
3797 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s7, s2
3798 ; CHECK-MVE-NEXT: vmaxnm.f32 s15, s13, s6
3799 ; CHECK-MVE-NEXT: vminnm.f32 s16, s16, s4
3800 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s2
3801 ; CHECK-MVE-NEXT: vminnm.f32 s15, s15, s4
3802 ; CHECK-MVE-NEXT: vmaxnm.f32 s11, s2, s6
3803 ; CHECK-MVE-NEXT: vcvt.s32.f32 s16, s16
3804 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s12, s1
3805 ; CHECK-MVE-NEXT: vmaxnm.f32 s9, s7, s6
3806 ; CHECK-MVE-NEXT: vminnm.f32 s11, s11, s4
3807 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s1, s1
3808 ; CHECK-MVE-NEXT: vcvt.s32.f32 s15, s15
3809 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s8, s0
3810 ; CHECK-MVE-NEXT: vmaxnm.f32 s5, s1, s6
3811 ; CHECK-MVE-NEXT: vminnm.f32 s9, s9, s4
3812 ; CHECK-MVE-NEXT: vcvt.s32.f32 s11, s11
3813 ; CHECK-MVE-NEXT: vmaxnm.f32 s10, s8, s6
3814 ; CHECK-MVE-NEXT: vmaxnm.f32 s14, s12, s6
3815 ; CHECK-MVE-NEXT: vminnm.f32 s5, s5, s4
3816 ; CHECK-MVE-NEXT: vcvt.s32.f32 s9, s9
3817 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s0, s0
3818 ; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s4
3819 ; CHECK-MVE-NEXT: vminnm.f32 s14, s14, s4
3820 ; CHECK-MVE-NEXT: vcvt.s32.f32 s5, s5
3821 ; CHECK-MVE-NEXT: vmaxnm.f32 s6, s0, s6
3822 ; CHECK-MVE-NEXT: vminnm.f32 s4, s6, s4
3823 ; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s10
3824 ; CHECK-MVE-NEXT: vcvt.s32.f32 s14, s14
3825 ; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s4
3826 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
3827 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
3828 ; CHECK-MVE-NEXT: vmov r12, s16
3829 ; CHECK-MVE-NEXT: vcmp.f32 s13, s13
3830 ; CHECK-MVE-NEXT: it vs
3831 ; CHECK-MVE-NEXT: movvs.w r12, #0
3832 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
3833 ; CHECK-MVE-NEXT: vmov lr, s15
3834 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
3835 ; CHECK-MVE-NEXT: it vs
3836 ; CHECK-MVE-NEXT: movvs.w lr, #0
3837 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
3838 ; CHECK-MVE-NEXT: vmov r2, s11
3839 ; CHECK-MVE-NEXT: vcmp.f32 s7, s7
3840 ; CHECK-MVE-NEXT: it vs
3841 ; CHECK-MVE-NEXT: movvs r2, #0
3842 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
3843 ; CHECK-MVE-NEXT: vmov r3, s9
3844 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
3845 ; CHECK-MVE-NEXT: it vs
3846 ; CHECK-MVE-NEXT: movvs r3, #0
3847 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
3848 ; CHECK-MVE-NEXT: vmov r0, s5
3849 ; CHECK-MVE-NEXT: vcmp.f32 s12, s12
3850 ; CHECK-MVE-NEXT: it vs
3851 ; CHECK-MVE-NEXT: movvs r0, #0
3852 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
3853 ; CHECK-MVE-NEXT: vmov r1, s14
3854 ; CHECK-MVE-NEXT: vmov r4, s10
3855 ; CHECK-MVE-NEXT: it vs
3856 ; CHECK-MVE-NEXT: movvs r1, #0
3857 ; CHECK-MVE-NEXT: vcmp.f32 s8, s8
3858 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
3859 ; CHECK-MVE-NEXT: it vs
3860 ; CHECK-MVE-NEXT: movvs r4, #0
3861 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
3862 ; CHECK-MVE-NEXT: vmov.16 q0[0], r4
3863 ; CHECK-MVE-NEXT: vmov r5, s4
3864 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
3865 ; CHECK-MVE-NEXT: it vs
3866 ; CHECK-MVE-NEXT: movvs r5, #0
3867 ; CHECK-MVE-NEXT: vmov.16 q0[1], r5
3868 ; CHECK-MVE-NEXT: vmov.16 q0[2], r0
3869 ; CHECK-MVE-NEXT: vmov.16 q0[3], r1
3870 ; CHECK-MVE-NEXT: vmov.16 q0[4], r2
3871 ; CHECK-MVE-NEXT: vmov.16 q0[5], r3
3872 ; CHECK-MVE-NEXT: vmov.16 q0[6], r12
3873 ; CHECK-MVE-NEXT: vmov.16 q0[7], lr
3874 ; CHECK-MVE-NEXT: vpop {d8}
3875 ; CHECK-MVE-NEXT: pop {r4, r5, r7, pc}
3876 ; CHECK-MVE-NEXT: .p2align 2
3877 ; CHECK-MVE-NEXT: @ %bb.1:
3878 ; CHECK-MVE-NEXT: .LCPI43_0:
3879 ; CHECK-MVE-NEXT: .long 0x42fe0000 @ float 127
3880 ; CHECK-MVE-NEXT: .LCPI43_1:
3881 ; CHECK-MVE-NEXT: .long 0xc3000000 @ float -128
3882 ;
3883 ; CHECK-MVEFP-LABEL: test_signed_v8f16_v8i8:
3884 ; CHECK-MVEFP: @ %bb.0:
3885 ; CHECK-MVEFP-NEXT: vcvt.s16.f16 q0, q0
3886 ; CHECK-MVEFP-NEXT: vqmovnb.s16 q0, q0
3887 ; CHECK-MVEFP-NEXT: vmovlb.s8 q0, q0
3888 ; CHECK-MVEFP-NEXT: bx lr
3889 %x = call <8 x i8> @llvm.fptosi.sat.v8f16.v8i8(<8 x half> %f)
3890 ret <8 x i8> %x
3891 }
3893 define arm_aapcs_vfpcc <8 x i13> @test_signed_v8f16_v8i13(<8 x half> %f) {
3894 ; CHECK-MVE-LABEL: test_signed_v8f16_v8i13:
3895 ; CHECK-MVE: @ %bb.0:
3896 ; CHECK-MVE-NEXT: .save {r4, r5, r7, lr}
3897 ; CHECK-MVE-NEXT: push {r4, r5, r7, lr}
3898 ; CHECK-MVE-NEXT: .vsave {d8}
3899 ; CHECK-MVE-NEXT: vpush {d8}
3900 ; CHECK-MVE-NEXT: vldr s6, .LCPI44_1
3901 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s13, s3
3902 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s3, s3
3903 ; CHECK-MVE-NEXT: vldr s4, .LCPI44_0
3904 ; CHECK-MVE-NEXT: vmaxnm.f32 s16, s3, s6
3905 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s7, s2
3906 ; CHECK-MVE-NEXT: vmaxnm.f32 s15, s13, s6
3907 ; CHECK-MVE-NEXT: vminnm.f32 s16, s16, s4
3908 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s2
3909 ; CHECK-MVE-NEXT: vminnm.f32 s15, s15, s4
3910 ; CHECK-MVE-NEXT: vmaxnm.f32 s11, s2, s6
3911 ; CHECK-MVE-NEXT: vcvt.s32.f32 s16, s16
3912 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s12, s1
3913 ; CHECK-MVE-NEXT: vmaxnm.f32 s9, s7, s6
3914 ; CHECK-MVE-NEXT: vminnm.f32 s11, s11, s4
3915 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s1, s1
3916 ; CHECK-MVE-NEXT: vcvt.s32.f32 s15, s15
3917 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s8, s0
3918 ; CHECK-MVE-NEXT: vmaxnm.f32 s5, s1, s6
3919 ; CHECK-MVE-NEXT: vminnm.f32 s9, s9, s4
3920 ; CHECK-MVE-NEXT: vcvt.s32.f32 s11, s11
3921 ; CHECK-MVE-NEXT: vmaxnm.f32 s10, s8, s6
3922 ; CHECK-MVE-NEXT: vmaxnm.f32 s14, s12, s6
3923 ; CHECK-MVE-NEXT: vminnm.f32 s5, s5, s4
3924 ; CHECK-MVE-NEXT: vcvt.s32.f32 s9, s9
3925 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s0, s0
3926 ; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s4
3927 ; CHECK-MVE-NEXT: vminnm.f32 s14, s14, s4
3928 ; CHECK-MVE-NEXT: vcvt.s32.f32 s5, s5
3929 ; CHECK-MVE-NEXT: vmaxnm.f32 s6, s0, s6
3930 ; CHECK-MVE-NEXT: vminnm.f32 s4, s6, s4
3931 ; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s10
3932 ; CHECK-MVE-NEXT: vcvt.s32.f32 s14, s14
3933 ; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s4
3934 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
3935 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
3936 ; CHECK-MVE-NEXT: vmov r12, s16
3937 ; CHECK-MVE-NEXT: vcmp.f32 s13, s13
3938 ; CHECK-MVE-NEXT: it vs
3939 ; CHECK-MVE-NEXT: movvs.w r12, #0
3940 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
3941 ; CHECK-MVE-NEXT: vmov lr, s15
3942 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
3943 ; CHECK-MVE-NEXT: it vs
3944 ; CHECK-MVE-NEXT: movvs.w lr, #0
3945 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
3946 ; CHECK-MVE-NEXT: vmov r2, s11
3947 ; CHECK-MVE-NEXT: vcmp.f32 s7, s7
3948 ; CHECK-MVE-NEXT: it vs
3949 ; CHECK-MVE-NEXT: movvs r2, #0
3950 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
3951 ; CHECK-MVE-NEXT: vmov r3, s9
3952 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
3953 ; CHECK-MVE-NEXT: it vs
3954 ; CHECK-MVE-NEXT: movvs r3, #0
3955 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
3956 ; CHECK-MVE-NEXT: vmov r0, s5
3957 ; CHECK-MVE-NEXT: vcmp.f32 s12, s12
3958 ; CHECK-MVE-NEXT: it vs
3959 ; CHECK-MVE-NEXT: movvs r0, #0
3960 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
3961 ; CHECK-MVE-NEXT: vmov r1, s14
3962 ; CHECK-MVE-NEXT: vmov r4, s10
3963 ; CHECK-MVE-NEXT: it vs
3964 ; CHECK-MVE-NEXT: movvs r1, #0
3965 ; CHECK-MVE-NEXT: vcmp.f32 s8, s8
3966 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
3967 ; CHECK-MVE-NEXT: it vs
3968 ; CHECK-MVE-NEXT: movvs r4, #0
3969 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
3970 ; CHECK-MVE-NEXT: vmov.16 q0[0], r4
3971 ; CHECK-MVE-NEXT: vmov r5, s4
3972 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
3973 ; CHECK-MVE-NEXT: it vs
3974 ; CHECK-MVE-NEXT: movvs r5, #0
3975 ; CHECK-MVE-NEXT: vmov.16 q0[1], r5
3976 ; CHECK-MVE-NEXT: vmov.16 q0[2], r0
3977 ; CHECK-MVE-NEXT: vmov.16 q0[3], r1
3978 ; CHECK-MVE-NEXT: vmov.16 q0[4], r2
3979 ; CHECK-MVE-NEXT: vmov.16 q0[5], r3
3980 ; CHECK-MVE-NEXT: vmov.16 q0[6], r12
3981 ; CHECK-MVE-NEXT: vmov.16 q0[7], lr
3982 ; CHECK-MVE-NEXT: vpop {d8}
3983 ; CHECK-MVE-NEXT: pop {r4, r5, r7, pc}
3984 ; CHECK-MVE-NEXT: .p2align 2
3985 ; CHECK-MVE-NEXT: @ %bb.1:
3986 ; CHECK-MVE-NEXT: .LCPI44_0:
3987 ; CHECK-MVE-NEXT: .long 0x457ff000 @ float 4095
3988 ; CHECK-MVE-NEXT: .LCPI44_1:
3989 ; CHECK-MVE-NEXT: .long 0xc5800000 @ float -4096
3990 ;
3991 ; CHECK-MVEFP-LABEL: test_signed_v8f16_v8i13:
3992 ; CHECK-MVEFP: @ %bb.0:
3993 ; CHECK-MVEFP-NEXT: vmvn.i16 q1, #0xf000
3994 ; CHECK-MVEFP-NEXT: vcvt.s16.f16 q0, q0
3995 ; CHECK-MVEFP-NEXT: vmov.i16 q2, #0xf000
3996 ; CHECK-MVEFP-NEXT: vmin.s16 q0, q0, q1
3997 ; CHECK-MVEFP-NEXT: vmax.s16 q0, q0, q2
3998 ; CHECK-MVEFP-NEXT: bx lr
3999 %x = call <8 x i13> @llvm.fptosi.sat.v8f16.v8i13(<8 x half> %f)
4000 ret <8 x i13> %x
4001 }
4003 define arm_aapcs_vfpcc <8 x i16> @test_signed_v8f16_v8i16(<8 x half> %f) {
4004 ; CHECK-MVE-LABEL: test_signed_v8f16_v8i16:
4005 ; CHECK-MVE: @ %bb.0:
4006 ; CHECK-MVE-NEXT: .save {r4, r5, r7, lr}
4007 ; CHECK-MVE-NEXT: push {r4, r5, r7, lr}
4008 ; CHECK-MVE-NEXT: .vsave {d8}
4009 ; CHECK-MVE-NEXT: vpush {d8}
4010 ; CHECK-MVE-NEXT: vldr s6, .LCPI45_1
4011 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s13, s3
4012 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s3, s3
4013 ; CHECK-MVE-NEXT: vldr s4, .LCPI45_0
4014 ; CHECK-MVE-NEXT: vmaxnm.f32 s16, s3, s6
4015 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s7, s2
4016 ; CHECK-MVE-NEXT: vmaxnm.f32 s15, s13, s6
4017 ; CHECK-MVE-NEXT: vminnm.f32 s16, s16, s4
4018 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s2
4019 ; CHECK-MVE-NEXT: vminnm.f32 s15, s15, s4
4020 ; CHECK-MVE-NEXT: vmaxnm.f32 s11, s2, s6
4021 ; CHECK-MVE-NEXT: vcvt.s32.f32 s16, s16
4022 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s12, s1
4023 ; CHECK-MVE-NEXT: vmaxnm.f32 s9, s7, s6
4024 ; CHECK-MVE-NEXT: vminnm.f32 s11, s11, s4
4025 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s1, s1
4026 ; CHECK-MVE-NEXT: vcvt.s32.f32 s15, s15
4027 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s8, s0
4028 ; CHECK-MVE-NEXT: vmaxnm.f32 s5, s1, s6
4029 ; CHECK-MVE-NEXT: vminnm.f32 s9, s9, s4
4030 ; CHECK-MVE-NEXT: vcvt.s32.f32 s11, s11
4031 ; CHECK-MVE-NEXT: vmaxnm.f32 s10, s8, s6
4032 ; CHECK-MVE-NEXT: vmaxnm.f32 s14, s12, s6
4033 ; CHECK-MVE-NEXT: vminnm.f32 s5, s5, s4
4034 ; CHECK-MVE-NEXT: vcvt.s32.f32 s9, s9
4035 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s0, s0
4036 ; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s4
4037 ; CHECK-MVE-NEXT: vminnm.f32 s14, s14, s4
4038 ; CHECK-MVE-NEXT: vcvt.s32.f32 s5, s5
4039 ; CHECK-MVE-NEXT: vmaxnm.f32 s6, s0, s6
4040 ; CHECK-MVE-NEXT: vminnm.f32 s4, s6, s4
4041 ; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s10
4042 ; CHECK-MVE-NEXT: vcvt.s32.f32 s14, s14
4043 ; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s4
4044 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
4045 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
4046 ; CHECK-MVE-NEXT: vmov r12, s16
4047 ; CHECK-MVE-NEXT: vcmp.f32 s13, s13
4048 ; CHECK-MVE-NEXT: it vs
4049 ; CHECK-MVE-NEXT: movvs.w r12, #0
4050 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
4051 ; CHECK-MVE-NEXT: vmov lr, s15
4052 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
4053 ; CHECK-MVE-NEXT: it vs
4054 ; CHECK-MVE-NEXT: movvs.w lr, #0
4055 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
4056 ; CHECK-MVE-NEXT: vmov r2, s11
4057 ; CHECK-MVE-NEXT: vcmp.f32 s7, s7
4058 ; CHECK-MVE-NEXT: it vs
4059 ; CHECK-MVE-NEXT: movvs r2, #0
4060 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
4061 ; CHECK-MVE-NEXT: vmov r3, s9
4062 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
4063 ; CHECK-MVE-NEXT: it vs
4064 ; CHECK-MVE-NEXT: movvs r3, #0
4065 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
4066 ; CHECK-MVE-NEXT: vmov r0, s5
4067 ; CHECK-MVE-NEXT: vcmp.f32 s12, s12
4068 ; CHECK-MVE-NEXT: it vs
4069 ; CHECK-MVE-NEXT: movvs r0, #0
4070 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
4071 ; CHECK-MVE-NEXT: vmov r1, s14
4072 ; CHECK-MVE-NEXT: vmov r4, s10
4073 ; CHECK-MVE-NEXT: it vs
4074 ; CHECK-MVE-NEXT: movvs r1, #0
4075 ; CHECK-MVE-NEXT: vcmp.f32 s8, s8
4076 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
4077 ; CHECK-MVE-NEXT: it vs
4078 ; CHECK-MVE-NEXT: movvs r4, #0
4079 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
4080 ; CHECK-MVE-NEXT: vmov.16 q0[0], r4
4081 ; CHECK-MVE-NEXT: vmov r5, s4
4082 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
4083 ; CHECK-MVE-NEXT: it vs
4084 ; CHECK-MVE-NEXT: movvs r5, #0
4085 ; CHECK-MVE-NEXT: vmov.16 q0[1], r5
4086 ; CHECK-MVE-NEXT: vmov.16 q0[2], r0
4087 ; CHECK-MVE-NEXT: vmov.16 q0[3], r1
4088 ; CHECK-MVE-NEXT: vmov.16 q0[4], r2
4089 ; CHECK-MVE-NEXT: vmov.16 q0[5], r3
4090 ; CHECK-MVE-NEXT: vmov.16 q0[6], r12
4091 ; CHECK-MVE-NEXT: vmov.16 q0[7], lr
4092 ; CHECK-MVE-NEXT: vpop {d8}
4093 ; CHECK-MVE-NEXT: pop {r4, r5, r7, pc}
4094 ; CHECK-MVE-NEXT: .p2align 2
4095 ; CHECK-MVE-NEXT: @ %bb.1:
4096 ; CHECK-MVE-NEXT: .LCPI45_0:
4097 ; CHECK-MVE-NEXT: .long 0x46fffe00 @ float 32767
4098 ; CHECK-MVE-NEXT: .LCPI45_1:
4099 ; CHECK-MVE-NEXT: .long 0xc7000000 @ float -32768
4100 ;
4101 ; CHECK-MVEFP-LABEL: test_signed_v8f16_v8i16:
4102 ; CHECK-MVEFP: @ %bb.0:
4103 ; CHECK-MVEFP-NEXT: vcvt.s16.f16 q0, q0
4104 ; CHECK-MVEFP-NEXT: bx lr
4105 %x = call <8 x i16> @llvm.fptosi.sat.v8f16.v8i16(<8 x half> %f)
4106 ret <8 x i16> %x
4107 }
4109 define arm_aapcs_vfpcc <8 x i19> @test_signed_v8f16_v8i19(<8 x half> %f) {
4110 ; CHECK-LABEL: test_signed_v8f16_v8i19:
4111 ; CHECK: @ %bb.0:
4112 ; CHECK-NEXT: .save {r4, r5, r7, r9, r11, lr}
4113 ; CHECK-NEXT: push.w {r4, r5, r7, r9, r11, lr}
4114 ; CHECK-NEXT: vldr s6, .LCPI46_1
4115 ; CHECK-NEXT: vcvtb.f32.f16 s12, s0
4116 ; CHECK-NEXT: vcvtt.f32.f16 s0, s0
4117 ; CHECK-NEXT: vldr s4, .LCPI46_0
4118 ; CHECK-NEXT: vmaxnm.f32 s5, s0, s6
4119 ; CHECK-NEXT: vmaxnm.f32 s14, s12, s6
4120 ; CHECK-NEXT: vminnm.f32 s5, s5, s4
4121 ; CHECK-NEXT: vcvtt.f32.f16 s8, s1
4122 ; CHECK-NEXT: vminnm.f32 s14, s14, s4
4123 ; CHECK-NEXT: vcvt.s32.f32 s5, s5
4124 ; CHECK-NEXT: vmaxnm.f32 s10, s8, s6
4125 ; CHECK-NEXT: vcvt.s32.f32 s14, s14
4126 ; CHECK-NEXT: vminnm.f32 s10, s10, s4
4127 ; CHECK-NEXT: vcvtb.f32.f16 s1, s1
4128 ; CHECK-NEXT: vcvt.s32.f32 s10, s10
4129 ; CHECK-NEXT: vmaxnm.f32 s7, s1, s6
4130 ; CHECK-NEXT: vminnm.f32 s7, s7, s4
4131 ; CHECK-NEXT: vcmp.f32 s0, s0
4132 ; CHECK-NEXT: vcvt.s32.f32 s7, s7
4133 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4134 ; CHECK-NEXT: vcmp.f32 s12, s12
4135 ; CHECK-NEXT: mov.w r7, #0
4136 ; CHECK-NEXT: vmov r2, s5
4137 ; CHECK-NEXT: vcvtb.f32.f16 s0, s2
4138 ; CHECK-NEXT: it vs
4139 ; CHECK-NEXT: movvs r2, #0
4140 ; CHECK-NEXT: vmov r1, s14
4141 ; CHECK-NEXT: bfc r2, #19, #13
4142 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4143 ; CHECK-NEXT: it vs
4144 ; CHECK-NEXT: movvs r1, #0
4145 ; CHECK-NEXT: vcmp.f32 s8, s8
4146 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4147 ; CHECK-NEXT: lsll r2, r7, #19
4148 ; CHECK-NEXT: bfc r1, #19, #13
4149 ; CHECK-NEXT: vmov r12, s10
4150 ; CHECK-NEXT: vcmp.f32 s1, s1
4151 ; CHECK-NEXT: vmaxnm.f32 s8, s0, s6
4152 ; CHECK-NEXT: orr.w r1, r1, r2
4153 ; CHECK-NEXT: str r1, [r0]
4154 ; CHECK-NEXT: it vs
4155 ; CHECK-NEXT: movvs.w r12, #0
4156 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4157 ; CHECK-NEXT: vcmp.f32 s0, s0
4158 ; CHECK-NEXT: vcvtt.f32.f16 s0, s2
4159 ; CHECK-NEXT: vmaxnm.f32 s2, s0, s6
4160 ; CHECK-NEXT: vminnm.f32 s8, s8, s4
4161 ; CHECK-NEXT: vminnm.f32 s2, s2, s4
4162 ; CHECK-NEXT: vmov r3, s7
4163 ; CHECK-NEXT: vcvt.s32.f32 s2, s2
4164 ; CHECK-NEXT: it vs
4165 ; CHECK-NEXT: movvs r3, #0
4166 ; CHECK-NEXT: vcvt.s32.f32 s8, s8
4167 ; CHECK-NEXT: bfc r3, #19, #13
4168 ; CHECK-NEXT: mov r2, r12
4169 ; CHECK-NEXT: movs r1, #0
4170 ; CHECK-NEXT: bfc r2, #19, #13
4171 ; CHECK-NEXT: mov r4, r3
4172 ; CHECK-NEXT: mov.w r9, #0
4173 ; CHECK-NEXT: lsrl r2, r1, #7
4174 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4175 ; CHECK-NEXT: vcmp.f32 s0, s0
4176 ; CHECK-NEXT: lsrl r4, r9, #26
4177 ; CHECK-NEXT: vcvtt.f32.f16 s0, s3
4178 ; CHECK-NEXT: mov lr, r1
4179 ; CHECK-NEXT: orr.w r1, r4, r2
4180 ; CHECK-NEXT: vmov r4, s2
4181 ; CHECK-NEXT: vmaxnm.f32 s2, s0, s6
4182 ; CHECK-NEXT: vmov r2, s8
4183 ; CHECK-NEXT: vminnm.f32 s2, s2, s4
4184 ; CHECK-NEXT: it vs
4185 ; CHECK-NEXT: movvs r2, #0
4186 ; CHECK-NEXT: vcvt.s32.f32 s2, s2
4187 ; CHECK-NEXT: bfc r2, #19, #13
4188 ; CHECK-NEXT: movs r5, #0
4189 ; CHECK-NEXT: lsll r2, r5, #12
4190 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4191 ; CHECK-NEXT: it vs
4192 ; CHECK-NEXT: movvs r4, #0
4193 ; CHECK-NEXT: orrs r2, r1
4194 ; CHECK-NEXT: bfc r4, #19, #13
4195 ; CHECK-NEXT: movs r1, #0
4196 ; CHECK-NEXT: lsll r4, r1, #31
4197 ; CHECK-NEXT: vcmp.f32 s0, s0
4198 ; CHECK-NEXT: orrs r2, r4
4199 ; CHECK-NEXT: str r2, [r0, #8]
4200 ; CHECK-NEXT: orr.w r2, r7, r3, lsl #6
4201 ; CHECK-NEXT: vcvtb.f32.f16 s0, s3
4202 ; CHECK-NEXT: orr.w r3, r2, r12, lsl #25
4203 ; CHECK-NEXT: vmov r2, s2
4204 ; CHECK-NEXT: vmaxnm.f32 s2, s0, s6
4205 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4206 ; CHECK-NEXT: vminnm.f32 s2, s2, s4
4207 ; CHECK-NEXT: it vs
4208 ; CHECK-NEXT: movvs r2, #0
4209 ; CHECK-NEXT: vcvt.s32.f32 s2, s2
4210 ; CHECK-NEXT: bfc r2, #19, #13
4211 ; CHECK-NEXT: movs r7, #0
4212 ; CHECK-NEXT: vcmp.f32 s0, s0
4213 ; CHECK-NEXT: lsll r2, r7, #5
4214 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4215 ; CHECK-NEXT: mov.w r11, #0
4216 ; CHECK-NEXT: vmov r7, s2
4217 ; CHECK-NEXT: it vs
4218 ; CHECK-NEXT: movvs r7, #0
4219 ; CHECK-NEXT: mov r4, r7
4220 ; CHECK-NEXT: bfc r4, #19, #13
4221 ; CHECK-NEXT: lsrl r4, r11, #14
4222 ; CHECK-NEXT: orrs r2, r4
4223 ; CHECK-NEXT: strh r2, [r0, #16]
4224 ; CHECK-NEXT: str r3, [r0, #4]
4225 ; CHECK-NEXT: lsrs r2, r2, #16
4226 ; CHECK-NEXT: strb r2, [r0, #18]
4227 ; CHECK-NEXT: orr.w r2, r9, lr
4228 ; CHECK-NEXT: orrs r2, r5
4229 ; CHECK-NEXT: orrs r1, r2
4230 ; CHECK-NEXT: orr.w r1, r1, r7, lsl #18
4231 ; CHECK-NEXT: str r1, [r0, #12]
4232 ; CHECK-NEXT: pop.w {r4, r5, r7, r9, r11, pc}
4233 ; CHECK-NEXT: .p2align 2
4234 ; CHECK-NEXT: @ %bb.1:
4235 ; CHECK-NEXT: .LCPI46_0:
4236 ; CHECK-NEXT: .long 0x487fffc0 @ float 262143
4237 ; CHECK-NEXT: .LCPI46_1:
4238 ; CHECK-NEXT: .long 0xc8800000 @ float -262144
4239 %x = call <8 x i19> @llvm.fptosi.sat.v8f16.v8i19(<8 x half> %f)
4240 ret <8 x i19> %x
4241 }
4243 define arm_aapcs_vfpcc <8 x i32> @test_signed_v8f16_v8i32_duplicate(<8 x half> %f) {
4244 ; CHECK-LABEL: test_signed_v8f16_v8i32_duplicate:
4245 ; CHECK: @ %bb.0:
4246 ; CHECK-NEXT: vmovx.f16 s4, s3
4247 ; CHECK-NEXT: vmovx.f16 s6, s0
4248 ; CHECK-NEXT: vcvt.s32.f16 s8, s4
4249 ; CHECK-NEXT: vmovx.f16 s4, s2
4250 ; CHECK-NEXT: vcvt.s32.f16 s10, s4
4251 ; CHECK-NEXT: vmovx.f16 s4, s1
4252 ; CHECK-NEXT: vcvt.s32.f16 s14, s2
4253 ; CHECK-NEXT: vcvt.s32.f16 s2, s1
4254 ; CHECK-NEXT: vcvt.s32.f16 s0, s0
4255 ; CHECK-NEXT: vcvt.s32.f16 s4, s4
4256 ; CHECK-NEXT: vcvt.s32.f16 s6, s6
4257 ; CHECK-NEXT: vmov r0, s2
4258 ; CHECK-NEXT: vmov r1, s0
4259 ; CHECK-NEXT: vcvt.s32.f16 s12, s3
4260 ; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
4261 ; CHECK-NEXT: vmov r0, s4
4262 ; CHECK-NEXT: vmov r1, s6
4263 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
4264 ; CHECK-NEXT: vmov r0, s12
4265 ; CHECK-NEXT: vmov r1, s14
4266 ; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
4267 ; CHECK-NEXT: vmov r0, s8
4268 ; CHECK-NEXT: vmov r1, s10
4269 ; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
4270 ; CHECK-NEXT: bx lr
4271 %x = call <8 x i32> @llvm.fptosi.sat.v8f16.v8i32(<8 x half> %f)
4272 ret <8 x i32> %x
4273 }
4275 define arm_aapcs_vfpcc <8 x i50> @test_signed_v8f16_v8i50(<8 x half> %f) {
4276 ; CHECK-LABEL: test_signed_v8f16_v8i50:
4277 ; CHECK: @ %bb.0:
4278 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
4279 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
4280 ; CHECK-NEXT: .pad #4
4281 ; CHECK-NEXT: sub sp, #4
4282 ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
4283 ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
4284 ; CHECK-NEXT: .pad #24
4285 ; CHECK-NEXT: sub sp, #24
4286 ; CHECK-NEXT: vmov q4, q0
4287 ; CHECK-NEXT: mov r4, r0
4288 ; CHECK-NEXT: vcvtt.f32.f16 s24, s16
4289 ; CHECK-NEXT: vmov r0, s24
4290 ; CHECK-NEXT: bl __aeabi_f2lz
4291 ; CHECK-NEXT: vcvtb.f32.f16 s26, s17
4292 ; CHECK-NEXT: mov r2, r0
4293 ; CHECK-NEXT: vmov r0, s26
4294 ; CHECK-NEXT: vldr s22, .LCPI48_0
4295 ; CHECK-NEXT: vldr s20, .LCPI48_1
4296 ; CHECK-NEXT: vcmp.f32 s24, s22
4297 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4298 ; CHECK-NEXT: itt lt
4299 ; CHECK-NEXT: movlt r1, #0
4300 ; CHECK-NEXT: movtlt r1, #65534
4301 ; CHECK-NEXT: it lt
4302 ; CHECK-NEXT: movlt r2, #0
4303 ; CHECK-NEXT: vcmp.f32 s24, s20
4304 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4305 ; CHECK-NEXT: it gt
4306 ; CHECK-NEXT: movgt.w r2, #-1
4307 ; CHECK-NEXT: vcmp.f32 s24, s24
4308 ; CHECK-NEXT: itt gt
4309 ; CHECK-NEXT: movwgt r1, #65535
4310 ; CHECK-NEXT: movtgt r1, #1
4311 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4312 ; CHECK-NEXT: it vs
4313 ; CHECK-NEXT: movvs r2, #0
4314 ; CHECK-NEXT: str r2, [sp, #20] @ 4-byte Spill
4315 ; CHECK-NEXT: it vs
4316 ; CHECK-NEXT: movvs r1, #0
4317 ; CHECK-NEXT: str r1, [sp, #16] @ 4-byte Spill
4318 ; CHECK-NEXT: bl __aeabi_f2lz
4319 ; CHECK-NEXT: vcvtt.f32.f16 s24, s17
4320 ; CHECK-NEXT: mov r2, r0
4321 ; CHECK-NEXT: vmov r0, s24
4322 ; CHECK-NEXT: vcmp.f32 s26, s22
4323 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4324 ; CHECK-NEXT: itt lt
4325 ; CHECK-NEXT: movlt r1, #0
4326 ; CHECK-NEXT: movtlt r1, #65534
4327 ; CHECK-NEXT: vcmp.f32 s26, s20
4328 ; CHECK-NEXT: it lt
4329 ; CHECK-NEXT: movlt r2, #0
4330 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4331 ; CHECK-NEXT: itt gt
4332 ; CHECK-NEXT: movwgt r1, #65535
4333 ; CHECK-NEXT: movtgt r1, #1
4334 ; CHECK-NEXT: it gt
4335 ; CHECK-NEXT: movgt.w r2, #-1
4336 ; CHECK-NEXT: vcmp.f32 s26, s26
4337 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4338 ; CHECK-NEXT: it vs
4339 ; CHECK-NEXT: movvs r2, #0
4340 ; CHECK-NEXT: str r2, [sp, #12] @ 4-byte Spill
4341 ; CHECK-NEXT: it vs
4342 ; CHECK-NEXT: movvs r1, #0
4343 ; CHECK-NEXT: str r1, [sp, #8] @ 4-byte Spill
4344 ; CHECK-NEXT: bl __aeabi_f2lz
4345 ; CHECK-NEXT: vcvtb.f32.f16 s26, s18
4346 ; CHECK-NEXT: mov r2, r0
4347 ; CHECK-NEXT: vmov r0, s26
4348 ; CHECK-NEXT: vcmp.f32 s24, s22
4349 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4350 ; CHECK-NEXT: itt lt
4351 ; CHECK-NEXT: movlt r1, #0
4352 ; CHECK-NEXT: movtlt r1, #65534
4353 ; CHECK-NEXT: vcmp.f32 s24, s20
4354 ; CHECK-NEXT: it lt
4355 ; CHECK-NEXT: movlt r2, #0
4356 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4357 ; CHECK-NEXT: itt gt
4358 ; CHECK-NEXT: movwgt r1, #65535
4359 ; CHECK-NEXT: movtgt r1, #1
4360 ; CHECK-NEXT: it gt
4361 ; CHECK-NEXT: movgt.w r2, #-1
4362 ; CHECK-NEXT: vcmp.f32 s24, s24
4363 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4364 ; CHECK-NEXT: it vs
4365 ; CHECK-NEXT: movvs r2, #0
4366 ; CHECK-NEXT: str r2, [sp, #4] @ 4-byte Spill
4367 ; CHECK-NEXT: it vs
4368 ; CHECK-NEXT: movvs r1, #0
4369 ; CHECK-NEXT: str r1, [sp] @ 4-byte Spill
4370 ; CHECK-NEXT: bl __aeabi_f2lz
4371 ; CHECK-NEXT: vcmp.f32 s26, s22
4372 ; CHECK-NEXT: mov r6, r1
4373 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4374 ; CHECK-NEXT: ittt lt
4375 ; CHECK-NEXT: movlt r0, #0
4376 ; CHECK-NEXT: movlt r6, #0
4377 ; CHECK-NEXT: movtlt r6, #65534
4378 ; CHECK-NEXT: vcmp.f32 s26, s20
4379 ; CHECK-NEXT: vcvtt.f32.f16 s18, s18
4380 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4381 ; CHECK-NEXT: ittt gt
4382 ; CHECK-NEXT: movwgt r6, #65535
4383 ; CHECK-NEXT: movtgt r6, #1
4384 ; CHECK-NEXT: movgt.w r0, #-1
4385 ; CHECK-NEXT: vcmp.f32 s26, s26
4386 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4387 ; CHECK-NEXT: it vs
4388 ; CHECK-NEXT: movvs r0, #0
4389 ; CHECK-NEXT: str.w r0, [r4, #25]
4390 ; CHECK-NEXT: vmov r0, s18
4391 ; CHECK-NEXT: it vs
4392 ; CHECK-NEXT: movvs r6, #0
4393 ; CHECK-NEXT: bl __aeabi_f2lz
4394 ; CHECK-NEXT: vcmp.f32 s18, s22
4395 ; CHECK-NEXT: mov r8, r0
4396 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4397 ; CHECK-NEXT: mov r9, r1
4398 ; CHECK-NEXT: vcmp.f32 s18, s20
4399 ; CHECK-NEXT: ittt lt
4400 ; CHECK-NEXT: movwlt r9, #0
4401 ; CHECK-NEXT: movtlt r9, #65534
4402 ; CHECK-NEXT: movlt.w r8, #0
4403 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4404 ; CHECK-NEXT: vcmp.f32 s18, s18
4405 ; CHECK-NEXT: vcvtb.f32.f16 s18, s19
4406 ; CHECK-NEXT: ittt gt
4407 ; CHECK-NEXT: movgt.w r8, #-1
4408 ; CHECK-NEXT: movwgt r9, #65535
4409 ; CHECK-NEXT: movtgt r9, #1
4410 ; CHECK-NEXT: vmov r0, s18
4411 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4412 ; CHECK-NEXT: itt vs
4413 ; CHECK-NEXT: movvs.w r8, #0
4414 ; CHECK-NEXT: movvs.w r9, #0
4415 ; CHECK-NEXT: bl __aeabi_f2lz
4416 ; CHECK-NEXT: vcmp.f32 s18, s22
4417 ; CHECK-NEXT: mov r11, r0
4418 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4419 ; CHECK-NEXT: mov r5, r1
4420 ; CHECK-NEXT: vcmp.f32 s18, s20
4421 ; CHECK-NEXT: ittt lt
4422 ; CHECK-NEXT: movlt r5, #0
4423 ; CHECK-NEXT: movtlt r5, #65534
4424 ; CHECK-NEXT: movlt.w r11, #0
4425 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4426 ; CHECK-NEXT: vcmp.f32 s18, s18
4427 ; CHECK-NEXT: vcvtt.f32.f16 s18, s19
4428 ; CHECK-NEXT: ittt gt
4429 ; CHECK-NEXT: movgt.w r11, #-1
4430 ; CHECK-NEXT: movwgt r5, #65535
4431 ; CHECK-NEXT: movtgt r5, #1
4432 ; CHECK-NEXT: vmov r0, s18
4433 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4434 ; CHECK-NEXT: itt vs
4435 ; CHECK-NEXT: movvs.w r11, #0
4436 ; CHECK-NEXT: movvs r5, #0
4437 ; CHECK-NEXT: bl __aeabi_f2lz
4438 ; CHECK-NEXT: vcvtb.f32.f16 s16, s16
4439 ; CHECK-NEXT: mov r10, r0
4440 ; CHECK-NEXT: vmov r0, s16
4441 ; CHECK-NEXT: mov r7, r1
4442 ; CHECK-NEXT: vcmp.f32 s18, s22
4443 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4444 ; CHECK-NEXT: ittt lt
4445 ; CHECK-NEXT: movlt r7, #0
4446 ; CHECK-NEXT: movtlt r7, #65534
4447 ; CHECK-NEXT: movlt.w r10, #0
4448 ; CHECK-NEXT: vcmp.f32 s18, s20
4449 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4450 ; CHECK-NEXT: ittt gt
4451 ; CHECK-NEXT: movgt.w r10, #-1
4452 ; CHECK-NEXT: movwgt r7, #65535
4453 ; CHECK-NEXT: movtgt r7, #1
4454 ; CHECK-NEXT: vcmp.f32 s18, s18
4455 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4456 ; CHECK-NEXT: itt vs
4457 ; CHECK-NEXT: movvs.w r10, #0
4458 ; CHECK-NEXT: movvs r7, #0
4459 ; CHECK-NEXT: bl __aeabi_f2lz
4460 ; CHECK-NEXT: vcmp.f32 s16, s22
4461 ; CHECK-NEXT: bfc r5, #18, #14
4462 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4463 ; CHECK-NEXT: ittt lt
4464 ; CHECK-NEXT: movlt r0, #0
4465 ; CHECK-NEXT: movlt r1, #0
4466 ; CHECK-NEXT: movtlt r1, #65534
4467 ; CHECK-NEXT: vcmp.f32 s16, s20
4468 ; CHECK-NEXT: mov r2, r11
4469 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4470 ; CHECK-NEXT: ittt gt
4471 ; CHECK-NEXT: movwgt r1, #65535
4472 ; CHECK-NEXT: movtgt r1, #1
4473 ; CHECK-NEXT: movgt.w r0, #-1
4474 ; CHECK-NEXT: vcmp.f32 s16, s16
4475 ; CHECK-NEXT: lsrl r2, r5, #28
4476 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4477 ; CHECK-NEXT: it vs
4478 ; CHECK-NEXT: movvs r0, #0
4479 ; CHECK-NEXT: str r0, [r4]
4480 ; CHECK-NEXT: lsr.w r0, r7, #10
4481 ; CHECK-NEXT: bfc r7, #18, #14
4482 ; CHECK-NEXT: bfc r9, #18, #14
4483 ; CHECK-NEXT: lsll r10, r7, #22
4484 ; CHECK-NEXT: bfc r6, #18, #14
4485 ; CHECK-NEXT: orr.w r3, r5, r7
4486 ; CHECK-NEXT: str.w r3, [r4, #45]
4487 ; CHECK-NEXT: orr.w r2, r2, r10
4488 ; CHECK-NEXT: str.w r2, [r4, #41]
4489 ; CHECK-NEXT: strb.w r0, [r4, #49]
4490 ; CHECK-NEXT: mov r0, r8
4491 ; CHECK-NEXT: lsrl r0, r9, #14
4492 ; CHECK-NEXT: orr.w r2, r9, r11, lsl #4
4493 ; CHECK-NEXT: str.w r2, [r4, #37]
4494 ; CHECK-NEXT: str.w r0, [r4, #33]
4495 ; CHECK-NEXT: orr.w r0, r6, r8, lsl #18
4496 ; CHECK-NEXT: str.w r0, [r4, #29]
4497 ; CHECK-NEXT: ldr r3, [sp] @ 4-byte Reload
4498 ; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
4499 ; CHECK-NEXT: ldr r6, [sp, #12] @ 4-byte Reload
4500 ; CHECK-NEXT: lsr.w r5, r3, #10
4501 ; CHECK-NEXT: bfc r3, #18, #14
4502 ; CHECK-NEXT: lsll r0, r3, #22
4503 ; CHECK-NEXT: mov r7, r3
4504 ; CHECK-NEXT: ldr r3, [sp, #8] @ 4-byte Reload
4505 ; CHECK-NEXT: mov r2, r6
4506 ; CHECK-NEXT: bfc r3, #18, #14
4507 ; CHECK-NEXT: lsrl r2, r3, #28
4508 ; CHECK-NEXT: orr.w r3, r3, r7
4509 ; CHECK-NEXT: str r3, [r4, #20]
4510 ; CHECK-NEXT: orr.w r2, r2, r0
4511 ; CHECK-NEXT: str r2, [r4, #16]
4512 ; CHECK-NEXT: strb r5, [r4, #24]
4513 ; CHECK-NEXT: ldr r3, [sp, #16] @ 4-byte Reload
4514 ; CHECK-NEXT: ldr r7, [sp, #20] @ 4-byte Reload
4515 ; CHECK-NEXT: bfc r3, #18, #14
4516 ; CHECK-NEXT: mov r0, r7
4517 ; CHECK-NEXT: lsrl r0, r3, #14
4518 ; CHECK-NEXT: orr.w r2, r3, r6, lsl #4
4519 ; CHECK-NEXT: strd r0, r2, [r4, #8]
4520 ; CHECK-NEXT: it vs
4521 ; CHECK-NEXT: movvs r1, #0
4522 ; CHECK-NEXT: bfc r1, #18, #14
4523 ; CHECK-NEXT: orr.w r0, r1, r7, lsl #18
4524 ; CHECK-NEXT: str r0, [r4, #4]
4525 ; CHECK-NEXT: add sp, #24
4526 ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
4527 ; CHECK-NEXT: add sp, #4
4528 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
4529 ; CHECK-NEXT: .p2align 2
4530 ; CHECK-NEXT: @ %bb.1:
4531 ; CHECK-NEXT: .LCPI48_0:
4532 ; CHECK-NEXT: .long 0xd8000000 @ float -5.62949953E+14
4533 ; CHECK-NEXT: .LCPI48_1:
4534 ; CHECK-NEXT: .long 0x57ffffff @ float 5.6294992E+14
4535 %x = call <8 x i50> @llvm.fptosi.sat.v8f16.v8i50(<8 x half> %f)
4536 ret <8 x i50> %x
4537 }
4539 define arm_aapcs_vfpcc <8 x i64> @test_signed_v8f16_v8i64(<8 x half> %f) {
4540 ; CHECK-LABEL: test_signed_v8f16_v8i64:
4541 ; CHECK: @ %bb.0:
4542 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
4543 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
4544 ; CHECK-NEXT: .pad #4
4545 ; CHECK-NEXT: sub sp, #4
4546 ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
4547 ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
4548 ; CHECK-NEXT: vmov q4, q0
4549 ; CHECK-NEXT: vcvtt.f32.f16 s24, s19
4550 ; CHECK-NEXT: vmov r0, s24
4551 ; CHECK-NEXT: bl __aeabi_f2lz
4552 ; CHECK-NEXT: vcvtb.f32.f16 s26, s19
4553 ; CHECK-NEXT: mov r9, r0
4554 ; CHECK-NEXT: vmov r0, s26
4555 ; CHECK-NEXT: vldr s28, .LCPI49_0
4556 ; CHECK-NEXT: vldr s30, .LCPI49_1
4557 ; CHECK-NEXT: mov r8, r1
4558 ; CHECK-NEXT: vcmp.f32 s24, s28
4559 ; CHECK-NEXT: vcvtt.f32.f16 s20, s16
4560 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4561 ; CHECK-NEXT: itt lt
4562 ; CHECK-NEXT: movlt.w r8, #-2147483648
4563 ; CHECK-NEXT: movlt.w r9, #0
4564 ; CHECK-NEXT: vcmp.f32 s24, s30
4565 ; CHECK-NEXT: vcvtt.f32.f16 s22, s18
4566 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4567 ; CHECK-NEXT: itt gt
4568 ; CHECK-NEXT: movgt.w r9, #-1
4569 ; CHECK-NEXT: mvngt r8, #-2147483648
4570 ; CHECK-NEXT: vcmp.f32 s24, s24
4571 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4572 ; CHECK-NEXT: vmov r6, s20
4573 ; CHECK-NEXT: vmov r4, s22
4574 ; CHECK-NEXT: itt vs
4575 ; CHECK-NEXT: movvs.w r8, #0
4576 ; CHECK-NEXT: movvs.w r9, #0
4577 ; CHECK-NEXT: bl __aeabi_f2lz
4578 ; CHECK-NEXT: mov r10, r0
4579 ; CHECK-NEXT: vcmp.f32 s26, s28
4580 ; CHECK-NEXT: mov r11, r1
4581 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4582 ; CHECK-NEXT: itt lt
4583 ; CHECK-NEXT: movlt.w r10, #0
4584 ; CHECK-NEXT: movlt.w r11, #-2147483648
4585 ; CHECK-NEXT: vcmp.f32 s26, s30
4586 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4587 ; CHECK-NEXT: mov r0, r4
4588 ; CHECK-NEXT: itt gt
4589 ; CHECK-NEXT: mvngt r11, #-2147483648
4590 ; CHECK-NEXT: movgt.w r10, #-1
4591 ; CHECK-NEXT: vcmp.f32 s26, s26
4592 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4593 ; CHECK-NEXT: itt vs
4594 ; CHECK-NEXT: movvs.w r10, #0
4595 ; CHECK-NEXT: movvs.w r11, #0
4596 ; CHECK-NEXT: bl __aeabi_f2lz
4597 ; CHECK-NEXT: mov r5, r0
4598 ; CHECK-NEXT: vcmp.f32 s22, s28
4599 ; CHECK-NEXT: mov r4, r1
4600 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4601 ; CHECK-NEXT: itt lt
4602 ; CHECK-NEXT: movlt.w r4, #-2147483648
4603 ; CHECK-NEXT: movlt r5, #0
4604 ; CHECK-NEXT: vcmp.f32 s22, s30
4605 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4606 ; CHECK-NEXT: mov r0, r6
4607 ; CHECK-NEXT: itt gt
4608 ; CHECK-NEXT: movgt.w r5, #-1
4609 ; CHECK-NEXT: mvngt r4, #-2147483648
4610 ; CHECK-NEXT: vcmp.f32 s22, s22
4611 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4612 ; CHECK-NEXT: itt vs
4613 ; CHECK-NEXT: movvs r4, #0
4614 ; CHECK-NEXT: movvs r5, #0
4615 ; CHECK-NEXT: bl __aeabi_f2lz
4616 ; CHECK-NEXT: vcvtb.f32.f16 s16, s16
4617 ; CHECK-NEXT: mov r7, r0
4618 ; CHECK-NEXT: vmov r0, s16
4619 ; CHECK-NEXT: mov r6, r1
4620 ; CHECK-NEXT: vcmp.f32 s20, s28
4621 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4622 ; CHECK-NEXT: itt lt
4623 ; CHECK-NEXT: movlt.w r6, #-2147483648
4624 ; CHECK-NEXT: movlt r7, #0
4625 ; CHECK-NEXT: vcmp.f32 s20, s30
4626 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4627 ; CHECK-NEXT: itt gt
4628 ; CHECK-NEXT: movgt.w r7, #-1
4629 ; CHECK-NEXT: mvngt r6, #-2147483648
4630 ; CHECK-NEXT: vcmp.f32 s20, s20
4631 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4632 ; CHECK-NEXT: itt vs
4633 ; CHECK-NEXT: movvs r6, #0
4634 ; CHECK-NEXT: movvs r7, #0
4635 ; CHECK-NEXT: bl __aeabi_f2lz
4636 ; CHECK-NEXT: vcmp.f32 s16, s28
4637 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4638 ; CHECK-NEXT: itt lt
4639 ; CHECK-NEXT: movlt r0, #0
4640 ; CHECK-NEXT: movlt.w r1, #-2147483648
4641 ; CHECK-NEXT: vcmp.f32 s16, s30
4642 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4643 ; CHECK-NEXT: vcmp.f32 s16, s16
4644 ; CHECK-NEXT: itt gt
4645 ; CHECK-NEXT: mvngt r1, #-2147483648
4646 ; CHECK-NEXT: movgt.w r0, #-1
4647 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4648 ; CHECK-NEXT: it vs
4649 ; CHECK-NEXT: movvs r0, #0
4650 ; CHECK-NEXT: vcvtt.f32.f16 s16, s17
4651 ; CHECK-NEXT: vmov q5[2], q5[0], r0, r7
4652 ; CHECK-NEXT: vmov r0, s16
4653 ; CHECK-NEXT: it vs
4654 ; CHECK-NEXT: movvs r1, #0
4655 ; CHECK-NEXT: vmov q5[3], q5[1], r1, r6
4656 ; CHECK-NEXT: bl __aeabi_f2lz
4657 ; CHECK-NEXT: vcmp.f32 s16, s28
4658 ; CHECK-NEXT: mov r7, r0
4659 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4660 ; CHECK-NEXT: mov r6, r1
4661 ; CHECK-NEXT: vcmp.f32 s16, s30
4662 ; CHECK-NEXT: itt lt
4663 ; CHECK-NEXT: movlt.w r6, #-2147483648
4664 ; CHECK-NEXT: movlt r7, #0
4665 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4666 ; CHECK-NEXT: vcmp.f32 s16, s16
4667 ; CHECK-NEXT: vcvtb.f32.f16 s16, s17
4668 ; CHECK-NEXT: itt gt
4669 ; CHECK-NEXT: movgt.w r7, #-1
4670 ; CHECK-NEXT: mvngt r6, #-2147483648
4671 ; CHECK-NEXT: vmov r0, s16
4672 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4673 ; CHECK-NEXT: itt vs
4674 ; CHECK-NEXT: movvs r6, #0
4675 ; CHECK-NEXT: movvs r7, #0
4676 ; CHECK-NEXT: bl __aeabi_f2lz
4677 ; CHECK-NEXT: vcmp.f32 s16, s28
4678 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4679 ; CHECK-NEXT: itt lt
4680 ; CHECK-NEXT: movlt r0, #0
4681 ; CHECK-NEXT: movlt.w r1, #-2147483648
4682 ; CHECK-NEXT: vcmp.f32 s16, s30
4683 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4684 ; CHECK-NEXT: vcmp.f32 s16, s16
4685 ; CHECK-NEXT: itt gt
4686 ; CHECK-NEXT: mvngt r1, #-2147483648
4687 ; CHECK-NEXT: movgt.w r0, #-1
4688 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4689 ; CHECK-NEXT: it vs
4690 ; CHECK-NEXT: movvs r0, #0
4691 ; CHECK-NEXT: vcvtb.f32.f16 s16, s18
4692 ; CHECK-NEXT: vmov q6[2], q6[0], r0, r7
4693 ; CHECK-NEXT: vmov r0, s16
4694 ; CHECK-NEXT: it vs
4695 ; CHECK-NEXT: movvs r1, #0
4696 ; CHECK-NEXT: vmov q6[3], q6[1], r1, r6
4697 ; CHECK-NEXT: bl __aeabi_f2lz
4698 ; CHECK-NEXT: vcmp.f32 s16, s28
4699 ; CHECK-NEXT: vmov q3[2], q3[0], r10, r9
4700 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4701 ; CHECK-NEXT: itt lt
4702 ; CHECK-NEXT: movlt r0, #0
4703 ; CHECK-NEXT: movlt.w r1, #-2147483648
4704 ; CHECK-NEXT: vcmp.f32 s16, s30
4705 ; CHECK-NEXT: vmov q3[3], q3[1], r11, r8
4706 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4707 ; CHECK-NEXT: itt gt
4708 ; CHECK-NEXT: mvngt r1, #-2147483648
4709 ; CHECK-NEXT: movgt.w r0, #-1
4710 ; CHECK-NEXT: vcmp.f32 s16, s16
4711 ; CHECK-NEXT: vmov q0, q5
4712 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4713 ; CHECK-NEXT: itt vs
4714 ; CHECK-NEXT: movvs r0, #0
4715 ; CHECK-NEXT: movvs r1, #0
4716 ; CHECK-NEXT: vmov q2[2], q2[0], r0, r5
4717 ; CHECK-NEXT: vmov q1, q6
4718 ; CHECK-NEXT: vmov q2[3], q2[1], r1, r4
4719 ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
4720 ; CHECK-NEXT: add sp, #4
4721 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
4722 ; CHECK-NEXT: .p2align 2
4723 ; CHECK-NEXT: @ %bb.1:
4724 ; CHECK-NEXT: .LCPI49_0:
4725 ; CHECK-NEXT: .long 0xdf000000 @ float -9.22337203E+18
4726 ; CHECK-NEXT: .LCPI49_1:
4727 ; CHECK-NEXT: .long 0x5effffff @ float 9.22337149E+18
4728 %x = call <8 x i64> @llvm.fptosi.sat.v8f16.v8i64(<8 x half> %f)
4729 ret <8 x i64> %x
4730 }
4732 define arm_aapcs_vfpcc <8 x i100> @test_signed_v8f16_v8i100(<8 x half> %f) {
4733 ; CHECK-LABEL: test_signed_v8f16_v8i100:
4734 ; CHECK: @ %bb.0:
4735 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
4736 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
4737 ; CHECK-NEXT: .pad #4
4738 ; CHECK-NEXT: sub sp, #4
4739 ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
4740 ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
4741 ; CHECK-NEXT: .pad #48
4742 ; CHECK-NEXT: sub sp, #48
4743 ; CHECK-NEXT: vmov q4, q0
4744 ; CHECK-NEXT: mov r4, r0
4745 ; CHECK-NEXT: vcvtb.f32.f16 s24, s17
4746 ; CHECK-NEXT: vmov r0, s24
4747 ; CHECK-NEXT: bl __fixsfti
4748 ; CHECK-NEXT: vcvtb.f32.f16 s26, s18
4749 ; CHECK-NEXT: mov r8, r0
4750 ; CHECK-NEXT: vmov r0, s26
4751 ; CHECK-NEXT: vldr s22, .LCPI50_0
4752 ; CHECK-NEXT: vldr s20, .LCPI50_1
4753 ; CHECK-NEXT: mov r9, r1
4754 ; CHECK-NEXT: vcmp.f32 s24, s22
4755 ; CHECK-NEXT: mov r10, r2
4756 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4757 ; CHECK-NEXT: itttt lt
4758 ; CHECK-NEXT: mvnlt r3, #7
4759 ; CHECK-NEXT: movlt.w r8, #0
4760 ; CHECK-NEXT: movlt.w r9, #0
4761 ; CHECK-NEXT: movlt.w r10, #0
4762 ; CHECK-NEXT: vcmp.f32 s24, s20
4763 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4764 ; CHECK-NEXT: itttt gt
4765 ; CHECK-NEXT: movgt.w r10, #-1
4766 ; CHECK-NEXT: movgt.w r9, #-1
4767 ; CHECK-NEXT: movgt.w r8, #-1
4768 ; CHECK-NEXT: movgt r3, #7
4769 ; CHECK-NEXT: vcmp.f32 s24, s24
4770 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4771 ; CHECK-NEXT: it vs
4772 ; CHECK-NEXT: movvs r3, #0
4773 ; CHECK-NEXT: str r3, [sp, #36] @ 4-byte Spill
4774 ; CHECK-NEXT: ittt vs
4775 ; CHECK-NEXT: movvs.w r8, #0
4776 ; CHECK-NEXT: movvs.w r9, #0
4777 ; CHECK-NEXT: movvs.w r10, #0
4778 ; CHECK-NEXT: bl __fixsfti
4779 ; CHECK-NEXT: vcvtb.f32.f16 s24, s19
4780 ; CHECK-NEXT: mov r5, r0
4781 ; CHECK-NEXT: vmov r0, s24
4782 ; CHECK-NEXT: mov r6, r1
4783 ; CHECK-NEXT: vcmp.f32 s26, s22
4784 ; CHECK-NEXT: mov r7, r2
4785 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4786 ; CHECK-NEXT: itttt lt
4787 ; CHECK-NEXT: mvnlt r3, #7
4788 ; CHECK-NEXT: movlt r5, #0
4789 ; CHECK-NEXT: movlt r6, #0
4790 ; CHECK-NEXT: movlt r7, #0
4791 ; CHECK-NEXT: vcmp.f32 s26, s20
4792 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4793 ; CHECK-NEXT: itttt gt
4794 ; CHECK-NEXT: movgt.w r7, #-1
4795 ; CHECK-NEXT: movgt.w r6, #-1
4796 ; CHECK-NEXT: movgt.w r5, #-1
4797 ; CHECK-NEXT: movgt r3, #7
4798 ; CHECK-NEXT: vcmp.f32 s26, s26
4799 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4800 ; CHECK-NEXT: it vs
4801 ; CHECK-NEXT: movvs r3, #0
4802 ; CHECK-NEXT: str r3, [sp, #32] @ 4-byte Spill
4803 ; CHECK-NEXT: ittt vs
4804 ; CHECK-NEXT: movvs r5, #0
4805 ; CHECK-NEXT: movvs r6, #0
4806 ; CHECK-NEXT: movvs r7, #0
4807 ; CHECK-NEXT: bl __fixsfti
4808 ; CHECK-NEXT: vcmp.f32 s24, s22
4809 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4810 ; CHECK-NEXT: itttt lt
4811 ; CHECK-NEXT: movlt r2, #0
4812 ; CHECK-NEXT: movlt r1, #0
4813 ; CHECK-NEXT: movlt r0, #0
4814 ; CHECK-NEXT: mvnlt r3, #7
4815 ; CHECK-NEXT: vcmp.f32 s24, s20
4816 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4817 ; CHECK-NEXT: vcmp.f32 s24, s24
4818 ; CHECK-NEXT: itttt gt
4819 ; CHECK-NEXT: movgt r3, #7
4820 ; CHECK-NEXT: movgt.w r0, #-1
4821 ; CHECK-NEXT: movgt.w r1, #-1
4822 ; CHECK-NEXT: movgt.w r2, #-1
4823 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4824 ; CHECK-NEXT: it vs
4825 ; CHECK-NEXT: movvs r2, #0
4826 ; CHECK-NEXT: str.w r2, [r4, #83]
4827 ; CHECK-NEXT: it vs
4828 ; CHECK-NEXT: movvs r1, #0
4829 ; CHECK-NEXT: str.w r1, [r4, #79]
4830 ; CHECK-NEXT: it vs
4831 ; CHECK-NEXT: movvs r0, #0
4832 ; CHECK-NEXT: vcvtt.f32.f16 s24, s16
4833 ; CHECK-NEXT: str.w r0, [r4, #75]
4834 ; CHECK-NEXT: vmov r0, s24
4835 ; CHECK-NEXT: str.w r7, [r4, #58]
4836 ; CHECK-NEXT: str.w r6, [r4, #54]
4837 ; CHECK-NEXT: str.w r5, [r4, #50]
4838 ; CHECK-NEXT: str.w r10, [r4, #33]
4839 ; CHECK-NEXT: str.w r9, [r4, #29]
4840 ; CHECK-NEXT: str.w r8, [r4, #25]
4841 ; CHECK-NEXT: it vs
4842 ; CHECK-NEXT: movvs r3, #0
4843 ; CHECK-NEXT: str r3, [sp, #28] @ 4-byte Spill
4844 ; CHECK-NEXT: bl __fixsfti
4845 ; CHECK-NEXT: vcmp.f32 s24, s22
4846 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4847 ; CHECK-NEXT: itttt lt
4848 ; CHECK-NEXT: mvnlt r3, #7
4849 ; CHECK-NEXT: movlt r2, #0
4850 ; CHECK-NEXT: movlt r0, #0
4851 ; CHECK-NEXT: movlt r1, #0
4852 ; CHECK-NEXT: vcmp.f32 s24, s20
4853 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4854 ; CHECK-NEXT: vcmp.f32 s24, s24
4855 ; CHECK-NEXT: itttt gt
4856 ; CHECK-NEXT: movgt.w r1, #-1
4857 ; CHECK-NEXT: movgt.w r0, #-1
4858 ; CHECK-NEXT: movgt.w r2, #-1
4859 ; CHECK-NEXT: movgt r3, #7
4860 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4861 ; CHECK-NEXT: it vs
4862 ; CHECK-NEXT: movvs r3, #0
4863 ; CHECK-NEXT: str r3, [sp, #24] @ 4-byte Spill
4864 ; CHECK-NEXT: it vs
4865 ; CHECK-NEXT: movvs r2, #0
4866 ; CHECK-NEXT: str r2, [sp, #20] @ 4-byte Spill
4867 ; CHECK-NEXT: it vs
4868 ; CHECK-NEXT: movvs r0, #0
4869 ; CHECK-NEXT: vcvtt.f32.f16 s24, s17
4870 ; CHECK-NEXT: str r0, [sp, #40] @ 4-byte Spill
4871 ; CHECK-NEXT: vmov r0, s24
4872 ; CHECK-NEXT: it vs
4873 ; CHECK-NEXT: movvs r1, #0
4874 ; CHECK-NEXT: str r1, [sp, #44] @ 4-byte Spill
4875 ; CHECK-NEXT: bl __fixsfti
4876 ; CHECK-NEXT: vcmp.f32 s24, s22
4877 ; CHECK-NEXT: vcvtt.f32.f16 s18, s18
4878 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4879 ; CHECK-NEXT: itttt lt
4880 ; CHECK-NEXT: mvnlt r3, #7
4881 ; CHECK-NEXT: movlt r2, #0
4882 ; CHECK-NEXT: movlt r1, #0
4883 ; CHECK-NEXT: movlt r0, #0
4884 ; CHECK-NEXT: vcmp.f32 s24, s20
4885 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4886 ; CHECK-NEXT: itttt gt
4887 ; CHECK-NEXT: movgt.w r0, #-1
4888 ; CHECK-NEXT: movgt.w r1, #-1
4889 ; CHECK-NEXT: movgt.w r2, #-1
4890 ; CHECK-NEXT: movgt r3, #7
4891 ; CHECK-NEXT: vcmp.f32 s24, s24
4892 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4893 ; CHECK-NEXT: it vs
4894 ; CHECK-NEXT: movvs r3, #0
4895 ; CHECK-NEXT: str r3, [sp, #16] @ 4-byte Spill
4896 ; CHECK-NEXT: it vs
4897 ; CHECK-NEXT: movvs r2, #0
4898 ; CHECK-NEXT: str r2, [sp, #12] @ 4-byte Spill
4899 ; CHECK-NEXT: it vs
4900 ; CHECK-NEXT: movvs r1, #0
4901 ; CHECK-NEXT: str r1, [sp, #8] @ 4-byte Spill
4902 ; CHECK-NEXT: it vs
4903 ; CHECK-NEXT: movvs r0, #0
4904 ; CHECK-NEXT: str r0, [sp, #4] @ 4-byte Spill
4905 ; CHECK-NEXT: vmov r0, s18
4906 ; CHECK-NEXT: bl __fixsfti
4907 ; CHECK-NEXT: vcmp.f32 s18, s22
4908 ; CHECK-NEXT: mov r5, r0
4909 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4910 ; CHECK-NEXT: mov r7, r1
4911 ; CHECK-NEXT: mov r8, r2
4912 ; CHECK-NEXT: vcmp.f32 s18, s20
4913 ; CHECK-NEXT: itttt lt
4914 ; CHECK-NEXT: mvnlt r3, #7
4915 ; CHECK-NEXT: movlt.w r8, #0
4916 ; CHECK-NEXT: movlt r5, #0
4917 ; CHECK-NEXT: movlt r7, #0
4918 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4919 ; CHECK-NEXT: vcmp.f32 s18, s18
4920 ; CHECK-NEXT: vcvtt.f32.f16 s18, s19
4921 ; CHECK-NEXT: vmov r0, s18
4922 ; CHECK-NEXT: itttt gt
4923 ; CHECK-NEXT: movgt.w r7, #-1
4924 ; CHECK-NEXT: movgt.w r5, #-1
4925 ; CHECK-NEXT: movgt.w r8, #-1
4926 ; CHECK-NEXT: movgt r3, #7
4927 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4928 ; CHECK-NEXT: it vs
4929 ; CHECK-NEXT: movvs r3, #0
4930 ; CHECK-NEXT: str r3, [sp] @ 4-byte Spill
4931 ; CHECK-NEXT: ittt vs
4932 ; CHECK-NEXT: movvs.w r8, #0
4933 ; CHECK-NEXT: movvs r5, #0
4934 ; CHECK-NEXT: movvs r7, #0
4935 ; CHECK-NEXT: bl __fixsfti
4936 ; CHECK-NEXT: vcvtb.f32.f16 s16, s16
4937 ; CHECK-NEXT: mov r6, r0
4938 ; CHECK-NEXT: vmov r0, s16
4939 ; CHECK-NEXT: mov r9, r1
4940 ; CHECK-NEXT: vcmp.f32 s18, s22
4941 ; CHECK-NEXT: mov r10, r2
4942 ; CHECK-NEXT: mov r11, r3
4943 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4944 ; CHECK-NEXT: itttt lt
4945 ; CHECK-NEXT: mvnlt r11, #7
4946 ; CHECK-NEXT: movlt.w r10, #0
4947 ; CHECK-NEXT: movlt.w r9, #0
4948 ; CHECK-NEXT: movlt r6, #0
4949 ; CHECK-NEXT: vcmp.f32 s18, s20
4950 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4951 ; CHECK-NEXT: itttt gt
4952 ; CHECK-NEXT: movgt.w r6, #-1
4953 ; CHECK-NEXT: movgt.w r9, #-1
4954 ; CHECK-NEXT: movgt.w r10, #-1
4955 ; CHECK-NEXT: movgt.w r11, #7
4956 ; CHECK-NEXT: vcmp.f32 s18, s18
4957 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4958 ; CHECK-NEXT: itttt vs
4959 ; CHECK-NEXT: movvs.w r11, #0
4960 ; CHECK-NEXT: movvs.w r10, #0
4961 ; CHECK-NEXT: movvs.w r9, #0
4962 ; CHECK-NEXT: movvs r6, #0
4963 ; CHECK-NEXT: bl __fixsfti
4964 ; CHECK-NEXT: vcmp.f32 s16, s22
4965 ; CHECK-NEXT: mov r12, r3
4966 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4967 ; CHECK-NEXT: itttt lt
4968 ; CHECK-NEXT: movlt r2, #0
4969 ; CHECK-NEXT: movlt r1, #0
4970 ; CHECK-NEXT: movlt r0, #0
4971 ; CHECK-NEXT: mvnlt r12, #7
4972 ; CHECK-NEXT: vcmp.f32 s16, s20
4973 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4974 ; CHECK-NEXT: itttt gt
4975 ; CHECK-NEXT: movgt.w r12, #7
4976 ; CHECK-NEXT: movgt.w r0, #-1
4977 ; CHECK-NEXT: movgt.w r1, #-1
4978 ; CHECK-NEXT: movgt.w r2, #-1
4979 ; CHECK-NEXT: vcmp.f32 s16, s16
4980 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
4981 ; CHECK-NEXT: it vs
4982 ; CHECK-NEXT: movvs r2, #0
4983 ; CHECK-NEXT: str r2, [r4, #8]
4984 ; CHECK-NEXT: it vs
4985 ; CHECK-NEXT: movvs r1, #0
4986 ; CHECK-NEXT: str r1, [r4, #4]
4987 ; CHECK-NEXT: it vs
4988 ; CHECK-NEXT: movvs r0, #0
4989 ; CHECK-NEXT: str r0, [r4]
4990 ; CHECK-NEXT: mov r0, r6
4991 ; CHECK-NEXT: lsrl r0, r9, #28
4992 ; CHECK-NEXT: str.w r0, [r4, #91]
4993 ; CHECK-NEXT: mov r0, r5
4994 ; CHECK-NEXT: lsrl r0, r7, #28
4995 ; CHECK-NEXT: str.w r0, [r4, #66]
4996 ; CHECK-NEXT: ldr.w lr, [sp, #4] @ 4-byte Reload
4997 ; CHECK-NEXT: ldr r3, [sp, #8] @ 4-byte Reload
4998 ; CHECK-NEXT: mov r0, lr
4999 ; CHECK-NEXT: lsrl r0, r3, #28
5000 ; CHECK-NEXT: str.w r0, [r4, #41]
5001 ; CHECK-NEXT: ldrd r0, r1, [sp, #40] @ 8-byte Folded Reload
5002 ; CHECK-NEXT: lsrl r0, r1, #28
5003 ; CHECK-NEXT: str r1, [sp, #44] @ 4-byte Spill
5004 ; CHECK-NEXT: and r1, r11, #15
5005 ; CHECK-NEXT: str r0, [r4, #16]
5006 ; CHECK-NEXT: orr.w r0, r9, r10, lsl #4
5007 ; CHECK-NEXT: lsrl r10, r1, #28
5008 ; CHECK-NEXT: str.w r0, [r4, #95]
5009 ; CHECK-NEXT: strb.w r10, [r4, #99]
5010 ; CHECK-NEXT: ldr r0, [sp, #28] @ 4-byte Reload
5011 ; CHECK-NEXT: and r0, r0, #15
5012 ; CHECK-NEXT: orr.w r0, r0, r6, lsl #4
5013 ; CHECK-NEXT: str.w r0, [r4, #87]
5014 ; CHECK-NEXT: orr.w r0, r7, r8, lsl #4
5015 ; CHECK-NEXT: str.w r0, [r4, #70]
5016 ; CHECK-NEXT: ldr r0, [sp] @ 4-byte Reload
5017 ; CHECK-NEXT: and r1, r0, #15
5018 ; CHECK-NEXT: lsrl r8, r1, #28
5019 ; CHECK-NEXT: strb.w r8, [r4, #74]
5020 ; CHECK-NEXT: ldr r0, [sp, #32] @ 4-byte Reload
5021 ; CHECK-NEXT: and r0, r0, #15
5022 ; CHECK-NEXT: orr.w r0, r0, r5, lsl #4
5023 ; CHECK-NEXT: str.w r0, [r4, #62]
5024 ; CHECK-NEXT: ldr r2, [sp, #12] @ 4-byte Reload
5025 ; CHECK-NEXT: orr.w r0, r3, r2, lsl #4
5026 ; CHECK-NEXT: str.w r0, [r4, #45]
5027 ; CHECK-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
5028 ; CHECK-NEXT: and r1, r0, #15
5029 ; CHECK-NEXT: lsrl r2, r1, #28
5030 ; CHECK-NEXT: strb.w r2, [r4, #49]
5031 ; CHECK-NEXT: ldr r0, [sp, #36] @ 4-byte Reload
5032 ; CHECK-NEXT: and r0, r0, #15
5033 ; CHECK-NEXT: orr.w r0, r0, lr, lsl #4
5034 ; CHECK-NEXT: str.w r0, [r4, #37]
5035 ; CHECK-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
5036 ; CHECK-NEXT: ldr r0, [sp, #44] @ 4-byte Reload
5037 ; CHECK-NEXT: orr.w r0, r0, r2, lsl #4
5038 ; CHECK-NEXT: str r0, [r4, #20]
5039 ; CHECK-NEXT: ldr r0, [sp, #24] @ 4-byte Reload
5040 ; CHECK-NEXT: and r1, r0, #15
5041 ; CHECK-NEXT: lsrl r2, r1, #28
5042 ; CHECK-NEXT: strb r2, [r4, #24]
5043 ; CHECK-NEXT: it vs
5044 ; CHECK-NEXT: movvs.w r12, #0
5045 ; CHECK-NEXT: ldr r1, [sp, #40] @ 4-byte Reload
5046 ; CHECK-NEXT: and r0, r12, #15
5047 ; CHECK-NEXT: orr.w r0, r0, r1, lsl #4
5048 ; CHECK-NEXT: str r0, [r4, #12]
5049 ; CHECK-NEXT: add sp, #48
5050 ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
5051 ; CHECK-NEXT: add sp, #4
5052 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
5053 ; CHECK-NEXT: .p2align 2
5054 ; CHECK-NEXT: @ %bb.1:
5055 ; CHECK-NEXT: .LCPI50_0:
5056 ; CHECK-NEXT: .long 0xf1000000 @ float -6.338253E+29
5057 ; CHECK-NEXT: .LCPI50_1:
5058 ; CHECK-NEXT: .long 0x70ffffff @ float 6.33825262E+29
5059 %x = call <8 x i100> @llvm.fptosi.sat.v8f16.v8i100(<8 x half> %f)
5060 ret <8 x i100> %x
5061 }
5063 define arm_aapcs_vfpcc <8 x i128> @test_signed_v8f16_v8i128(<8 x half> %f) {
5064 ; CHECK-LABEL: test_signed_v8f16_v8i128:
5065 ; CHECK: @ %bb.0:
5066 ; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
5067 ; CHECK-NEXT: push {r4, r5, r6, r7, lr}
5068 ; CHECK-NEXT: .pad #4
5069 ; CHECK-NEXT: sub sp, #4
5070 ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
5071 ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
5072 ; CHECK-NEXT: vmov q4, q0
5073 ; CHECK-NEXT: mov r4, r0
5074 ; CHECK-NEXT: vcvtt.f32.f16 s30, s19
5075 ; CHECK-NEXT: vcvtb.f32.f16 s20, s16
5076 ; CHECK-NEXT: vmov r0, s30
5077 ; CHECK-NEXT: vcvtb.f32.f16 s26, s19
5078 ; CHECK-NEXT: vldr s22, .LCPI51_0
5079 ; CHECK-NEXT: vmov r5, s20
5080 ; CHECK-NEXT: vmov r7, s26
5081 ; CHECK-NEXT: vcvtt.f32.f16 s28, s18
5082 ; CHECK-NEXT: bl __fixsfti
5083 ; CHECK-NEXT: vldr s24, .LCPI51_1
5084 ; CHECK-NEXT: add.w r12, r4, #112
5085 ; CHECK-NEXT: vmov r6, s28
5086 ; CHECK-NEXT: vcvtb.f32.f16 s18, s18
5087 ; CHECK-NEXT: vcmp.f32 s30, s24
5088 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
5089 ; CHECK-NEXT: itttt lt
5090 ; CHECK-NEXT: movlt.w r3, #-2147483648
5091 ; CHECK-NEXT: movlt r2, #0
5092 ; CHECK-NEXT: movlt r1, #0
5093 ; CHECK-NEXT: movlt r0, #0
5094 ; CHECK-NEXT: vcmp.f32 s30, s22
5095 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
5096 ; CHECK-NEXT: itttt gt
5097 ; CHECK-NEXT: movgt.w r0, #-1
5098 ; CHECK-NEXT: movgt.w r1, #-1
5099 ; CHECK-NEXT: movgt.w r2, #-1
5100 ; CHECK-NEXT: mvngt r3, #-2147483648
5101 ; CHECK-NEXT: vcmp.f32 s30, s30
5102 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
5103 ; CHECK-NEXT: it vs
5104 ; CHECK-NEXT: movvs r3, #0
5105 ; CHECK-NEXT: ittt vs
5106 ; CHECK-NEXT: movvs r2, #0
5107 ; CHECK-NEXT: movvs r1, #0
5108 ; CHECK-NEXT: movvs r0, #0
5109 ; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
5110 ; CHECK-NEXT: mov r0, r7
5111 ; CHECK-NEXT: bl __fixsfti
5112 ; CHECK-NEXT: vcmp.f32 s26, s24
5113 ; CHECK-NEXT: add.w r12, r4, #96
5114 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
5115 ; CHECK-NEXT: itttt lt
5116 ; CHECK-NEXT: movlt.w r3, #-2147483648
5117 ; CHECK-NEXT: movlt r2, #0
5118 ; CHECK-NEXT: movlt r1, #0
5119 ; CHECK-NEXT: movlt r0, #0
5120 ; CHECK-NEXT: vcmp.f32 s26, s22
5121 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
5122 ; CHECK-NEXT: vcmp.f32 s26, s26
5123 ; CHECK-NEXT: itttt gt
5124 ; CHECK-NEXT: movgt.w r0, #-1
5125 ; CHECK-NEXT: movgt.w r1, #-1
5126 ; CHECK-NEXT: movgt.w r2, #-1
5127 ; CHECK-NEXT: mvngt r3, #-2147483648
5128 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
5129 ; CHECK-NEXT: it vs
5130 ; CHECK-NEXT: movvs r3, #0
5131 ; CHECK-NEXT: ittt vs
5132 ; CHECK-NEXT: movvs r2, #0
5133 ; CHECK-NEXT: movvs r1, #0
5134 ; CHECK-NEXT: movvs r0, #0
5135 ; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
5136 ; CHECK-NEXT: mov r0, r6
5137 ; CHECK-NEXT: vmov r7, s18
5138 ; CHECK-NEXT: vcvtt.f32.f16 s26, s17
5139 ; CHECK-NEXT: bl __fixsfti
5140 ; CHECK-NEXT: vcmp.f32 s28, s24
5141 ; CHECK-NEXT: add.w r12, r4, #80
5142 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
5143 ; CHECK-NEXT: itttt lt
5144 ; CHECK-NEXT: movlt.w r3, #-2147483648
5145 ; CHECK-NEXT: movlt r2, #0
5146 ; CHECK-NEXT: movlt r1, #0
5147 ; CHECK-NEXT: movlt r0, #0
5148 ; CHECK-NEXT: vcmp.f32 s28, s22
5149 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
5150 ; CHECK-NEXT: vcmp.f32 s28, s28
5151 ; CHECK-NEXT: itttt gt
5152 ; CHECK-NEXT: movgt.w r0, #-1
5153 ; CHECK-NEXT: movgt.w r1, #-1
5154 ; CHECK-NEXT: movgt.w r2, #-1
5155 ; CHECK-NEXT: mvngt r3, #-2147483648
5156 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
5157 ; CHECK-NEXT: it vs
5158 ; CHECK-NEXT: movvs r3, #0
5159 ; CHECK-NEXT: ittt vs
5160 ; CHECK-NEXT: movvs r2, #0
5161 ; CHECK-NEXT: movvs r1, #0
5162 ; CHECK-NEXT: movvs r0, #0
5163 ; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
5164 ; CHECK-NEXT: mov r0, r7
5165 ; CHECK-NEXT: vmov r6, s26
5166 ; CHECK-NEXT: vcvtb.f32.f16 s28, s17
5167 ; CHECK-NEXT: bl __fixsfti
5168 ; CHECK-NEXT: vcmp.f32 s18, s24
5169 ; CHECK-NEXT: add.w r12, r4, #64
5170 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
5171 ; CHECK-NEXT: itttt lt
5172 ; CHECK-NEXT: movlt.w r3, #-2147483648
5173 ; CHECK-NEXT: movlt r2, #0
5174 ; CHECK-NEXT: movlt r1, #0
5175 ; CHECK-NEXT: movlt r0, #0
5176 ; CHECK-NEXT: vcmp.f32 s18, s22
5177 ; CHECK-NEXT: vcvtt.f32.f16 s16, s16
5178 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
5179 ; CHECK-NEXT: itttt gt
5180 ; CHECK-NEXT: movgt.w r0, #-1
5181 ; CHECK-NEXT: movgt.w r1, #-1
5182 ; CHECK-NEXT: movgt.w r2, #-1
5183 ; CHECK-NEXT: mvngt r3, #-2147483648
5184 ; CHECK-NEXT: vcmp.f32 s18, s18
5185 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
5186 ; CHECK-NEXT: it vs
5187 ; CHECK-NEXT: movvs r3, #0
5188 ; CHECK-NEXT: ittt vs
5189 ; CHECK-NEXT: movvs r2, #0
5190 ; CHECK-NEXT: movvs r1, #0
5191 ; CHECK-NEXT: movvs r0, #0
5192 ; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
5193 ; CHECK-NEXT: mov r0, r6
5194 ; CHECK-NEXT: vmov r7, s28
5195 ; CHECK-NEXT: bl __fixsfti
5196 ; CHECK-NEXT: vcmp.f32 s26, s24
5197 ; CHECK-NEXT: add.w r12, r4, #48
5198 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
5199 ; CHECK-NEXT: itttt lt
5200 ; CHECK-NEXT: movlt.w r3, #-2147483648
5201 ; CHECK-NEXT: movlt r2, #0
5202 ; CHECK-NEXT: movlt r1, #0
5203 ; CHECK-NEXT: movlt r0, #0
5204 ; CHECK-NEXT: vcmp.f32 s26, s22
5205 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
5206 ; CHECK-NEXT: itttt gt
5207 ; CHECK-NEXT: movgt.w r0, #-1
5208 ; CHECK-NEXT: movgt.w r1, #-1
5209 ; CHECK-NEXT: movgt.w r2, #-1
5210 ; CHECK-NEXT: mvngt r3, #-2147483648
5211 ; CHECK-NEXT: vcmp.f32 s26, s26
5212 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
5213 ; CHECK-NEXT: it vs
5214 ; CHECK-NEXT: movvs r3, #0
5215 ; CHECK-NEXT: ittt vs
5216 ; CHECK-NEXT: movvs r2, #0
5217 ; CHECK-NEXT: movvs r1, #0
5218 ; CHECK-NEXT: movvs r0, #0
5219 ; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
5220 ; CHECK-NEXT: mov r0, r7
5221 ; CHECK-NEXT: vmov r6, s16
5222 ; CHECK-NEXT: bl __fixsfti
5223 ; CHECK-NEXT: vcmp.f32 s28, s24
5224 ; CHECK-NEXT: add.w r12, r4, #32
5225 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
5226 ; CHECK-NEXT: itttt lt
5227 ; CHECK-NEXT: movlt.w r3, #-2147483648
5228 ; CHECK-NEXT: movlt r2, #0
5229 ; CHECK-NEXT: movlt r1, #0
5230 ; CHECK-NEXT: movlt r0, #0
5231 ; CHECK-NEXT: vcmp.f32 s28, s22
5232 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
5233 ; CHECK-NEXT: itttt gt
5234 ; CHECK-NEXT: movgt.w r0, #-1
5235 ; CHECK-NEXT: movgt.w r1, #-1
5236 ; CHECK-NEXT: movgt.w r2, #-1
5237 ; CHECK-NEXT: mvngt r3, #-2147483648
5238 ; CHECK-NEXT: vcmp.f32 s28, s28
5239 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
5240 ; CHECK-NEXT: itttt vs
5241 ; CHECK-NEXT: movvs r3, #0
5242 ; CHECK-NEXT: movvs r2, #0
5243 ; CHECK-NEXT: movvs r1, #0
5244 ; CHECK-NEXT: movvs r0, #0
5245 ; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
5246 ; CHECK-NEXT: mov r0, r6
5247 ; CHECK-NEXT: bl __fixsfti
5248 ; CHECK-NEXT: vcmp.f32 s16, s24
5249 ; CHECK-NEXT: add.w r12, r4, #16
5250 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
5251 ; CHECK-NEXT: itttt lt
5252 ; CHECK-NEXT: movlt.w r3, #-2147483648
5253 ; CHECK-NEXT: movlt r2, #0
5254 ; CHECK-NEXT: movlt r1, #0
5255 ; CHECK-NEXT: movlt r0, #0
5256 ; CHECK-NEXT: vcmp.f32 s16, s22
5257 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
5258 ; CHECK-NEXT: itttt gt
5259 ; CHECK-NEXT: movgt.w r0, #-1
5260 ; CHECK-NEXT: movgt.w r1, #-1
5261 ; CHECK-NEXT: movgt.w r2, #-1
5262 ; CHECK-NEXT: mvngt r3, #-2147483648
5263 ; CHECK-NEXT: vcmp.f32 s16, s16
5264 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
5265 ; CHECK-NEXT: itttt vs
5266 ; CHECK-NEXT: movvs r3, #0
5267 ; CHECK-NEXT: movvs r2, #0
5268 ; CHECK-NEXT: movvs r1, #0
5269 ; CHECK-NEXT: movvs r0, #0
5270 ; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
5271 ; CHECK-NEXT: mov r0, r5
5272 ; CHECK-NEXT: bl __fixsfti
5273 ; CHECK-NEXT: vcmp.f32 s20, s24
5274 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
5275 ; CHECK-NEXT: itttt lt
5276 ; CHECK-NEXT: movlt.w r3, #-2147483648
5277 ; CHECK-NEXT: movlt r2, #0
5278 ; CHECK-NEXT: movlt r1, #0
5279 ; CHECK-NEXT: movlt r0, #0
5280 ; CHECK-NEXT: vcmp.f32 s20, s22
5281 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
5282 ; CHECK-NEXT: itttt gt
5283 ; CHECK-NEXT: movgt.w r0, #-1
5284 ; CHECK-NEXT: movgt.w r1, #-1
5285 ; CHECK-NEXT: movgt.w r2, #-1
5286 ; CHECK-NEXT: mvngt r3, #-2147483648
5287 ; CHECK-NEXT: vcmp.f32 s20, s20
5288 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
5289 ; CHECK-NEXT: itttt vs
5290 ; CHECK-NEXT: movvs r3, #0
5291 ; CHECK-NEXT: movvs r2, #0
5292 ; CHECK-NEXT: movvs r1, #0
5293 ; CHECK-NEXT: movvs r0, #0
5294 ; CHECK-NEXT: stm r4!, {r0, r1, r2, r3}
5295 ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
5296 ; CHECK-NEXT: add sp, #4
5297 ; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
5298 ; CHECK-NEXT: .p2align 2
5299 ; CHECK-NEXT: @ %bb.1:
5300 ; CHECK-NEXT: .LCPI51_0:
5301 ; CHECK-NEXT: .long 0x7effffff @ float 1.70141173E+38
5302 ; CHECK-NEXT: .LCPI51_1:
5303 ; CHECK-NEXT: .long 0xff000000 @ float -1.70141183E+38
5304 %x = call <8 x i128> @llvm.fptosi.sat.v8f16.v8i128(<8 x half> %f)
5305 ret <8 x i128> %x
5306 }