| blob | 11fa3337544a1ae775e2b38664b1e04fea427a06 |
1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
2 ; RUN: opt -S -mtriple riscv64-unknown-linux-gnu < %s --passes=slp-vectorizer -mattr=+v -slp-threshold=-20 | FileCheck %s
3 ; RUN: opt -S -mtriple riscv64-unknown-linux-gnu < %s --passes=slp-vectorizer -mattr=+v -slp-threshold=-15 | FileCheck %s --check-prefix=THR15
5 define i32 @test(ptr %pix1, ptr %pix2, i64 %idx.ext, i64 %idx.ext63, ptr %add.ptr, ptr %add.ptr64) {
6 ; CHECK-LABEL: define i32 @test(
7 ; CHECK-SAME: ptr [[PIX1:%.*]], ptr [[PIX2:%.*]], i64 [[IDX_EXT:%.*]], i64 [[IDX_EXT63:%.*]], ptr [[ADD_PTR:%.*]], ptr [[ADD_PTR64:%.*]]) #[[ATTR0:[0-9]+]] {
8 ; CHECK-NEXT: entry:
9 ; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[PIX1]], align 1
10 ; CHECK-NEXT: [[CONV1:%.*]] = zext i8 [[TMP0]] to i32
11 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[PIX1]], i64 4
12 ; CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr i8, ptr [[PIX2]], i64 4
13 ; CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr i8, ptr [[PIX1]], i64 1
14 ; CHECK-NEXT: [[ARRAYIDX32:%.*]] = getelementptr i8, ptr [[PIX1]], i64 3
15 ; CHECK-NEXT: [[TMP10:%.*]] = load i8, ptr [[ARRAYIDX32]], align 1
16 ; CHECK-NEXT: [[CONV33:%.*]] = zext i8 [[TMP10]] to i32
17 ; CHECK-NEXT: [[ADD_PTR3:%.*]] = getelementptr i8, ptr [[PIX1]], i64 [[IDX_EXT]]
18 ; CHECK-NEXT: [[ADD_PTR644:%.*]] = getelementptr i8, ptr [[PIX2]], i64 [[IDX_EXT63]]
19 ; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr [[ADD_PTR3]], align 1
20 ; CHECK-NEXT: [[CONV_1:%.*]] = zext i8 [[TMP11]] to i32
21 ; CHECK-NEXT: [[ARRAYIDX3_1:%.*]] = getelementptr i8, ptr [[ADD_PTR3]], i64 4
22 ; CHECK-NEXT: [[ARRAYIDX5_1:%.*]] = getelementptr i8, ptr [[ADD_PTR644]], i64 4
23 ; CHECK-NEXT: [[ARRAYIDX8_1:%.*]] = getelementptr i8, ptr [[ADD_PTR3]], i64 1
24 ; CHECK-NEXT: [[ARRAYIDX27_1:%.*]] = getelementptr i8, ptr [[ADD_PTR3]], i64 3
25 ; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[ARRAYIDX27_1]], align 1
26 ; CHECK-NEXT: [[CONV33_1:%.*]] = zext i8 [[TMP5]] to i32
27 ; CHECK-NEXT: [[ADD_PTR_1:%.*]] = getelementptr i8, ptr [[ADD_PTR]], i64 [[IDX_EXT]]
28 ; CHECK-NEXT: [[ADD_PTR64_1:%.*]] = getelementptr i8, ptr [[ADD_PTR64]], i64 [[IDX_EXT63]]
29 ; CHECK-NEXT: [[ARRAYIDX3_2:%.*]] = getelementptr i8, ptr [[ADD_PTR_1]], i64 4
30 ; CHECK-NEXT: [[ARRAYIDX5_2:%.*]] = getelementptr i8, ptr [[ADD_PTR64_1]], i64 4
31 ; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i8>, ptr [[ADD_PTR_1]], align 1
32 ; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <4 x i8> [[TMP4]], <4 x i8> poison, <2 x i32> <i32 0, i32 2>
33 ; CHECK-NEXT: [[TMP21:%.*]] = zext <2 x i8> [[TMP19]] to <2 x i32>
34 ; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i8>, ptr [[ADD_PTR64_1]], align 1
35 ; CHECK-NEXT: [[TMP22:%.*]] = shufflevector <4 x i8> [[TMP9]], <4 x i8> poison, <2 x i32> <i32 0, i32 2>
36 ; CHECK-NEXT: [[TMP31:%.*]] = zext <2 x i8> [[TMP22]] to <2 x i32>
37 ; CHECK-NEXT: [[TMP23:%.*]] = sub <2 x i32> [[TMP21]], [[TMP31]]
38 ; CHECK-NEXT: [[TMP13:%.*]] = load <4 x i8>, ptr [[ARRAYIDX3_2]], align 1
39 ; CHECK-NEXT: [[TMP49:%.*]] = shufflevector <4 x i8> [[TMP13]], <4 x i8> poison, <2 x i32> <i32 0, i32 2>
40 ; CHECK-NEXT: [[TMP26:%.*]] = zext <2 x i8> [[TMP49]] to <2 x i32>
41 ; CHECK-NEXT: [[TMP16:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5_2]], align 1
42 ; CHECK-NEXT: [[TMP27:%.*]] = shufflevector <4 x i8> [[TMP16]], <4 x i8> poison, <2 x i32> <i32 0, i32 2>
43 ; CHECK-NEXT: [[TMP50:%.*]] = zext <2 x i8> [[TMP27]] to <2 x i32>
44 ; CHECK-NEXT: [[TMP24:%.*]] = sub <2 x i32> [[TMP26]], [[TMP50]]
45 ; CHECK-NEXT: [[TMP25:%.*]] = shl <2 x i32> [[TMP24]], splat (i32 16)
46 ; CHECK-NEXT: [[TMP30:%.*]] = add <2 x i32> [[TMP25]], [[TMP23]]
47 ; CHECK-NEXT: [[TMP32:%.*]] = shufflevector <4 x i8> [[TMP4]], <4 x i8> poison, <2 x i32> <i32 1, i32 3>
48 ; CHECK-NEXT: [[TMP51:%.*]] = zext <2 x i8> [[TMP32]] to <2 x i32>
49 ; CHECK-NEXT: [[TMP56:%.*]] = shufflevector <4 x i8> [[TMP9]], <4 x i8> poison, <2 x i32> <i32 1, i32 3>
50 ; CHECK-NEXT: [[TMP57:%.*]] = zext <2 x i8> [[TMP56]] to <2 x i32>
51 ; CHECK-NEXT: [[TMP35:%.*]] = sub <2 x i32> [[TMP51]], [[TMP57]]
52 ; CHECK-NEXT: [[TMP38:%.*]] = shufflevector <4 x i8> [[TMP13]], <4 x i8> poison, <2 x i32> <i32 1, i32 3>
53 ; CHECK-NEXT: [[TMP39:%.*]] = zext <2 x i8> [[TMP38]] to <2 x i32>
54 ; CHECK-NEXT: [[TMP40:%.*]] = shufflevector <4 x i8> [[TMP16]], <4 x i8> poison, <2 x i32> <i32 1, i32 3>
55 ; CHECK-NEXT: [[TMP61:%.*]] = zext <2 x i8> [[TMP40]] to <2 x i32>
56 ; CHECK-NEXT: [[TMP36:%.*]] = sub <2 x i32> [[TMP39]], [[TMP61]]
57 ; CHECK-NEXT: [[TMP37:%.*]] = shl <2 x i32> [[TMP36]], splat (i32 16)
58 ; CHECK-NEXT: [[TMP42:%.*]] = add <2 x i32> [[TMP37]], [[TMP35]]
59 ; CHECK-NEXT: [[TMP34:%.*]] = add <2 x i32> [[TMP42]], [[TMP30]]
60 ; CHECK-NEXT: [[TMP44:%.*]] = sub <2 x i32> [[TMP30]], [[TMP42]]
61 ; CHECK-NEXT: [[TMP43:%.*]] = extractelement <2 x i32> [[TMP34]], i32 0
62 ; CHECK-NEXT: [[CONV_2:%.*]] = extractelement <2 x i32> [[TMP34]], i32 1
63 ; CHECK-NEXT: [[ADD48_2:%.*]] = add i32 [[CONV_2]], [[TMP43]]
64 ; CHECK-NEXT: [[TMP46:%.*]] = extractelement <2 x i32> [[TMP44]], i32 0
65 ; CHECK-NEXT: [[TMP47:%.*]] = extractelement <2 x i32> [[TMP44]], i32 1
66 ; CHECK-NEXT: [[ADD55_2:%.*]] = add i32 [[TMP47]], [[TMP46]]
67 ; CHECK-NEXT: [[ARRAYIDX5_3:%.*]] = getelementptr i8, ptr null, i64 4
68 ; CHECK-NEXT: [[TMP53:%.*]] = load <2 x i8>, ptr null, align 1
69 ; CHECK-NEXT: [[TMP52:%.*]] = load i8, ptr null, align 1
70 ; CHECK-NEXT: [[TMP62:%.*]] = zext <2 x i8> [[TMP53]] to <2 x i32>
71 ; CHECK-NEXT: [[TMP77:%.*]] = zext i8 [[TMP52]] to i32
72 ; CHECK-NEXT: [[TMP54:%.*]] = load <2 x i8>, ptr null, align 1
73 ; CHECK-NEXT: [[TMP55:%.*]] = zext <2 x i8> [[TMP54]] to <2 x i32>
74 ; CHECK-NEXT: [[TMP59:%.*]] = sub <2 x i32> [[TMP62]], [[TMP55]]
75 ; CHECK-NEXT: [[TMP41:%.*]] = call <2 x i8> @llvm.experimental.vp.strided.load.v2i8.p0.i64(ptr align 1 null, i64 4, <2 x i1> splat (i1 true), i32 2)
76 ; CHECK-NEXT: [[TMP58:%.*]] = zext <2 x i8> [[TMP41]] to <2 x i32>
77 ; CHECK-NEXT: [[TMP48:%.*]] = shufflevector <2 x i32> [[TMP58]], <2 x i32> poison, <2 x i32> <i32 1, i32 0>
78 ; CHECK-NEXT: [[TMP63:%.*]] = load <2 x i8>, ptr [[ARRAYIDX5_3]], align 1
79 ; CHECK-NEXT: [[TMP76:%.*]] = zext <2 x i8> [[TMP63]] to <2 x i32>
80 ; CHECK-NEXT: [[TMP81:%.*]] = sub <2 x i32> [[TMP48]], [[TMP76]]
81 ; CHECK-NEXT: [[TMP167:%.*]] = shl <2 x i32> [[TMP81]], splat (i32 16)
82 ; CHECK-NEXT: [[TMP75:%.*]] = add <2 x i32> [[TMP167]], [[TMP59]]
83 ; CHECK-NEXT: [[ARRAYIDX20_3:%.*]] = getelementptr i8, ptr null, i64 2
84 ; CHECK-NEXT: [[ARRAYIDX22_3:%.*]] = getelementptr i8, ptr null, i64 2
85 ; CHECK-NEXT: [[ARRAYIDX27_3:%.*]] = getelementptr i8, ptr null, i64 6
86 ; CHECK-NEXT: [[TMP64:%.*]] = load <2 x i8>, ptr [[ARRAYIDX20_3]], align 1
87 ; CHECK-NEXT: [[TMP79:%.*]] = zext <2 x i8> [[TMP64]] to <2 x i32>
88 ; CHECK-NEXT: [[TMP82:%.*]] = load <2 x i8>, ptr [[ARRAYIDX22_3]], align 1
89 ; CHECK-NEXT: [[TMP91:%.*]] = zext <2 x i8> [[TMP82]] to <2 x i32>
90 ; CHECK-NEXT: [[TMP65:%.*]] = sub <2 x i32> [[TMP79]], [[TMP91]]
91 ; CHECK-NEXT: [[TMP170:%.*]] = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> zeroinitializer, i32 1, <2 x i1> splat (i1 true), <2 x i8> poison)
92 ; CHECK-NEXT: [[TMP171:%.*]] = zext <2 x i8> [[TMP170]] to <2 x i32>
93 ; CHECK-NEXT: [[TMP172:%.*]] = load <2 x i8>, ptr [[ARRAYIDX27_3]], align 1
94 ; CHECK-NEXT: [[TMP173:%.*]] = zext <2 x i8> [[TMP172]] to <2 x i32>
95 ; CHECK-NEXT: [[TMP66:%.*]] = sub <2 x i32> [[TMP171]], [[TMP173]]
96 ; CHECK-NEXT: [[TMP67:%.*]] = shl <2 x i32> [[TMP66]], splat (i32 16)
97 ; CHECK-NEXT: [[TMP69:%.*]] = add <2 x i32> [[TMP67]], [[TMP65]]
98 ; CHECK-NEXT: [[TMP176:%.*]] = extractelement <2 x i32> [[TMP75]], i32 0
99 ; CHECK-NEXT: [[TMP197:%.*]] = extractelement <2 x i32> [[TMP75]], i32 1
100 ; CHECK-NEXT: [[SUB59:%.*]] = add i32 [[TMP197]], [[TMP176]]
101 ; CHECK-NEXT: [[SUB45_3:%.*]] = sub i32 [[TMP176]], [[TMP197]]
102 ; CHECK-NEXT: [[ADD112_2:%.*]] = extractelement <2 x i32> [[TMP69]], i32 0
103 ; CHECK-NEXT: [[XOR_I63_2:%.*]] = extractelement <2 x i32> [[TMP69]], i32 1
104 ; CHECK-NEXT: [[SUB59_1:%.*]] = add i32 [[XOR_I63_2]], [[ADD112_2]]
105 ; CHECK-NEXT: [[SUB47_3:%.*]] = sub i32 [[ADD112_2]], [[XOR_I63_2]]
106 ; CHECK-NEXT: [[ADD94:%.*]] = add i32 [[SUB59_1]], [[SUB59]]
107 ; CHECK-NEXT: [[TMP70:%.*]] = shufflevector <2 x i32> [[TMP34]], <2 x i32> poison, <2 x i32> <i32 poison, i32 0>
108 ; CHECK-NEXT: [[TMP71:%.*]] = insertelement <2 x i32> [[TMP70]], i32 [[SUB59]], i32 0
109 ; CHECK-NEXT: [[TMP72:%.*]] = insertelement <2 x i32> [[TMP34]], i32 [[SUB59_1]], i32 0
110 ; CHECK-NEXT: [[TMP222:%.*]] = sub <2 x i32> [[TMP71]], [[TMP72]]
111 ; CHECK-NEXT: [[ADD55_3:%.*]] = add i32 [[SUB47_3]], [[SUB45_3]]
112 ; CHECK-NEXT: [[TMP74:%.*]] = shufflevector <2 x i32> [[TMP44]], <2 x i32> poison, <2 x i32> <i32 poison, i32 0>
113 ; CHECK-NEXT: [[TMP78:%.*]] = insertelement <2 x i32> [[TMP74]], i32 [[SUB45_3]], i32 0
114 ; CHECK-NEXT: [[TMP80:%.*]] = insertelement <2 x i32> [[TMP44]], i32 [[SUB47_3]], i32 0
115 ; CHECK-NEXT: [[TMP85:%.*]] = sub <2 x i32> [[TMP78]], [[TMP80]]
116 ; CHECK-NEXT: [[ADD95:%.*]] = add i32 [[ADD94]], [[ADD48_2]]
117 ; CHECK-NEXT: [[SUB86_3:%.*]] = sub i32 [[ADD48_2]], [[ADD94]]
118 ; CHECK-NEXT: [[SHR_I_1:%.*]] = lshr i32 [[TMP77]], 15
119 ; CHECK-NEXT: [[AND_I_1:%.*]] = and i32 [[SHR_I_1]], 65537
120 ; CHECK-NEXT: [[MUL_I_1:%.*]] = mul i32 [[AND_I_1]], 65535
121 ; CHECK-NEXT: [[SHR_I49_1:%.*]] = lshr i32 [[CONV_2]], 15
122 ; CHECK-NEXT: [[AND_I50_1:%.*]] = and i32 [[SHR_I49_1]], 65537
123 ; CHECK-NEXT: [[MUL_I51_1:%.*]] = mul i32 [[AND_I50_1]], 65535
124 ; CHECK-NEXT: [[TMP86:%.*]] = extractelement <2 x i32> [[TMP222]], i32 0
125 ; CHECK-NEXT: [[TMP87:%.*]] = extractelement <2 x i32> [[TMP222]], i32 1
126 ; CHECK-NEXT: [[ADD94_3:%.*]] = add i32 [[TMP86]], [[TMP87]]
127 ; CHECK-NEXT: [[ADD112_1:%.*]] = sub i32 [[TMP87]], [[TMP86]]
128 ; CHECK-NEXT: [[SHR_I49_2:%.*]] = lshr i32 [[CONV_1]], 15
129 ; CHECK-NEXT: [[AND_I50_2:%.*]] = and i32 [[SHR_I49_2]], 65537
130 ; CHECK-NEXT: [[MUL_I51_2:%.*]] = mul i32 [[AND_I50_2]], 65535
131 ; CHECK-NEXT: [[TMP88:%.*]] = extractelement <2 x i32> [[TMP85]], i32 0
132 ; CHECK-NEXT: [[TMP89:%.*]] = extractelement <2 x i32> [[TMP85]], i32 1
133 ; CHECK-NEXT: [[ADD94_4:%.*]] = add i32 [[TMP88]], [[TMP89]]
134 ; CHECK-NEXT: [[SUB102_3:%.*]] = sub i32 [[TMP89]], [[TMP88]]
135 ; CHECK-NEXT: [[SHR_I49_3:%.*]] = lshr i32 [[CONV1]], 15
136 ; CHECK-NEXT: [[AND_I50_3:%.*]] = and i32 [[SHR_I49_3]], 65537
137 ; CHECK-NEXT: [[MUL_I51_3:%.*]] = mul i32 [[AND_I50_3]], 65535
138 ; CHECK-NEXT: [[TMP90:%.*]] = load <2 x i8>, ptr [[ARRAYIDX8]], align 1
139 ; CHECK-NEXT: [[TMP102:%.*]] = zext <2 x i8> [[TMP90]] to <2 x i32>
140 ; CHECK-NEXT: [[TMP92:%.*]] = load <4 x i8>, ptr [[PIX2]], align 1
141 ; CHECK-NEXT: [[TMP93:%.*]] = shufflevector <4 x i8> [[TMP92]], <4 x i8> poison, <2 x i32> <i32 0, i32 2>
142 ; CHECK-NEXT: [[TMP94:%.*]] = zext <2 x i8> [[TMP93]] to <2 x i32>
143 ; CHECK-NEXT: [[TMP95:%.*]] = load <4 x i8>, ptr [[TMP1]], align 1
144 ; CHECK-NEXT: [[TMP96:%.*]] = shufflevector <4 x i8> [[TMP95]], <4 x i8> poison, <2 x i32> <i32 0, i32 2>
145 ; CHECK-NEXT: [[TMP97:%.*]] = zext <2 x i8> [[TMP96]] to <2 x i32>
146 ; CHECK-NEXT: [[TMP98:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5]], align 1
147 ; CHECK-NEXT: [[TMP99:%.*]] = shufflevector <4 x i8> [[TMP98]], <4 x i8> poison, <2 x i32> <i32 0, i32 2>
148 ; CHECK-NEXT: [[TMP100:%.*]] = zext <2 x i8> [[TMP99]] to <2 x i32>
149 ; CHECK-NEXT: [[TMP101:%.*]] = sub <2 x i32> [[TMP97]], [[TMP100]]
150 ; CHECK-NEXT: [[TMP224:%.*]] = shl <2 x i32> [[TMP101]], splat (i32 16)
151 ; CHECK-NEXT: [[TMP103:%.*]] = shufflevector <4 x i8> [[TMP92]], <4 x i8> poison, <2 x i32> <i32 1, i32 3>
152 ; CHECK-NEXT: [[TMP104:%.*]] = zext <2 x i8> [[TMP103]] to <2 x i32>
153 ; CHECK-NEXT: [[TMP105:%.*]] = shufflevector <4 x i8> [[TMP95]], <4 x i8> poison, <2 x i32> <i32 1, i32 3>
154 ; CHECK-NEXT: [[TMP106:%.*]] = zext <2 x i8> [[TMP105]] to <2 x i32>
155 ; CHECK-NEXT: [[TMP107:%.*]] = shufflevector <4 x i8> [[TMP98]], <4 x i8> poison, <2 x i32> <i32 1, i32 3>
156 ; CHECK-NEXT: [[TMP108:%.*]] = zext <2 x i8> [[TMP107]] to <2 x i32>
157 ; CHECK-NEXT: [[TMP109:%.*]] = sub <2 x i32> [[TMP106]], [[TMP108]]
158 ; CHECK-NEXT: [[TMP110:%.*]] = shl <2 x i32> [[TMP109]], splat (i32 16)
159 ; CHECK-NEXT: [[TMP111:%.*]] = insertelement <2 x i32> [[TMP102]], i32 [[CONV33]], i32 1
160 ; CHECK-NEXT: [[TMP112:%.*]] = sub <2 x i32> [[TMP111]], [[TMP104]]
161 ; CHECK-NEXT: [[TMP113:%.*]] = add <2 x i32> [[TMP110]], [[TMP112]]
162 ; CHECK-NEXT: [[TMP114:%.*]] = insertelement <2 x i32> [[TMP102]], i32 [[CONV1]], i32 0
163 ; CHECK-NEXT: [[TMP115:%.*]] = sub <2 x i32> [[TMP114]], [[TMP94]]
164 ; CHECK-NEXT: [[TMP116:%.*]] = add <2 x i32> [[TMP224]], [[TMP115]]
165 ; CHECK-NEXT: [[TMP117:%.*]] = shufflevector <2 x i32> [[TMP113]], <2 x i32> [[TMP116]], <2 x i32> <i32 0, i32 2>
166 ; CHECK-NEXT: [[TMP126:%.*]] = add <2 x i32> [[TMP113]], [[TMP116]]
167 ; CHECK-NEXT: [[TMP119:%.*]] = sub <2 x i32> [[TMP116]], [[TMP113]]
168 ; CHECK-NEXT: [[TMP120:%.*]] = extractelement <2 x i32> [[TMP126]], i32 0
169 ; CHECK-NEXT: [[TMP127:%.*]] = extractelement <2 x i32> [[TMP126]], i32 1
170 ; CHECK-NEXT: [[ADD48:%.*]] = add i32 [[TMP127]], [[TMP120]]
171 ; CHECK-NEXT: [[TMP166:%.*]] = sub i32 [[TMP120]], [[TMP127]]
172 ; CHECK-NEXT: [[TMP128:%.*]] = extractelement <2 x i32> [[TMP119]], i32 0
173 ; CHECK-NEXT: [[TMP129:%.*]] = extractelement <2 x i32> [[TMP119]], i32 1
174 ; CHECK-NEXT: [[ADD55:%.*]] = add i32 [[TMP129]], [[TMP128]]
175 ; CHECK-NEXT: [[SUB60:%.*]] = sub i32 [[TMP128]], [[TMP129]]
176 ; CHECK-NEXT: [[SHR_I59:%.*]] = lshr i32 [[TMP127]], 15
177 ; CHECK-NEXT: [[AND_I60:%.*]] = and i32 [[SHR_I59]], 65537
178 ; CHECK-NEXT: [[MUL_I61:%.*]] = mul i32 [[AND_I60]], 65535
179 ; CHECK-NEXT: [[SHR_I59_1:%.*]] = lshr i32 [[TMP129]], 15
180 ; CHECK-NEXT: [[AND_I60_1:%.*]] = and i32 [[SHR_I59_1]], 65537
181 ; CHECK-NEXT: [[MUL_I61_1:%.*]] = mul i32 [[AND_I60_1]], 65535
182 ; CHECK-NEXT: [[TMP130:%.*]] = load <2 x i8>, ptr [[ARRAYIDX8_1]], align 1
183 ; CHECK-NEXT: [[TMP131:%.*]] = zext <2 x i8> [[TMP130]] to <2 x i32>
184 ; CHECK-NEXT: [[TMP132:%.*]] = load <4 x i8>, ptr [[ADD_PTR644]], align 1
185 ; CHECK-NEXT: [[TMP133:%.*]] = shufflevector <4 x i8> [[TMP132]], <4 x i8> poison, <2 x i32> <i32 0, i32 2>
186 ; CHECK-NEXT: [[TMP134:%.*]] = zext <2 x i8> [[TMP133]] to <2 x i32>
187 ; CHECK-NEXT: [[TMP135:%.*]] = load <4 x i8>, ptr [[ARRAYIDX3_1]], align 1
188 ; CHECK-NEXT: [[TMP136:%.*]] = shufflevector <4 x i8> [[TMP135]], <4 x i8> poison, <2 x i32> <i32 0, i32 2>
189 ; CHECK-NEXT: [[TMP137:%.*]] = zext <2 x i8> [[TMP136]] to <2 x i32>
190 ; CHECK-NEXT: [[TMP138:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5_1]], align 1
191 ; CHECK-NEXT: [[TMP139:%.*]] = shufflevector <4 x i8> [[TMP138]], <4 x i8> poison, <2 x i32> <i32 0, i32 2>
192 ; CHECK-NEXT: [[TMP140:%.*]] = zext <2 x i8> [[TMP139]] to <2 x i32>
193 ; CHECK-NEXT: [[TMP141:%.*]] = sub <2 x i32> [[TMP137]], [[TMP140]]
194 ; CHECK-NEXT: [[TMP142:%.*]] = shl <2 x i32> [[TMP141]], splat (i32 16)
195 ; CHECK-NEXT: [[TMP143:%.*]] = shufflevector <4 x i8> [[TMP132]], <4 x i8> poison, <2 x i32> <i32 1, i32 3>
196 ; CHECK-NEXT: [[TMP144:%.*]] = zext <2 x i8> [[TMP143]] to <2 x i32>
197 ; CHECK-NEXT: [[TMP145:%.*]] = shufflevector <4 x i8> [[TMP135]], <4 x i8> poison, <2 x i32> <i32 1, i32 3>
198 ; CHECK-NEXT: [[TMP146:%.*]] = zext <2 x i8> [[TMP145]] to <2 x i32>
199 ; CHECK-NEXT: [[TMP147:%.*]] = shufflevector <4 x i8> [[TMP138]], <4 x i8> poison, <2 x i32> <i32 1, i32 3>
200 ; CHECK-NEXT: [[TMP148:%.*]] = zext <2 x i8> [[TMP147]] to <2 x i32>
201 ; CHECK-NEXT: [[TMP149:%.*]] = sub <2 x i32> [[TMP146]], [[TMP148]]
202 ; CHECK-NEXT: [[TMP150:%.*]] = shl <2 x i32> [[TMP149]], splat (i32 16)
203 ; CHECK-NEXT: [[TMP151:%.*]] = insertelement <2 x i32> [[TMP131]], i32 [[CONV33_1]], i32 1
204 ; CHECK-NEXT: [[TMP225:%.*]] = sub <2 x i32> [[TMP151]], [[TMP144]]
205 ; CHECK-NEXT: [[TMP153:%.*]] = add <2 x i32> [[TMP150]], [[TMP225]]
206 ; CHECK-NEXT: [[TMP154:%.*]] = insertelement <2 x i32> [[TMP131]], i32 [[CONV_1]], i32 0
207 ; CHECK-NEXT: [[TMP155:%.*]] = sub <2 x i32> [[TMP154]], [[TMP134]]
208 ; CHECK-NEXT: [[TMP156:%.*]] = add <2 x i32> [[TMP142]], [[TMP155]]
209 ; CHECK-NEXT: [[TMP157:%.*]] = add <2 x i32> [[TMP153]], [[TMP156]]
210 ; CHECK-NEXT: [[TMP158:%.*]] = sub <2 x i32> [[TMP156]], [[TMP153]]
211 ; CHECK-NEXT: [[TMP159:%.*]] = extractelement <2 x i32> [[TMP157]], i32 0
212 ; CHECK-NEXT: [[TMP160:%.*]] = extractelement <2 x i32> [[TMP157]], i32 1
213 ; CHECK-NEXT: [[ADD48_1:%.*]] = add i32 [[TMP160]], [[TMP159]]
214 ; CHECK-NEXT: [[SUB51_1:%.*]] = sub i32 [[TMP159]], [[TMP160]]
215 ; CHECK-NEXT: [[TMP161:%.*]] = extractelement <2 x i32> [[TMP158]], i32 0
216 ; CHECK-NEXT: [[TMP162:%.*]] = extractelement <2 x i32> [[TMP158]], i32 1
217 ; CHECK-NEXT: [[ADD55_1:%.*]] = add i32 [[TMP162]], [[TMP161]]
218 ; CHECK-NEXT: [[SUB59_2:%.*]] = sub i32 [[TMP161]], [[TMP162]]
219 ; CHECK-NEXT: [[SHR_I54:%.*]] = lshr i32 [[TMP160]], 15
220 ; CHECK-NEXT: [[AND_I55:%.*]] = and i32 [[SHR_I54]], 65537
221 ; CHECK-NEXT: [[MUL_I56:%.*]] = mul i32 [[AND_I55]], 65535
222 ; CHECK-NEXT: [[SHR_I54_1:%.*]] = lshr i32 [[TMP162]], 15
223 ; CHECK-NEXT: [[AND_I55_1:%.*]] = and i32 [[SHR_I54_1]], 65537
224 ; CHECK-NEXT: [[MUL_I56_1:%.*]] = mul i32 [[AND_I55_1]], 65535
225 ; CHECK-NEXT: [[TMP163:%.*]] = lshr <2 x i32> [[TMP131]], splat (i32 15)
226 ; CHECK-NEXT: [[TMP164:%.*]] = and <2 x i32> [[TMP163]], splat (i32 65537)
227 ; CHECK-NEXT: [[TMP165:%.*]] = mul <2 x i32> [[TMP164]], splat (i32 65535)
228 ; CHECK-NEXT: [[ADD78:%.*]] = add i32 [[ADD48_1]], [[ADD48]]
229 ; CHECK-NEXT: [[SUB86:%.*]] = sub i32 [[ADD48]], [[ADD48_1]]
230 ; CHECK-NEXT: [[ADD103:%.*]] = add i32 [[ADD95]], [[ADD78]]
231 ; CHECK-NEXT: [[SUB104:%.*]] = sub i32 [[ADD78]], [[ADD95]]
232 ; CHECK-NEXT: [[ADD105:%.*]] = add i32 [[SUB86_3]], [[SUB86]]
233 ; CHECK-NEXT: [[SUB106:%.*]] = sub i32 [[SUB86]], [[SUB86_3]]
234 ; CHECK-NEXT: [[ADD_I:%.*]] = add i32 [[MUL_I_1]], [[ADD103]]
235 ; CHECK-NEXT: [[XOR_I:%.*]] = xor i32 [[ADD_I]], [[TMP77]]
236 ; CHECK-NEXT: [[ADD_I52:%.*]] = add i32 [[MUL_I51_1]], [[ADD105]]
237 ; CHECK-NEXT: [[XOR_I53:%.*]] = xor i32 [[ADD_I52]], [[CONV_2]]
238 ; CHECK-NEXT: [[ADD_I57:%.*]] = add i32 [[MUL_I56]], [[SUB104]]
239 ; CHECK-NEXT: [[XOR_I58:%.*]] = xor i32 [[ADD_I57]], [[TMP160]]
240 ; CHECK-NEXT: [[ADD_I62:%.*]] = add i32 [[MUL_I61]], [[SUB106]]
241 ; CHECK-NEXT: [[XOR_I63:%.*]] = xor i32 [[ADD_I62]], [[TMP127]]
242 ; CHECK-NEXT: [[ADD110:%.*]] = add i32 [[XOR_I53]], [[XOR_I]]
243 ; CHECK-NEXT: [[ADD112:%.*]] = add i32 [[ADD110]], [[XOR_I58]]
244 ; CHECK-NEXT: [[ADD105_3:%.*]] = add i32 [[ADD112]], [[XOR_I63]]
245 ; CHECK-NEXT: [[TMP169:%.*]] = load <2 x i8>, ptr [[ADD_PTR_1]], align 1
246 ; CHECK-NEXT: [[TMP181:%.*]] = zext <2 x i8> [[TMP169]] to <2 x i32>
247 ; CHECK-NEXT: [[TMP152:%.*]] = insertelement <2 x i32> poison, i32 [[ADD55_2]], i32 0
248 ; CHECK-NEXT: [[TMP182:%.*]] = shufflevector <2 x i32> [[TMP152]], <2 x i32> poison, <2 x i32> zeroinitializer
249 ; CHECK-NEXT: [[TMP183:%.*]] = insertelement <2 x i32> poison, i32 [[ADD55_3]], i32 0
250 ; CHECK-NEXT: [[TMP184:%.*]] = shufflevector <2 x i32> [[TMP183]], <2 x i32> poison, <2 x i32> zeroinitializer
251 ; CHECK-NEXT: [[TMP191:%.*]] = sub <2 x i32> [[TMP182]], [[TMP184]]
252 ; CHECK-NEXT: [[TMP192:%.*]] = add <2 x i32> [[TMP182]], [[TMP184]]
253 ; CHECK-NEXT: [[TMP194:%.*]] = shufflevector <2 x i32> [[TMP191]], <2 x i32> [[TMP192]], <2 x i32> <i32 0, i32 3>
254 ; CHECK-NEXT: [[TMP195:%.*]] = lshr <2 x i32> [[TMP181]], splat (i32 15)
255 ; CHECK-NEXT: [[TMP196:%.*]] = and <2 x i32> [[TMP195]], splat (i32 65537)
256 ; CHECK-NEXT: [[TMP198:%.*]] = mul <2 x i32> [[TMP196]], splat (i32 65535)
257 ; CHECK-NEXT: [[TMP202:%.*]] = insertelement <2 x i32> poison, i32 [[ADD55]], i32 0
258 ; CHECK-NEXT: [[TMP203:%.*]] = shufflevector <2 x i32> [[TMP202]], <2 x i32> poison, <2 x i32> zeroinitializer
259 ; CHECK-NEXT: [[TMP205:%.*]] = insertelement <2 x i32> poison, i32 [[ADD55_1]], i32 0
260 ; CHECK-NEXT: [[TMP206:%.*]] = shufflevector <2 x i32> [[TMP205]], <2 x i32> poison, <2 x i32> zeroinitializer
261 ; CHECK-NEXT: [[TMP207:%.*]] = sub <2 x i32> [[TMP203]], [[TMP206]]
262 ; CHECK-NEXT: [[TMP210:%.*]] = add <2 x i32> [[TMP203]], [[TMP206]]
263 ; CHECK-NEXT: [[TMP168:%.*]] = shufflevector <2 x i32> [[TMP207]], <2 x i32> [[TMP210]], <2 x i32> <i32 0, i32 3>
264 ; CHECK-NEXT: [[ADD94_1:%.*]] = extractelement <2 x i32> [[TMP194]], i32 1
265 ; CHECK-NEXT: [[ADD78_1:%.*]] = extractelement <2 x i32> [[TMP168]], i32 1
266 ; CHECK-NEXT: [[SUB104_1:%.*]] = sub i32 [[ADD78_1]], [[ADD94_1]]
267 ; CHECK-NEXT: [[TMP220:%.*]] = add <2 x i32> [[TMP194]], [[TMP168]]
268 ; CHECK-NEXT: [[SUB102_1:%.*]] = extractelement <2 x i32> [[TMP194]], i32 0
269 ; CHECK-NEXT: [[SUB86_1:%.*]] = extractelement <2 x i32> [[TMP168]], i32 0
270 ; CHECK-NEXT: [[TMP174:%.*]] = shufflevector <2 x i32> [[TMP168]], <2 x i32> [[TMP194]], <2 x i32> <i32 0, i32 2>
271 ; CHECK-NEXT: [[SUB106_1:%.*]] = sub i32 [[SUB86_1]], [[SUB102_1]]
272 ; CHECK-NEXT: [[TMP175:%.*]] = add <2 x i32> [[TMP198]], [[TMP220]]
273 ; CHECK-NEXT: [[TMP221:%.*]] = xor <2 x i32> [[TMP175]], [[TMP181]]
274 ; CHECK-NEXT: [[ADD_I57_1:%.*]] = add i32 [[MUL_I56_1]], [[SUB104_1]]
275 ; CHECK-NEXT: [[XOR_I58_1:%.*]] = xor i32 [[ADD_I57_1]], [[TMP162]]
276 ; CHECK-NEXT: [[ADD_I62_1:%.*]] = add i32 [[MUL_I61_1]], [[SUB106_1]]
277 ; CHECK-NEXT: [[XOR_I63_1:%.*]] = xor i32 [[ADD_I62_1]], [[TMP129]]
278 ; CHECK-NEXT: [[XOR_I53_1:%.*]] = extractelement <2 x i32> [[TMP221]], i32 0
279 ; CHECK-NEXT: [[ADD108_1:%.*]] = add i32 [[XOR_I53_1]], [[ADD105_3]]
280 ; CHECK-NEXT: [[XOR_I_1:%.*]] = extractelement <2 x i32> [[TMP221]], i32 1
281 ; CHECK-NEXT: [[ADD110_1:%.*]] = add i32 [[ADD108_1]], [[XOR_I_1]]
282 ; CHECK-NEXT: [[ADD112_5:%.*]] = add i32 [[ADD110_1]], [[XOR_I58_1]]
283 ; CHECK-NEXT: [[ADD113_2:%.*]] = add i32 [[ADD112_5]], [[XOR_I63_1]]
284 ; CHECK-NEXT: [[ADD78_3:%.*]] = add i32 [[SUB51_1]], [[TMP166]]
285 ; CHECK-NEXT: [[TMP204:%.*]] = sub i32 [[TMP166]], [[SUB51_1]]
286 ; CHECK-NEXT: [[TMP177:%.*]] = insertelement <2 x i32> poison, i32 [[ADD78_3]], i32 0
287 ; CHECK-NEXT: [[TMP178:%.*]] = shufflevector <2 x i32> [[TMP177]], <2 x i32> poison, <2 x i32> zeroinitializer
288 ; CHECK-NEXT: [[TMP179:%.*]] = insertelement <2 x i32> poison, i32 [[ADD94_3]], i32 0
289 ; CHECK-NEXT: [[TMP180:%.*]] = shufflevector <2 x i32> [[TMP179]], <2 x i32> poison, <2 x i32> zeroinitializer
290 ; CHECK-NEXT: [[TMP199:%.*]] = add <2 x i32> [[TMP178]], [[TMP180]]
291 ; CHECK-NEXT: [[TMP200:%.*]] = sub <2 x i32> [[TMP178]], [[TMP180]]
292 ; CHECK-NEXT: [[TMP201:%.*]] = shufflevector <2 x i32> [[TMP199]], <2 x i32> [[TMP200]], <2 x i32> <i32 0, i32 3>
293 ; CHECK-NEXT: [[ADD113_1:%.*]] = add i32 [[ADD112_1]], [[TMP204]]
294 ; CHECK-NEXT: [[SUB106_2:%.*]] = sub i32 [[TMP204]], [[ADD112_1]]
295 ; CHECK-NEXT: [[ADD_I52_2:%.*]] = add i32 [[MUL_I51_2]], [[ADD113_1]]
296 ; CHECK-NEXT: [[XOR_I53_2:%.*]] = xor i32 [[ADD_I52_2]], [[CONV_1]]
297 ; CHECK-NEXT: [[TMP208:%.*]] = add <2 x i32> [[TMP165]], [[TMP201]]
298 ; CHECK-NEXT: [[TMP209:%.*]] = xor <2 x i32> [[TMP208]], [[TMP131]]
299 ; CHECK-NEXT: [[SHR_I59_2:%.*]] = lshr i32 [[TMP120]], 15
300 ; CHECK-NEXT: [[AND_I60_2:%.*]] = and i32 [[SHR_I59_2]], 65537
301 ; CHECK-NEXT: [[MUL_I61_2:%.*]] = mul i32 [[AND_I60_2]], 65535
302 ; CHECK-NEXT: [[ADD_I62_2:%.*]] = add i32 [[MUL_I61_2]], [[SUB106_2]]
303 ; CHECK-NEXT: [[XOR_I63_4:%.*]] = xor i32 [[ADD_I62_2]], [[TMP120]]
304 ; CHECK-NEXT: [[ADD108_2:%.*]] = add i32 [[XOR_I53_2]], [[ADD113_2]]
305 ; CHECK-NEXT: [[TMP211:%.*]] = extractelement <2 x i32> [[TMP209]], i32 0
306 ; CHECK-NEXT: [[ADD110_2:%.*]] = add i32 [[ADD108_2]], [[TMP211]]
307 ; CHECK-NEXT: [[TMP212:%.*]] = extractelement <2 x i32> [[TMP209]], i32 1
308 ; CHECK-NEXT: [[ADD112_4:%.*]] = add i32 [[ADD110_2]], [[TMP212]]
309 ; CHECK-NEXT: [[ADD113_4:%.*]] = add i32 [[ADD112_4]], [[XOR_I63_4]]
310 ; CHECK-NEXT: [[ADD78_4:%.*]] = add i32 [[SUB59_2]], [[SUB60]]
311 ; CHECK-NEXT: [[SUB86_4:%.*]] = sub i32 [[SUB60]], [[SUB59_2]]
312 ; CHECK-NEXT: [[TMP213:%.*]] = insertelement <2 x i32> poison, i32 [[ADD78_4]], i32 0
313 ; CHECK-NEXT: [[TMP214:%.*]] = shufflevector <2 x i32> [[TMP213]], <2 x i32> poison, <2 x i32> zeroinitializer
314 ; CHECK-NEXT: [[TMP215:%.*]] = insertelement <2 x i32> poison, i32 [[ADD94_4]], i32 0
315 ; CHECK-NEXT: [[TMP216:%.*]] = shufflevector <2 x i32> [[TMP215]], <2 x i32> poison, <2 x i32> zeroinitializer
316 ; CHECK-NEXT: [[TMP217:%.*]] = add <2 x i32> [[TMP214]], [[TMP216]]
317 ; CHECK-NEXT: [[TMP218:%.*]] = sub <2 x i32> [[TMP214]], [[TMP216]]
318 ; CHECK-NEXT: [[TMP219:%.*]] = shufflevector <2 x i32> [[TMP217]], <2 x i32> [[TMP218]], <2 x i32> <i32 0, i32 3>
319 ; CHECK-NEXT: [[ADD105_4:%.*]] = add i32 [[SUB102_3]], [[SUB86_4]]
320 ; CHECK-NEXT: [[SUB106_3:%.*]] = sub i32 [[SUB86_4]], [[SUB102_3]]
321 ; CHECK-NEXT: [[ADD_I52_4:%.*]] = add i32 [[MUL_I51_3]], [[ADD105_4]]
322 ; CHECK-NEXT: [[XOR_I53_3:%.*]] = xor i32 [[ADD_I52_4]], [[CONV1]]
323 ; CHECK-NEXT: [[TMP185:%.*]] = lshr <2 x i32> [[TMP102]], splat (i32 15)
324 ; CHECK-NEXT: [[TMP193:%.*]] = and <2 x i32> [[TMP185]], splat (i32 65537)
325 ; CHECK-NEXT: [[TMP186:%.*]] = mul <2 x i32> [[TMP193]], splat (i32 65535)
326 ; CHECK-NEXT: [[TMP187:%.*]] = add <2 x i32> [[TMP186]], [[TMP219]]
327 ; CHECK-NEXT: [[TMP188:%.*]] = xor <2 x i32> [[TMP187]], [[TMP102]]
328 ; CHECK-NEXT: [[SHR_I59_3:%.*]] = lshr i32 [[CONV33]], 15
329 ; CHECK-NEXT: [[AND_I60_3:%.*]] = and i32 [[SHR_I59_3]], 65537
330 ; CHECK-NEXT: [[MUL_I61_3:%.*]] = mul i32 [[AND_I60_3]], 65535
331 ; CHECK-NEXT: [[ADD_I62_3:%.*]] = add i32 [[MUL_I61_3]], [[SUB106_3]]
332 ; CHECK-NEXT: [[XOR_I63_3:%.*]] = xor i32 [[ADD_I62_3]], [[CONV33]]
333 ; CHECK-NEXT: [[ADD108_3:%.*]] = add i32 [[XOR_I53_3]], [[ADD113_4]]
334 ; CHECK-NEXT: [[TMP189:%.*]] = extractelement <2 x i32> [[TMP188]], i32 0
335 ; CHECK-NEXT: [[ADD110_3:%.*]] = add i32 [[ADD108_3]], [[TMP189]]
336 ; CHECK-NEXT: [[TMP190:%.*]] = extractelement <2 x i32> [[TMP188]], i32 1
337 ; CHECK-NEXT: [[ADD112_3:%.*]] = add i32 [[ADD110_3]], [[TMP190]]
338 ; CHECK-NEXT: [[ADD113_3:%.*]] = add i32 [[ADD112_3]], [[XOR_I63_3]]
339 ; CHECK-NEXT: ret i32 [[ADD113_3]]
340 ;
341 ; THR15-LABEL: define i32 @test(
342 ; THR15-SAME: ptr [[PIX1:%.*]], ptr [[PIX2:%.*]], i64 [[IDX_EXT:%.*]], i64 [[IDX_EXT63:%.*]], ptr [[ADD_PTR:%.*]], ptr [[ADD_PTR64:%.*]]) #[[ATTR0:[0-9]+]] {
343 ; THR15-NEXT: entry:
344 ; THR15-NEXT: [[TMP0:%.*]] = load i8, ptr [[PIX1]], align 1
345 ; THR15-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32
346 ; THR15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr i8, ptr [[PIX1]], i64 4
347 ; THR15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr i8, ptr [[PIX2]], i64 4
348 ; THR15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr i8, ptr [[PIX1]], i64 1
349 ; THR15-NEXT: [[ARRAYIDX32:%.*]] = getelementptr i8, ptr [[PIX1]], i64 3
350 ; THR15-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX32]], align 1
351 ; THR15-NEXT: [[CONV33:%.*]] = zext i8 [[TMP1]] to i32
352 ; THR15-NEXT: [[ADD_PTR3:%.*]] = getelementptr i8, ptr [[PIX1]], i64 [[IDX_EXT]]
353 ; THR15-NEXT: [[ADD_PTR644:%.*]] = getelementptr i8, ptr [[PIX2]], i64 [[IDX_EXT63]]
354 ; THR15-NEXT: [[TMP2:%.*]] = load i8, ptr [[ADD_PTR3]], align 1
355 ; THR15-NEXT: [[CONV_1:%.*]] = zext i8 [[TMP2]] to i32
356 ; THR15-NEXT: [[ARRAYIDX3_1:%.*]] = getelementptr i8, ptr [[ADD_PTR3]], i64 4
357 ; THR15-NEXT: [[ARRAYIDX5_1:%.*]] = getelementptr i8, ptr [[ADD_PTR644]], i64 4
358 ; THR15-NEXT: [[ARRAYIDX8_1:%.*]] = getelementptr i8, ptr [[ADD_PTR3]], i64 1
359 ; THR15-NEXT: [[ARRAYIDX27_1:%.*]] = getelementptr i8, ptr [[ADD_PTR3]], i64 3
360 ; THR15-NEXT: [[TMP5:%.*]] = load i8, ptr [[ARRAYIDX27_1]], align 1
361 ; THR15-NEXT: [[CONV33_1:%.*]] = zext i8 [[TMP5]] to i32
362 ; THR15-NEXT: [[ADD_PTR_1:%.*]] = getelementptr i8, ptr [[ADD_PTR]], i64 [[IDX_EXT]]
363 ; THR15-NEXT: [[ADD_PTR64_1:%.*]] = getelementptr i8, ptr [[ADD_PTR64]], i64 [[IDX_EXT63]]
364 ; THR15-NEXT: [[ARRAYIDX3_2:%.*]] = getelementptr i8, ptr [[ADD_PTR_1]], i64 4
365 ; THR15-NEXT: [[ARRAYIDX5_2:%.*]] = getelementptr i8, ptr [[ADD_PTR64_1]], i64 4
366 ; THR15-NEXT: [[ARRAYIDX8_2:%.*]] = getelementptr i8, ptr [[ADD_PTR_1]], i64 1
367 ; THR15-NEXT: [[TMP4:%.*]] = load <4 x i8>, ptr [[ADD_PTR_1]], align 1
368 ; THR15-NEXT: [[TMP7:%.*]] = load i8, ptr [[ARRAYIDX8_2]], align 1
369 ; THR15-NEXT: [[TMP6:%.*]] = load i8, ptr [[ADD_PTR_1]], align 1
370 ; THR15-NEXT: [[TMP19:%.*]] = shufflevector <4 x i8> [[TMP4]], <4 x i8> poison, <2 x i32> <i32 0, i32 2>
371 ; THR15-NEXT: [[TMP20:%.*]] = zext <2 x i8> [[TMP19]] to <2 x i32>
372 ; THR15-NEXT: [[TMP87:%.*]] = zext i8 [[TMP6]] to i32
373 ; THR15-NEXT: [[TMP9:%.*]] = load <4 x i8>, ptr [[ADD_PTR64_1]], align 1
374 ; THR15-NEXT: [[TMP21:%.*]] = shufflevector <4 x i8> [[TMP9]], <4 x i8> poison, <2 x i32> <i32 0, i32 2>
375 ; THR15-NEXT: [[TMP22:%.*]] = zext <2 x i8> [[TMP21]] to <2 x i32>
376 ; THR15-NEXT: [[TMP23:%.*]] = sub <2 x i32> [[TMP20]], [[TMP22]]
377 ; THR15-NEXT: [[TMP13:%.*]] = load <4 x i8>, ptr [[ARRAYIDX3_2]], align 1
378 ; THR15-NEXT: [[TMP24:%.*]] = shufflevector <4 x i8> [[TMP13]], <4 x i8> poison, <2 x i32> <i32 0, i32 2>
379 ; THR15-NEXT: [[TMP25:%.*]] = zext <2 x i8> [[TMP24]] to <2 x i32>
380 ; THR15-NEXT: [[TMP16:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5_2]], align 1
381 ; THR15-NEXT: [[TMP26:%.*]] = shufflevector <4 x i8> [[TMP16]], <4 x i8> poison, <2 x i32> <i32 0, i32 2>
382 ; THR15-NEXT: [[TMP27:%.*]] = zext <2 x i8> [[TMP26]] to <2 x i32>
383 ; THR15-NEXT: [[TMP28:%.*]] = sub <2 x i32> [[TMP25]], [[TMP27]]
384 ; THR15-NEXT: [[TMP29:%.*]] = shl <2 x i32> [[TMP28]], splat (i32 16)
385 ; THR15-NEXT: [[TMP59:%.*]] = add <2 x i32> [[TMP29]], [[TMP23]]
386 ; THR15-NEXT: [[TMP31:%.*]] = shufflevector <4 x i8> [[TMP4]], <4 x i8> poison, <2 x i32> <i32 1, i32 3>
387 ; THR15-NEXT: [[TMP32:%.*]] = zext <2 x i8> [[TMP31]] to <2 x i32>
388 ; THR15-NEXT: [[TMP86:%.*]] = zext i8 [[TMP7]] to i32
389 ; THR15-NEXT: [[TMP33:%.*]] = shufflevector <4 x i8> [[TMP9]], <4 x i8> poison, <2 x i32> <i32 1, i32 3>
390 ; THR15-NEXT: [[TMP34:%.*]] = zext <2 x i8> [[TMP33]] to <2 x i32>
391 ; THR15-NEXT: [[TMP35:%.*]] = sub <2 x i32> [[TMP32]], [[TMP34]]
392 ; THR15-NEXT: [[TMP36:%.*]] = shufflevector <4 x i8> [[TMP13]], <4 x i8> poison, <2 x i32> <i32 1, i32 3>
393 ; THR15-NEXT: [[TMP37:%.*]] = zext <2 x i8> [[TMP36]] to <2 x i32>
394 ; THR15-NEXT: [[TMP38:%.*]] = shufflevector <4 x i8> [[TMP16]], <4 x i8> poison, <2 x i32> <i32 1, i32 3>
395 ; THR15-NEXT: [[TMP39:%.*]] = zext <2 x i8> [[TMP38]] to <2 x i32>
396 ; THR15-NEXT: [[TMP40:%.*]] = sub <2 x i32> [[TMP37]], [[TMP39]]
397 ; THR15-NEXT: [[TMP41:%.*]] = shl <2 x i32> [[TMP40]], splat (i32 16)
398 ; THR15-NEXT: [[TMP76:%.*]] = add <2 x i32> [[TMP41]], [[TMP35]]
399 ; THR15-NEXT: [[TMP30:%.*]] = add <2 x i32> [[TMP76]], [[TMP59]]
400 ; THR15-NEXT: [[TMP42:%.*]] = sub <2 x i32> [[TMP59]], [[TMP76]]
401 ; THR15-NEXT: [[TMP43:%.*]] = extractelement <2 x i32> [[TMP30]], i32 0
402 ; THR15-NEXT: [[TMP44:%.*]] = extractelement <2 x i32> [[TMP30]], i32 1
403 ; THR15-NEXT: [[ADD44_2:%.*]] = add i32 [[TMP44]], [[TMP43]]
404 ; THR15-NEXT: [[TMP45:%.*]] = extractelement <2 x i32> [[TMP42]], i32 0
405 ; THR15-NEXT: [[TMP46:%.*]] = extractelement <2 x i32> [[TMP42]], i32 1
406 ; THR15-NEXT: [[ADD46_2:%.*]] = add i32 [[TMP46]], [[TMP45]]
407 ; THR15-NEXT: [[ARRAYIDX5_3:%.*]] = getelementptr i8, ptr null, i64 4
408 ; THR15-NEXT: [[TMP47:%.*]] = load <2 x i8>, ptr null, align 1
409 ; THR15-NEXT: [[TMP48:%.*]] = load i8, ptr null, align 1
410 ; THR15-NEXT: [[TMP49:%.*]] = zext <2 x i8> [[TMP47]] to <2 x i32>
411 ; THR15-NEXT: [[CONV_3:%.*]] = zext i8 [[TMP48]] to i32
412 ; THR15-NEXT: [[TMP50:%.*]] = load <2 x i8>, ptr null, align 1
413 ; THR15-NEXT: [[TMP51:%.*]] = zext <2 x i8> [[TMP50]] to <2 x i32>
414 ; THR15-NEXT: [[TMP52:%.*]] = sub <2 x i32> [[TMP49]], [[TMP51]]
415 ; THR15-NEXT: [[TMP53:%.*]] = call <2 x i8> @llvm.experimental.vp.strided.load.v2i8.p0.i64(ptr align 1 null, i64 4, <2 x i1> splat (i1 true), i32 2)
416 ; THR15-NEXT: [[TMP54:%.*]] = zext <2 x i8> [[TMP53]] to <2 x i32>
417 ; THR15-NEXT: [[TMP77:%.*]] = shufflevector <2 x i32> [[TMP54]], <2 x i32> poison, <2 x i32> <i32 1, i32 0>
418 ; THR15-NEXT: [[TMP55:%.*]] = load <2 x i8>, ptr [[ARRAYIDX5_3]], align 1
419 ; THR15-NEXT: [[TMP56:%.*]] = zext <2 x i8> [[TMP55]] to <2 x i32>
420 ; THR15-NEXT: [[TMP57:%.*]] = sub <2 x i32> [[TMP77]], [[TMP56]]
421 ; THR15-NEXT: [[TMP58:%.*]] = shl <2 x i32> [[TMP57]], splat (i32 16)
422 ; THR15-NEXT: [[TMP72:%.*]] = add <2 x i32> [[TMP58]], [[TMP52]]
423 ; THR15-NEXT: [[ARRAYIDX20_3:%.*]] = getelementptr i8, ptr null, i64 2
424 ; THR15-NEXT: [[ARRAYIDX22_3:%.*]] = getelementptr i8, ptr null, i64 2
425 ; THR15-NEXT: [[ARRAYIDX27_3:%.*]] = getelementptr i8, ptr null, i64 6
426 ; THR15-NEXT: [[TMP60:%.*]] = load <2 x i8>, ptr [[ARRAYIDX20_3]], align 1
427 ; THR15-NEXT: [[TMP61:%.*]] = zext <2 x i8> [[TMP60]] to <2 x i32>
428 ; THR15-NEXT: [[TMP62:%.*]] = load <2 x i8>, ptr [[ARRAYIDX22_3]], align 1
429 ; THR15-NEXT: [[TMP63:%.*]] = zext <2 x i8> [[TMP62]] to <2 x i32>
430 ; THR15-NEXT: [[TMP64:%.*]] = sub <2 x i32> [[TMP61]], [[TMP63]]
431 ; THR15-NEXT: [[TMP65:%.*]] = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> zeroinitializer, i32 1, <2 x i1> splat (i1 true), <2 x i8> poison)
432 ; THR15-NEXT: [[TMP66:%.*]] = zext <2 x i8> [[TMP65]] to <2 x i32>
433 ; THR15-NEXT: [[TMP67:%.*]] = load <2 x i8>, ptr [[ARRAYIDX27_3]], align 1
434 ; THR15-NEXT: [[TMP68:%.*]] = zext <2 x i8> [[TMP67]] to <2 x i32>
435 ; THR15-NEXT: [[TMP69:%.*]] = sub <2 x i32> [[TMP66]], [[TMP68]]
436 ; THR15-NEXT: [[TMP70:%.*]] = shl <2 x i32> [[TMP69]], splat (i32 16)
437 ; THR15-NEXT: [[TMP73:%.*]] = add <2 x i32> [[TMP70]], [[TMP64]]
438 ; THR15-NEXT: [[TMP74:%.*]] = extractelement <2 x i32> [[TMP72]], i32 0
439 ; THR15-NEXT: [[TMP75:%.*]] = extractelement <2 x i32> [[TMP72]], i32 1
440 ; THR15-NEXT: [[ADD48_3:%.*]] = add i32 [[TMP75]], [[TMP74]]
441 ; THR15-NEXT: [[SUB45_3:%.*]] = sub i32 [[TMP74]], [[TMP75]]
442 ; THR15-NEXT: [[TMP80:%.*]] = extractelement <2 x i32> [[TMP73]], i32 0
443 ; THR15-NEXT: [[TMP81:%.*]] = extractelement <2 x i32> [[TMP73]], i32 1
444 ; THR15-NEXT: [[ADD55_3:%.*]] = add i32 [[TMP81]], [[TMP80]]
445 ; THR15-NEXT: [[SUB47_3:%.*]] = sub i32 [[TMP80]], [[TMP81]]
446 ; THR15-NEXT: [[ADD48_4:%.*]] = add i32 [[ADD55_3]], [[ADD48_3]]
447 ; THR15-NEXT: [[TMP78:%.*]] = shufflevector <2 x i32> [[TMP30]], <2 x i32> poison, <2 x i32> <i32 poison, i32 0>
448 ; THR15-NEXT: [[TMP71:%.*]] = insertelement <2 x i32> [[TMP78]], i32 [[ADD48_3]], i32 0
449 ; THR15-NEXT: [[TMP83:%.*]] = insertelement <2 x i32> [[TMP30]], i32 [[ADD55_3]], i32 0
450 ; THR15-NEXT: [[TMP79:%.*]] = sub <2 x i32> [[TMP71]], [[TMP83]]
451 ; THR15-NEXT: [[ADD55_4:%.*]] = add i32 [[SUB47_3]], [[SUB45_3]]
452 ; THR15-NEXT: [[TMP137:%.*]] = shufflevector <2 x i32> [[TMP42]], <2 x i32> poison, <2 x i32> <i32 poison, i32 0>
453 ; THR15-NEXT: [[TMP82:%.*]] = insertelement <2 x i32> [[TMP137]], i32 [[SUB45_3]], i32 0
454 ; THR15-NEXT: [[TMP84:%.*]] = insertelement <2 x i32> [[TMP42]], i32 [[SUB47_3]], i32 0
455 ; THR15-NEXT: [[TMP85:%.*]] = sub <2 x i32> [[TMP82]], [[TMP84]]
456 ; THR15-NEXT: [[ADD94:%.*]] = add i32 [[ADD48_4]], [[ADD44_2]]
457 ; THR15-NEXT: [[SUB102:%.*]] = sub i32 [[ADD44_2]], [[ADD48_4]]
458 ; THR15-NEXT: [[SHR_I:%.*]] = lshr i32 [[CONV_3]], 15
459 ; THR15-NEXT: [[AND_I:%.*]] = and i32 [[SHR_I]], 65537
460 ; THR15-NEXT: [[MUL_I:%.*]] = mul i32 [[AND_I]], 65535
461 ; THR15-NEXT: [[SHR_I49:%.*]] = lshr i32 [[TMP44]], 15
462 ; THR15-NEXT: [[AND_I50:%.*]] = and i32 [[SHR_I49]], 65537
463 ; THR15-NEXT: [[MUL_I51:%.*]] = mul i32 [[AND_I50]], 65535
464 ; THR15-NEXT: [[ADD94_1:%.*]] = add i32 [[ADD55_4]], [[ADD46_2]]
465 ; THR15-NEXT: [[SUB102_1:%.*]] = sub i32 [[ADD46_2]], [[ADD55_4]]
466 ; THR15-NEXT: [[SHR_I_1:%.*]] = lshr i32 [[TMP86]], 15
467 ; THR15-NEXT: [[AND_I_1:%.*]] = and i32 [[SHR_I_1]], 65537
468 ; THR15-NEXT: [[MUL_I_1:%.*]] = mul i32 [[AND_I_1]], 65535
469 ; THR15-NEXT: [[SHR_I49_1:%.*]] = lshr i32 [[TMP87]], 15
470 ; THR15-NEXT: [[AND_I50_1:%.*]] = and i32 [[SHR_I49_1]], 65537
471 ; THR15-NEXT: [[MUL_I51_1:%.*]] = mul i32 [[AND_I50_1]], 65535
472 ; THR15-NEXT: [[TMP88:%.*]] = extractelement <2 x i32> [[TMP79]], i32 0
473 ; THR15-NEXT: [[TMP89:%.*]] = extractelement <2 x i32> [[TMP79]], i32 1
474 ; THR15-NEXT: [[ADD94_2:%.*]] = add i32 [[TMP88]], [[TMP89]]
475 ; THR15-NEXT: [[SUB102_2:%.*]] = sub i32 [[TMP89]], [[TMP88]]
476 ; THR15-NEXT: [[SHR_I49_2:%.*]] = lshr i32 [[CONV_1]], 15
477 ; THR15-NEXT: [[AND_I50_2:%.*]] = and i32 [[SHR_I49_2]], 65537
478 ; THR15-NEXT: [[MUL_I51_2:%.*]] = mul i32 [[AND_I50_2]], 65535
479 ; THR15-NEXT: [[TMP90:%.*]] = extractelement <2 x i32> [[TMP85]], i32 0
480 ; THR15-NEXT: [[TMP91:%.*]] = extractelement <2 x i32> [[TMP85]], i32 1
481 ; THR15-NEXT: [[ADD94_3:%.*]] = add i32 [[TMP90]], [[TMP91]]
482 ; THR15-NEXT: [[SUB102_3:%.*]] = sub i32 [[TMP91]], [[TMP90]]
483 ; THR15-NEXT: [[SHR_I49_3:%.*]] = lshr i32 [[CONV]], 15
484 ; THR15-NEXT: [[AND_I50_3:%.*]] = and i32 [[SHR_I49_3]], 65537
485 ; THR15-NEXT: [[MUL_I51_3:%.*]] = mul i32 [[AND_I50_3]], 65535
486 ; THR15-NEXT: [[TMP92:%.*]] = load <2 x i8>, ptr [[ARRAYIDX8]], align 1
487 ; THR15-NEXT: [[TMP93:%.*]] = zext <2 x i8> [[TMP92]] to <2 x i32>
488 ; THR15-NEXT: [[TMP143:%.*]] = load <4 x i8>, ptr [[PIX2]], align 1
489 ; THR15-NEXT: [[TMP94:%.*]] = shufflevector <4 x i8> [[TMP143]], <4 x i8> poison, <2 x i32> <i32 0, i32 2>
490 ; THR15-NEXT: [[TMP95:%.*]] = zext <2 x i8> [[TMP94]] to <2 x i32>
491 ; THR15-NEXT: [[TMP146:%.*]] = load <4 x i8>, ptr [[ARRAYIDX3]], align 1
492 ; THR15-NEXT: [[TMP96:%.*]] = shufflevector <4 x i8> [[TMP146]], <4 x i8> poison, <2 x i32> <i32 0, i32 2>
493 ; THR15-NEXT: [[TMP97:%.*]] = zext <2 x i8> [[TMP96]] to <2 x i32>
494 ; THR15-NEXT: [[TMP147:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5]], align 1
495 ; THR15-NEXT: [[TMP98:%.*]] = shufflevector <4 x i8> [[TMP147]], <4 x i8> poison, <2 x i32> <i32 0, i32 2>
496 ; THR15-NEXT: [[TMP99:%.*]] = zext <2 x i8> [[TMP98]] to <2 x i32>
497 ; THR15-NEXT: [[TMP100:%.*]] = sub <2 x i32> [[TMP97]], [[TMP99]]
498 ; THR15-NEXT: [[TMP101:%.*]] = shl <2 x i32> [[TMP100]], splat (i32 16)
499 ; THR15-NEXT: [[TMP102:%.*]] = shufflevector <4 x i8> [[TMP143]], <4 x i8> poison, <2 x i32> <i32 1, i32 3>
500 ; THR15-NEXT: [[TMP103:%.*]] = zext <2 x i8> [[TMP102]] to <2 x i32>
501 ; THR15-NEXT: [[TMP104:%.*]] = shufflevector <4 x i8> [[TMP146]], <4 x i8> poison, <2 x i32> <i32 1, i32 3>
502 ; THR15-NEXT: [[TMP105:%.*]] = zext <2 x i8> [[TMP104]] to <2 x i32>
503 ; THR15-NEXT: [[TMP106:%.*]] = shufflevector <4 x i8> [[TMP147]], <4 x i8> poison, <2 x i32> <i32 1, i32 3>
504 ; THR15-NEXT: [[TMP107:%.*]] = zext <2 x i8> [[TMP106]] to <2 x i32>
505 ; THR15-NEXT: [[TMP108:%.*]] = sub <2 x i32> [[TMP105]], [[TMP107]]
506 ; THR15-NEXT: [[TMP109:%.*]] = shl <2 x i32> [[TMP108]], splat (i32 16)
507 ; THR15-NEXT: [[TMP110:%.*]] = insertelement <2 x i32> [[TMP93]], i32 [[CONV33]], i32 1
508 ; THR15-NEXT: [[TMP111:%.*]] = sub <2 x i32> [[TMP110]], [[TMP103]]
509 ; THR15-NEXT: [[TMP112:%.*]] = add <2 x i32> [[TMP109]], [[TMP111]]
510 ; THR15-NEXT: [[TMP113:%.*]] = insertelement <2 x i32> [[TMP93]], i32 [[CONV]], i32 0
511 ; THR15-NEXT: [[TMP114:%.*]] = sub <2 x i32> [[TMP113]], [[TMP95]]
512 ; THR15-NEXT: [[TMP115:%.*]] = add <2 x i32> [[TMP101]], [[TMP114]]
513 ; THR15-NEXT: [[TMP116:%.*]] = shufflevector <2 x i32> [[TMP112]], <2 x i32> [[TMP115]], <2 x i32> <i32 0, i32 2>
514 ; THR15-NEXT: [[TMP117:%.*]] = add <2 x i32> [[TMP112]], [[TMP115]]
515 ; THR15-NEXT: [[TMP118:%.*]] = sub <2 x i32> [[TMP115]], [[TMP112]]
516 ; THR15-NEXT: [[TMP119:%.*]] = extractelement <2 x i32> [[TMP117]], i32 0
517 ; THR15-NEXT: [[TMP120:%.*]] = extractelement <2 x i32> [[TMP117]], i32 1
518 ; THR15-NEXT: [[ADD48:%.*]] = add i32 [[TMP120]], [[TMP119]]
519 ; THR15-NEXT: [[SUB51:%.*]] = sub i32 [[TMP119]], [[TMP120]]
520 ; THR15-NEXT: [[TMP121:%.*]] = extractelement <2 x i32> [[TMP118]], i32 0
521 ; THR15-NEXT: [[TMP122:%.*]] = extractelement <2 x i32> [[TMP118]], i32 1
522 ; THR15-NEXT: [[ADD55:%.*]] = add i32 [[TMP122]], [[TMP121]]
523 ; THR15-NEXT: [[SUB59:%.*]] = sub i32 [[TMP121]], [[TMP122]]
524 ; THR15-NEXT: [[SHR_I59:%.*]] = lshr i32 [[TMP120]], 15
525 ; THR15-NEXT: [[AND_I60:%.*]] = and i32 [[SHR_I59]], 65537
526 ; THR15-NEXT: [[MUL_I61:%.*]] = mul i32 [[AND_I60]], 65535
527 ; THR15-NEXT: [[SHR_I59_1:%.*]] = lshr i32 [[TMP122]], 15
528 ; THR15-NEXT: [[AND_I60_1:%.*]] = and i32 [[SHR_I59_1]], 65537
529 ; THR15-NEXT: [[MUL_I61_1:%.*]] = mul i32 [[AND_I60_1]], 65535
530 ; THR15-NEXT: [[TMP123:%.*]] = load <2 x i8>, ptr [[ARRAYIDX8_1]], align 1
531 ; THR15-NEXT: [[TMP124:%.*]] = zext <2 x i8> [[TMP123]] to <2 x i32>
532 ; THR15-NEXT: [[TMP148:%.*]] = load <4 x i8>, ptr [[ADD_PTR644]], align 1
533 ; THR15-NEXT: [[TMP125:%.*]] = shufflevector <4 x i8> [[TMP148]], <4 x i8> poison, <2 x i32> <i32 0, i32 2>
534 ; THR15-NEXT: [[TMP126:%.*]] = zext <2 x i8> [[TMP125]] to <2 x i32>
535 ; THR15-NEXT: [[TMP152:%.*]] = load <4 x i8>, ptr [[ARRAYIDX3_1]], align 1
536 ; THR15-NEXT: [[TMP127:%.*]] = shufflevector <4 x i8> [[TMP152]], <4 x i8> poison, <2 x i32> <i32 0, i32 2>
537 ; THR15-NEXT: [[TMP128:%.*]] = zext <2 x i8> [[TMP127]] to <2 x i32>
538 ; THR15-NEXT: [[TMP153:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5_1]], align 1
539 ; THR15-NEXT: [[TMP129:%.*]] = shufflevector <4 x i8> [[TMP153]], <4 x i8> poison, <2 x i32> <i32 0, i32 2>
540 ; THR15-NEXT: [[TMP130:%.*]] = zext <2 x i8> [[TMP129]] to <2 x i32>
541 ; THR15-NEXT: [[TMP131:%.*]] = sub <2 x i32> [[TMP128]], [[TMP130]]
542 ; THR15-NEXT: [[TMP132:%.*]] = shl <2 x i32> [[TMP131]], splat (i32 16)
543 ; THR15-NEXT: [[TMP138:%.*]] = shufflevector <4 x i8> [[TMP148]], <4 x i8> poison, <2 x i32> <i32 1, i32 3>
544 ; THR15-NEXT: [[TMP139:%.*]] = zext <2 x i8> [[TMP138]] to <2 x i32>
545 ; THR15-NEXT: [[TMP154:%.*]] = shufflevector <4 x i8> [[TMP152]], <4 x i8> poison, <2 x i32> <i32 1, i32 3>
546 ; THR15-NEXT: [[TMP155:%.*]] = zext <2 x i8> [[TMP154]] to <2 x i32>
547 ; THR15-NEXT: [[TMP133:%.*]] = shufflevector <4 x i8> [[TMP153]], <4 x i8> poison, <2 x i32> <i32 1, i32 3>
548 ; THR15-NEXT: [[TMP134:%.*]] = zext <2 x i8> [[TMP133]] to <2 x i32>
549 ; THR15-NEXT: [[TMP135:%.*]] = sub <2 x i32> [[TMP155]], [[TMP134]]
550 ; THR15-NEXT: [[TMP170:%.*]] = shl <2 x i32> [[TMP135]], splat (i32 16)
551 ; THR15-NEXT: [[TMP140:%.*]] = insertelement <2 x i32> [[TMP124]], i32 [[CONV33_1]], i32 1
552 ; THR15-NEXT: [[TMP141:%.*]] = sub <2 x i32> [[TMP140]], [[TMP139]]
553 ; THR15-NEXT: [[TMP171:%.*]] = add <2 x i32> [[TMP170]], [[TMP141]]
554 ; THR15-NEXT: [[TMP186:%.*]] = insertelement <2 x i32> [[TMP124]], i32 [[CONV_1]], i32 0
555 ; THR15-NEXT: [[TMP187:%.*]] = sub <2 x i32> [[TMP186]], [[TMP126]]
556 ; THR15-NEXT: [[TMP142:%.*]] = add <2 x i32> [[TMP132]], [[TMP187]]
557 ; THR15-NEXT: [[TMP136:%.*]] = add <2 x i32> [[TMP171]], [[TMP142]]
558 ; THR15-NEXT: [[TMP149:%.*]] = sub <2 x i32> [[TMP142]], [[TMP171]]
559 ; THR15-NEXT: [[TMP144:%.*]] = extractelement <2 x i32> [[TMP136]], i32 0
560 ; THR15-NEXT: [[TMP145:%.*]] = extractelement <2 x i32> [[TMP136]], i32 1
561 ; THR15-NEXT: [[ADD48_2:%.*]] = add i32 [[TMP145]], [[TMP144]]
562 ; THR15-NEXT: [[SUB45_1:%.*]] = sub i32 [[TMP144]], [[TMP145]]
563 ; THR15-NEXT: [[TMP150:%.*]] = extractelement <2 x i32> [[TMP149]], i32 0
564 ; THR15-NEXT: [[TMP151:%.*]] = extractelement <2 x i32> [[TMP149]], i32 1
565 ; THR15-NEXT: [[ADD48_1:%.*]] = add i32 [[TMP151]], [[TMP150]]
566 ; THR15-NEXT: [[SUB51_1:%.*]] = sub i32 [[TMP150]], [[TMP151]]
567 ; THR15-NEXT: [[SHR_I54:%.*]] = lshr i32 [[TMP145]], 15
568 ; THR15-NEXT: [[AND_I55:%.*]] = and i32 [[SHR_I54]], 65537
569 ; THR15-NEXT: [[MUL_I56:%.*]] = mul i32 [[AND_I55]], 65535
570 ; THR15-NEXT: [[SHR_I54_1:%.*]] = lshr i32 [[TMP151]], 15
571 ; THR15-NEXT: [[AND_I55_1:%.*]] = and i32 [[SHR_I54_1]], 65537
572 ; THR15-NEXT: [[MUL_I56_1:%.*]] = mul i32 [[AND_I55_1]], 65535
573 ; THR15-NEXT: [[TMP156:%.*]] = lshr <2 x i32> [[TMP124]], splat (i32 15)
574 ; THR15-NEXT: [[TMP157:%.*]] = and <2 x i32> [[TMP156]], splat (i32 65537)
575 ; THR15-NEXT: [[TMP158:%.*]] = mul <2 x i32> [[TMP157]], splat (i32 65535)
576 ; THR15-NEXT: [[ADD78:%.*]] = add i32 [[ADD48_2]], [[ADD48]]
577 ; THR15-NEXT: [[SUB86:%.*]] = sub i32 [[ADD48]], [[ADD48_2]]
578 ; THR15-NEXT: [[ADD103:%.*]] = add i32 [[ADD94]], [[ADD78]]
579 ; THR15-NEXT: [[SUB104:%.*]] = sub i32 [[ADD78]], [[ADD94]]
580 ; THR15-NEXT: [[ADD105:%.*]] = add i32 [[SUB102]], [[SUB86]]
581 ; THR15-NEXT: [[SUB106:%.*]] = sub i32 [[SUB86]], [[SUB102]]
582 ; THR15-NEXT: [[ADD_I:%.*]] = add i32 [[MUL_I]], [[ADD103]]
583 ; THR15-NEXT: [[XOR_I:%.*]] = xor i32 [[ADD_I]], [[CONV_3]]
584 ; THR15-NEXT: [[ADD_I52:%.*]] = add i32 [[MUL_I51]], [[ADD105]]
585 ; THR15-NEXT: [[XOR_I53:%.*]] = xor i32 [[ADD_I52]], [[TMP44]]
586 ; THR15-NEXT: [[ADD_I57:%.*]] = add i32 [[MUL_I56]], [[SUB104]]
587 ; THR15-NEXT: [[XOR_I58:%.*]] = xor i32 [[ADD_I57]], [[TMP145]]
588 ; THR15-NEXT: [[ADD_I62:%.*]] = add i32 [[MUL_I61]], [[SUB106]]
589 ; THR15-NEXT: [[XOR_I63:%.*]] = xor i32 [[ADD_I62]], [[TMP120]]
590 ; THR15-NEXT: [[ADD110:%.*]] = add i32 [[XOR_I53]], [[XOR_I]]
591 ; THR15-NEXT: [[ADD112:%.*]] = add i32 [[ADD110]], [[XOR_I58]]
592 ; THR15-NEXT: [[ADD113:%.*]] = add i32 [[ADD112]], [[XOR_I63]]
593 ; THR15-NEXT: [[ADD78_1:%.*]] = add i32 [[ADD48_1]], [[ADD55]]
594 ; THR15-NEXT: [[SUB86_1:%.*]] = sub i32 [[ADD55]], [[ADD48_1]]
595 ; THR15-NEXT: [[ADD103_1:%.*]] = add i32 [[ADD94_1]], [[ADD78_1]]
596 ; THR15-NEXT: [[SUB104_1:%.*]] = sub i32 [[ADD78_1]], [[ADD94_1]]
597 ; THR15-NEXT: [[ADD105_1:%.*]] = add i32 [[SUB102_1]], [[SUB86_1]]
598 ; THR15-NEXT: [[SUB106_1:%.*]] = sub i32 [[SUB86_1]], [[SUB102_1]]
599 ; THR15-NEXT: [[ADD_I_1:%.*]] = add i32 [[MUL_I_1]], [[ADD103_1]]
600 ; THR15-NEXT: [[XOR_I_1:%.*]] = xor i32 [[ADD_I_1]], [[TMP86]]
601 ; THR15-NEXT: [[ADD_I52_1:%.*]] = add i32 [[MUL_I51_1]], [[ADD105_1]]
602 ; THR15-NEXT: [[XOR_I53_1:%.*]] = xor i32 [[ADD_I52_1]], [[TMP87]]
603 ; THR15-NEXT: [[ADD_I57_1:%.*]] = add i32 [[MUL_I56_1]], [[SUB104_1]]
604 ; THR15-NEXT: [[XOR_I58_1:%.*]] = xor i32 [[ADD_I57_1]], [[TMP151]]
605 ; THR15-NEXT: [[ADD_I62_1:%.*]] = add i32 [[MUL_I61_1]], [[SUB106_1]]
606 ; THR15-NEXT: [[XOR_I63_1:%.*]] = xor i32 [[ADD_I62_1]], [[TMP122]]
607 ; THR15-NEXT: [[ADD108_1:%.*]] = add i32 [[XOR_I53_1]], [[ADD113]]
608 ; THR15-NEXT: [[ADD110_1:%.*]] = add i32 [[ADD108_1]], [[XOR_I_1]]
609 ; THR15-NEXT: [[ADD112_1:%.*]] = add i32 [[ADD110_1]], [[XOR_I58_1]]
610 ; THR15-NEXT: [[ADD113_1:%.*]] = add i32 [[ADD112_1]], [[XOR_I63_1]]
611 ; THR15-NEXT: [[ADD78_2:%.*]] = add i32 [[SUB45_1]], [[SUB51]]
612 ; THR15-NEXT: [[SUB86_2:%.*]] = sub i32 [[SUB51]], [[SUB45_1]]
613 ; THR15-NEXT: [[TMP159:%.*]] = insertelement <2 x i32> poison, i32 [[ADD78_2]], i32 0
614 ; THR15-NEXT: [[TMP160:%.*]] = shufflevector <2 x i32> [[TMP159]], <2 x i32> poison, <2 x i32> zeroinitializer
615 ; THR15-NEXT: [[TMP161:%.*]] = insertelement <2 x i32> poison, i32 [[ADD94_2]], i32 0
616 ; THR15-NEXT: [[TMP162:%.*]] = shufflevector <2 x i32> [[TMP161]], <2 x i32> poison, <2 x i32> zeroinitializer
617 ; THR15-NEXT: [[TMP163:%.*]] = add <2 x i32> [[TMP160]], [[TMP162]]
618 ; THR15-NEXT: [[TMP164:%.*]] = sub <2 x i32> [[TMP160]], [[TMP162]]
619 ; THR15-NEXT: [[TMP165:%.*]] = shufflevector <2 x i32> [[TMP163]], <2 x i32> [[TMP164]], <2 x i32> <i32 0, i32 3>
620 ; THR15-NEXT: [[ADD105_2:%.*]] = add i32 [[SUB102_2]], [[SUB86_2]]
621 ; THR15-NEXT: [[SUB106_2:%.*]] = sub i32 [[SUB86_2]], [[SUB102_2]]
622 ; THR15-NEXT: [[ADD_I52_2:%.*]] = add i32 [[MUL_I51_2]], [[ADD105_2]]
623 ; THR15-NEXT: [[XOR_I53_2:%.*]] = xor i32 [[ADD_I52_2]], [[CONV_1]]
624 ; THR15-NEXT: [[TMP166:%.*]] = add <2 x i32> [[TMP158]], [[TMP165]]
625 ; THR15-NEXT: [[TMP167:%.*]] = xor <2 x i32> [[TMP166]], [[TMP124]]
626 ; THR15-NEXT: [[SHR_I59_2:%.*]] = lshr i32 [[TMP119]], 15
627 ; THR15-NEXT: [[AND_I60_2:%.*]] = and i32 [[SHR_I59_2]], 65537
628 ; THR15-NEXT: [[MUL_I61_2:%.*]] = mul i32 [[AND_I60_2]], 65535
629 ; THR15-NEXT: [[ADD_I62_2:%.*]] = add i32 [[MUL_I61_2]], [[SUB106_2]]
630 ; THR15-NEXT: [[XOR_I63_2:%.*]] = xor i32 [[ADD_I62_2]], [[TMP119]]
631 ; THR15-NEXT: [[ADD108_2:%.*]] = add i32 [[XOR_I53_2]], [[ADD113_1]]
632 ; THR15-NEXT: [[TMP168:%.*]] = extractelement <2 x i32> [[TMP167]], i32 0
633 ; THR15-NEXT: [[ADD110_2:%.*]] = add i32 [[ADD108_2]], [[TMP168]]
634 ; THR15-NEXT: [[TMP169:%.*]] = extractelement <2 x i32> [[TMP167]], i32 1
635 ; THR15-NEXT: [[ADD112_2:%.*]] = add i32 [[ADD110_2]], [[TMP169]]
636 ; THR15-NEXT: [[ADD113_2:%.*]] = add i32 [[ADD112_2]], [[XOR_I63_2]]
637 ; THR15-NEXT: [[ADD78_3:%.*]] = add i32 [[SUB51_1]], [[SUB59]]
638 ; THR15-NEXT: [[SUB86_3:%.*]] = sub i32 [[SUB59]], [[SUB51_1]]
639 ; THR15-NEXT: [[TMP172:%.*]] = insertelement <2 x i32> poison, i32 [[ADD78_3]], i32 0
640 ; THR15-NEXT: [[TMP173:%.*]] = shufflevector <2 x i32> [[TMP172]], <2 x i32> poison, <2 x i32> zeroinitializer
641 ; THR15-NEXT: [[TMP174:%.*]] = insertelement <2 x i32> poison, i32 [[ADD94_3]], i32 0
642 ; THR15-NEXT: [[TMP175:%.*]] = shufflevector <2 x i32> [[TMP174]], <2 x i32> poison, <2 x i32> zeroinitializer
643 ; THR15-NEXT: [[TMP176:%.*]] = add <2 x i32> [[TMP173]], [[TMP175]]
644 ; THR15-NEXT: [[TMP177:%.*]] = sub <2 x i32> [[TMP173]], [[TMP175]]
645 ; THR15-NEXT: [[TMP178:%.*]] = shufflevector <2 x i32> [[TMP176]], <2 x i32> [[TMP177]], <2 x i32> <i32 0, i32 3>
646 ; THR15-NEXT: [[ADD105_3:%.*]] = add i32 [[SUB102_3]], [[SUB86_3]]
647 ; THR15-NEXT: [[SUB106_3:%.*]] = sub i32 [[SUB86_3]], [[SUB102_3]]
648 ; THR15-NEXT: [[ADD_I52_3:%.*]] = add i32 [[MUL_I51_3]], [[ADD105_3]]
649 ; THR15-NEXT: [[XOR_I53_3:%.*]] = xor i32 [[ADD_I52_3]], [[CONV]]
650 ; THR15-NEXT: [[TMP179:%.*]] = lshr <2 x i32> [[TMP93]], splat (i32 15)
651 ; THR15-NEXT: [[TMP180:%.*]] = and <2 x i32> [[TMP179]], splat (i32 65537)
652 ; THR15-NEXT: [[TMP181:%.*]] = mul <2 x i32> [[TMP180]], splat (i32 65535)
653 ; THR15-NEXT: [[TMP182:%.*]] = add <2 x i32> [[TMP181]], [[TMP178]]
654 ; THR15-NEXT: [[TMP183:%.*]] = xor <2 x i32> [[TMP182]], [[TMP93]]
655 ; THR15-NEXT: [[SHR_I59_3:%.*]] = lshr i32 [[CONV33]], 15
656 ; THR15-NEXT: [[AND_I60_3:%.*]] = and i32 [[SHR_I59_3]], 65537
657 ; THR15-NEXT: [[MUL_I61_3:%.*]] = mul i32 [[AND_I60_3]], 65535
658 ; THR15-NEXT: [[ADD_I62_3:%.*]] = add i32 [[MUL_I61_3]], [[SUB106_3]]
659 ; THR15-NEXT: [[XOR_I63_3:%.*]] = xor i32 [[ADD_I62_3]], [[CONV33]]
660 ; THR15-NEXT: [[ADD108_3:%.*]] = add i32 [[XOR_I53_3]], [[ADD113_2]]
661 ; THR15-NEXT: [[TMP184:%.*]] = extractelement <2 x i32> [[TMP183]], i32 0
662 ; THR15-NEXT: [[ADD110_3:%.*]] = add i32 [[ADD108_3]], [[TMP184]]
663 ; THR15-NEXT: [[TMP185:%.*]] = extractelement <2 x i32> [[TMP183]], i32 1
664 ; THR15-NEXT: [[ADD112_3:%.*]] = add i32 [[ADD110_3]], [[TMP185]]
665 ; THR15-NEXT: [[ADD113_3:%.*]] = add i32 [[ADD112_3]], [[XOR_I63_3]]
666 ; THR15-NEXT: ret i32 [[ADD113_3]]
667 ;
668 entry:
669 %0 = load i8, ptr %pix1, align 1
670 %conv = zext i8 %0 to i32
671 %1 = load i8, ptr %pix2, align 1
672 %conv2 = zext i8 %1 to i32
673 %sub = sub i32 %conv, %conv2
674 %arrayidx3 = getelementptr i8, ptr %pix1, i64 4
675 %2 = load i8, ptr %arrayidx3, align 1
676 %conv4 = zext i8 %2 to i32
677 %arrayidx5 = getelementptr i8, ptr %pix2, i64 4
678 %3 = load i8, ptr %arrayidx5, align 1
679 %conv6 = zext i8 %3 to i32
680 %sub7 = sub i32 %conv4, %conv6
681 %shl = shl i32 %sub7, 16
682 %add = add i32 %shl, %sub
683 %arrayidx8 = getelementptr i8, ptr %pix1, i64 1
684 %4 = load i8, ptr %arrayidx8, align 1
685 %conv9 = zext i8 %4 to i32
686 %arrayidx10 = getelementptr i8, ptr %pix2, i64 1
687 %5 = load i8, ptr %arrayidx10, align 1
688 %conv11 = zext i8 %5 to i32
689 %sub12 = sub i32 %conv9, %conv11
690 %arrayidx13 = getelementptr i8, ptr %pix1, i64 5
691 %6 = load i8, ptr %arrayidx13, align 1
692 %conv14 = zext i8 %6 to i32
693 %arrayidx15 = getelementptr i8, ptr %pix2, i64 5
694 %7 = load i8, ptr %arrayidx15, align 1
695 %conv16 = zext i8 %7 to i32
696 %sub17 = sub i32 %conv14, %conv16
697 %shl18 = shl i32 %sub17, 16
698 %add19 = add i32 %shl18, %sub12
699 %arrayidx20 = getelementptr i8, ptr %pix1, i64 2
700 %8 = load i8, ptr %arrayidx20, align 1
701 %conv21 = zext i8 %8 to i32
702 %arrayidx22 = getelementptr i8, ptr %pix2, i64 2
703 %9 = load i8, ptr %arrayidx22, align 1
704 %conv23 = zext i8 %9 to i32
705 %sub24 = sub i32 %conv21, %conv23
706 %arrayidx25 = getelementptr i8, ptr %pix1, i64 6
707 %10 = load i8, ptr %arrayidx25, align 1
708 %conv26 = zext i8 %10 to i32
709 %arrayidx27 = getelementptr i8, ptr %pix2, i64 6
710 %11 = load i8, ptr %arrayidx27, align 1
711 %conv28 = zext i8 %11 to i32
712 %sub29 = sub i32 %conv26, %conv28
713 %shl30 = shl i32 %sub29, 16
714 %add31 = add i32 %shl30, %sub24
715 %arrayidx32 = getelementptr i8, ptr %pix1, i64 3
716 %12 = load i8, ptr %arrayidx32, align 1
717 %conv33 = zext i8 %12 to i32
718 %arrayidx34 = getelementptr i8, ptr %pix2, i64 3
719 %13 = load i8, ptr %arrayidx34, align 1
720 %conv35 = zext i8 %13 to i32
721 %sub36 = sub i32 %conv33, %conv35
722 %arrayidx37 = getelementptr i8, ptr %pix1, i64 7
723 %14 = load i8, ptr %arrayidx37, align 1
724 %conv38 = zext i8 %14 to i32
725 %arrayidx39 = getelementptr i8, ptr %pix2, i64 7
726 %15 = load i8, ptr %arrayidx39, align 1
727 %conv40 = zext i8 %15 to i32
728 %sub41 = sub i32 %conv38, %conv40
729 %shl42 = shl i32 %sub41, 16
730 %add43 = add i32 %shl42, %sub36
731 %add44 = add i32 %add19, %add
732 %sub45 = sub i32 %add, %add19
733 %add46 = add i32 %add43, %add31
734 %sub47 = sub i32 %add31, %add43
735 %add48 = add i32 %add46, %add44
736 %sub51 = sub i32 %add44, %add46
737 %add55 = add i32 %sub47, %sub45
738 %sub59 = sub i32 %sub45, %sub47
739 %add.ptr3 = getelementptr i8, ptr %pix1, i64 %idx.ext
740 %add.ptr644 = getelementptr i8, ptr %pix2, i64 %idx.ext63
741 %16 = load i8, ptr %add.ptr3, align 1
742 %conv.1 = zext i8 %16 to i32
743 %17 = load i8, ptr %add.ptr644, align 1
744 %conv2.1 = zext i8 %17 to i32
745 %sub.1 = sub i32 %conv.1, %conv2.1
746 %arrayidx3.1 = getelementptr i8, ptr %add.ptr3, i64 4
747 %18 = load i8, ptr %arrayidx3.1, align 1
748 %conv4.1 = zext i8 %18 to i32
749 %arrayidx5.1 = getelementptr i8, ptr %add.ptr644, i64 4
750 %19 = load i8, ptr %arrayidx5.1, align 1
751 %conv6.1 = zext i8 %19 to i32
752 %sub7.1 = sub i32 %conv4.1, %conv6.1
753 %shl.1 = shl i32 %sub7.1, 16
754 %add.1 = add i32 %shl.1, %sub.1
755 %arrayidx8.1 = getelementptr i8, ptr %add.ptr3, i64 1
756 %20 = load i8, ptr %arrayidx8.1, align 1
757 %conv9.1 = zext i8 %20 to i32
758 %arrayidx10.1 = getelementptr i8, ptr %add.ptr644, i64 1
759 %21 = load i8, ptr %arrayidx10.1, align 1
760 %conv11.1 = zext i8 %21 to i32
761 %sub12.1 = sub i32 %conv9.1, %conv11.1
762 %arrayidx13.1 = getelementptr i8, ptr %add.ptr3, i64 5
763 %22 = load i8, ptr %arrayidx13.1, align 1
764 %conv14.1 = zext i8 %22 to i32
765 %arrayidx15.1 = getelementptr i8, ptr %add.ptr644, i64 5
766 %23 = load i8, ptr %arrayidx15.1, align 1
767 %conv16.1 = zext i8 %23 to i32
768 %sub17.1 = sub i32 %conv14.1, %conv16.1
769 %shl18.1 = shl i32 %sub17.1, 16
770 %add19.1 = add i32 %shl18.1, %sub12.1
771 %arrayidx20.1 = getelementptr i8, ptr %add.ptr3, i64 2
772 %24 = load i8, ptr %arrayidx20.1, align 1
773 %conv21.1 = zext i8 %24 to i32
774 %arrayidx22.1 = getelementptr i8, ptr %add.ptr644, i64 2
775 %25 = load i8, ptr %arrayidx22.1, align 1
776 %conv23.1 = zext i8 %25 to i32
777 %sub24.1 = sub i32 %conv21.1, %conv23.1
778 %arrayidx25.1 = getelementptr i8, ptr %add.ptr3, i64 6
779 %26 = load i8, ptr %arrayidx25.1, align 1
780 %conv26.1 = zext i8 %26 to i32
781 %arrayidx27.1 = getelementptr i8, ptr %add.ptr644, i64 6
782 %27 = load i8, ptr %arrayidx27.1, align 1
783 %conv28.1 = zext i8 %27 to i32
784 %sub29.1 = sub i32 %conv26.1, %conv28.1
785 %shl30.1 = shl i32 %sub29.1, 16
786 %add31.1 = add i32 %shl30.1, %sub24.1
787 %arrayidx32.1 = getelementptr i8, ptr %add.ptr3, i64 3
788 %28 = load i8, ptr %arrayidx32.1, align 1
789 %conv33.1 = zext i8 %28 to i32
790 %arrayidx34.1 = getelementptr i8, ptr %add.ptr644, i64 3
791 %29 = load i8, ptr %arrayidx34.1, align 1
792 %conv35.1 = zext i8 %29 to i32
793 %sub36.1 = sub i32 %conv33.1, %conv35.1
794 %arrayidx37.1 = getelementptr i8, ptr %add.ptr3, i64 7
795 %30 = load i8, ptr %arrayidx37.1, align 1
796 %conv38.1 = zext i8 %30 to i32
797 %arrayidx39.1 = getelementptr i8, ptr %add.ptr644, i64 7
798 %31 = load i8, ptr %arrayidx39.1, align 1
799 %conv40.1 = zext i8 %31 to i32
800 %sub41.1 = sub i32 %conv38.1, %conv40.1
801 %shl42.1 = shl i32 %sub41.1, 16
802 %add43.1 = add i32 %shl42.1, %sub36.1
803 %add44.1 = add i32 %add19.1, %add.1
804 %sub45.1 = sub i32 %add.1, %add19.1
805 %add46.1 = add i32 %add43.1, %add31.1
806 %sub47.1 = sub i32 %add31.1, %add43.1
807 %add48.1 = add i32 %add46.1, %add44.1
808 %sub51.1 = sub i32 %add44.1, %add46.1
809 %add55.1 = add i32 %sub47.1, %sub45.1
810 %sub59.1 = sub i32 %sub45.1, %sub47.1
811 %add.ptr.1 = getelementptr i8, ptr %add.ptr, i64 %idx.ext
812 %add.ptr64.1 = getelementptr i8, ptr %add.ptr64, i64 %idx.ext63
813 %32 = load i8, ptr %add.ptr.1, align 1
814 %conv.2 = zext i8 %32 to i32
815 %33 = load i8, ptr %add.ptr64.1, align 1
816 %conv2.2 = zext i8 %33 to i32
817 %sub.2 = sub i32 %conv.2, %conv2.2
818 %arrayidx3.2 = getelementptr i8, ptr %add.ptr.1, i64 4
819 %34 = load i8, ptr %arrayidx3.2, align 1
820 %conv4.2 = zext i8 %34 to i32
821 %arrayidx5.2 = getelementptr i8, ptr %add.ptr64.1, i64 4
822 %35 = load i8, ptr %arrayidx5.2, align 1
823 %conv6.2 = zext i8 %35 to i32
824 %sub7.2 = sub i32 %conv4.2, %conv6.2
825 %shl.2 = shl i32 %sub7.2, 16
826 %add.2 = add i32 %shl.2, %sub.2
827 %arrayidx8.2 = getelementptr i8, ptr %add.ptr.1, i64 1
828 %36 = load i8, ptr %arrayidx8.2, align 1
829 %conv9.2 = zext i8 %36 to i32
830 %arrayidx10.2 = getelementptr i8, ptr %add.ptr64.1, i64 1
831 %37 = load i8, ptr %arrayidx10.2, align 1
832 %conv11.2 = zext i8 %37 to i32
833 %sub12.2 = sub i32 %conv9.2, %conv11.2
834 %arrayidx13.2 = getelementptr i8, ptr %add.ptr.1, i64 5
835 %38 = load i8, ptr %arrayidx13.2, align 1
836 %conv14.2 = zext i8 %38 to i32
837 %arrayidx15.2 = getelementptr i8, ptr %add.ptr64.1, i64 5
838 %39 = load i8, ptr %arrayidx15.2, align 1
839 %conv16.2 = zext i8 %39 to i32
840 %sub17.2 = sub i32 %conv14.2, %conv16.2
841 %shl18.2 = shl i32 %sub17.2, 16
842 %add19.2 = add i32 %shl18.2, %sub12.2
843 %arrayidx20.2 = getelementptr i8, ptr %add.ptr.1, i64 2
844 %40 = load i8, ptr %arrayidx20.2, align 1
845 %conv21.2 = zext i8 %40 to i32
846 %arrayidx22.2 = getelementptr i8, ptr %add.ptr64.1, i64 2
847 %41 = load i8, ptr %arrayidx22.2, align 1
848 %conv23.2 = zext i8 %41 to i32
849 %sub24.2 = sub i32 %conv21.2, %conv23.2
850 %arrayidx25.2 = getelementptr i8, ptr %add.ptr.1, i64 6
851 %42 = load i8, ptr %arrayidx25.2, align 1
852 %conv26.2 = zext i8 %42 to i32
853 %arrayidx27.2 = getelementptr i8, ptr %add.ptr64.1, i64 6
854 %43 = load i8, ptr %arrayidx27.2, align 1
855 %conv28.2 = zext i8 %43 to i32
856 %sub29.2 = sub i32 %conv26.2, %conv28.2
857 %shl30.2 = shl i32 %sub29.2, 16
858 %add31.2 = add i32 %shl30.2, %sub24.2
859 %arrayidx32.2 = getelementptr i8, ptr %add.ptr.1, i64 3
860 %44 = load i8, ptr %arrayidx32.2, align 1
861 %conv33.2 = zext i8 %44 to i32
862 %arrayidx34.2 = getelementptr i8, ptr %add.ptr64.1, i64 3
863 %45 = load i8, ptr %arrayidx34.2, align 1
864 %conv35.2 = zext i8 %45 to i32
865 %sub36.2 = sub i32 %conv33.2, %conv35.2
866 %arrayidx37.2 = getelementptr i8, ptr %add.ptr.1, i64 7
867 %46 = load i8, ptr %arrayidx37.2, align 1
868 %conv38.2 = zext i8 %46 to i32
869 %arrayidx39.2 = getelementptr i8, ptr %add.ptr64.1, i64 7
870 %47 = load i8, ptr %arrayidx39.2, align 1
871 %conv40.2 = zext i8 %47 to i32
872 %sub41.2 = sub i32 %conv38.2, %conv40.2
873 %shl42.2 = shl i32 %sub41.2, 16
874 %add43.2 = add i32 %shl42.2, %sub36.2
875 %add44.2 = add i32 %add19.2, %add.2
876 %sub45.2 = sub i32 %add.2, %add19.2
877 %add46.2 = add i32 %add43.2, %add31.2
878 %sub47.2 = sub i32 %add31.2, %add43.2
879 %add48.2 = add i32 %add46.2, %add44.2
880 %sub51.2 = sub i32 %add44.2, %add46.2
881 %add55.2 = add i32 %sub47.2, %sub45.2
882 %sub59.2 = sub i32 %sub45.2, %sub47.2
883 %48 = load i8, ptr null, align 1
884 %conv.3 = zext i8 %48 to i32
885 %49 = load i8, ptr null, align 1
886 %conv2.3 = zext i8 %49 to i32
887 %sub.3 = sub i32 %conv.3, %conv2.3
888 %arrayidx3.3 = getelementptr i8, ptr null, i64 4
889 %50 = load i8, ptr %arrayidx3.3, align 1
890 %conv4.3 = zext i8 %50 to i32
891 %arrayidx5.3 = getelementptr i8, ptr null, i64 4
892 %51 = load i8, ptr %arrayidx5.3, align 1
893 %conv6.3 = zext i8 %51 to i32
894 %sub7.3 = sub i32 %conv4.3, %conv6.3
895 %shl.3 = shl i32 %sub7.3, 16
896 %add.3 = add i32 %shl.3, %sub.3
897 %arrayidx8.3 = getelementptr i8, ptr null, i64 1
898 %52 = load i8, ptr %arrayidx8.3, align 1
899 %conv9.3 = zext i8 %52 to i32
900 %arrayidx10.3 = getelementptr i8, ptr null, i64 1
901 %53 = load i8, ptr %arrayidx10.3, align 1
902 %conv11.3 = zext i8 %53 to i32
903 %sub12.3 = sub i32 %conv9.3, %conv11.3
904 %54 = load i8, ptr null, align 1
905 %conv14.3 = zext i8 %54 to i32
906 %arrayidx15.3 = getelementptr i8, ptr null, i64 5
907 %55 = load i8, ptr %arrayidx15.3, align 1
908 %conv16.3 = zext i8 %55 to i32
909 %sub17.3 = sub i32 %conv14.3, %conv16.3
910 %shl18.3 = shl i32 %sub17.3, 16
911 %add19.3 = add i32 %shl18.3, %sub12.3
912 %arrayidx20.3 = getelementptr i8, ptr null, i64 2
913 %56 = load i8, ptr %arrayidx20.3, align 1
914 %conv21.3 = zext i8 %56 to i32
915 %arrayidx22.3 = getelementptr i8, ptr null, i64 2
916 %57 = load i8, ptr %arrayidx22.3, align 1
917 %conv23.3 = zext i8 %57 to i32
918 %sub24.3 = sub i32 %conv21.3, %conv23.3
919 %58 = load i8, ptr null, align 1
920 %conv26.3 = zext i8 %58 to i32
921 %arrayidx27.3 = getelementptr i8, ptr null, i64 6
922 %59 = load i8, ptr %arrayidx27.3, align 1
923 %conv28.3 = zext i8 %59 to i32
924 %sub29.3 = sub i32 %conv26.3, %conv28.3
925 %shl30.3 = shl i32 %sub29.3, 16
926 %add31.3 = add i32 %shl30.3, %sub24.3
927 %arrayidx32.3 = getelementptr i8, ptr null, i64 3
928 %60 = load i8, ptr %arrayidx32.3, align 1
929 %conv33.3 = zext i8 %60 to i32
930 %arrayidx34.3 = getelementptr i8, ptr null, i64 3
931 %61 = load i8, ptr %arrayidx34.3, align 1
932 %conv35.3 = zext i8 %61 to i32
933 %sub36.3 = sub i32 %conv33.3, %conv35.3
934 %62 = load i8, ptr null, align 1
935 %conv38.3 = zext i8 %62 to i32
936 %arrayidx39.3 = getelementptr i8, ptr null, i64 7
937 %63 = load i8, ptr %arrayidx39.3, align 1
938 %conv40.3 = zext i8 %63 to i32
939 %sub41.3 = sub i32 %conv38.3, %conv40.3
940 %shl42.3 = shl i32 %sub41.3, 16
941 %add43.3 = add i32 %shl42.3, %sub36.3
942 %add44.3 = add i32 %add19.3, %add.3
943 %sub45.3 = sub i32 %add.3, %add19.3
944 %add46.3 = add i32 %add43.3, %add31.3
945 %sub47.3 = sub i32 %add31.3, %add43.3
946 %add48.3 = add i32 %add46.3, %add44.3
947 %sub51.3 = sub i32 %add44.3, %add46.3
948 %add55.3 = add i32 %sub47.3, %sub45.3
949 %sub59.3 = sub i32 %sub45.3, %sub47.3
950 %add78 = add i32 %add48.1, %add48
951 %sub86 = sub i32 %add48, %add48.1
952 %add94 = add i32 %add48.3, %add48.2
953 %sub102 = sub i32 %add48.2, %add48.3
954 %add103 = add i32 %add94, %add78
955 %sub104 = sub i32 %add78, %add94
956 %add105 = add i32 %sub102, %sub86
957 %sub106 = sub i32 %sub86, %sub102
958 %shr.i = lshr i32 %conv.3, 15
959 %and.i = and i32 %shr.i, 65537
960 %mul.i = mul i32 %and.i, 65535
961 %add.i = add i32 %mul.i, %add103
962 %xor.i = xor i32 %add.i, %conv.3
963 %shr.i49 = lshr i32 %add46.2, 15
964 %and.i50 = and i32 %shr.i49, 65537
965 %mul.i51 = mul i32 %and.i50, 65535
966 %add.i52 = add i32 %mul.i51, %add105
967 %xor.i53 = xor i32 %add.i52, %add46.2
968 %shr.i54 = lshr i32 %add46.1, 15
969 %and.i55 = and i32 %shr.i54, 65537
970 %mul.i56 = mul i32 %and.i55, 65535
971 %add.i57 = add i32 %mul.i56, %sub104
972 %xor.i58 = xor i32 %add.i57, %add46.1
973 %shr.i59 = lshr i32 %add46, 15
974 %and.i60 = and i32 %shr.i59, 65537
975 %mul.i61 = mul i32 %and.i60, 65535
976 %add.i62 = add i32 %mul.i61, %sub106
977 %xor.i63 = xor i32 %add.i62, %add46
978 %add110 = add i32 %xor.i53, %xor.i
979 %add112 = add i32 %add110, %xor.i58
980 %add113 = add i32 %add112, %xor.i63
981 %add78.1 = add i32 %add55.1, %add55
982 %sub86.1 = sub i32 %add55, %add55.1
983 %add94.1 = add i32 %add55.3, %add55.2
984 %sub102.1 = sub i32 %add55.2, %add55.3
985 %add103.1 = add i32 %add94.1, %add78.1
986 %sub104.1 = sub i32 %add78.1, %add94.1
987 %add105.1 = add i32 %sub102.1, %sub86.1
988 %sub106.1 = sub i32 %sub86.1, %sub102.1
989 %shr.i.1 = lshr i32 %conv9.2, 15
990 %and.i.1 = and i32 %shr.i.1, 65537
991 %mul.i.1 = mul i32 %and.i.1, 65535
992 %add.i.1 = add i32 %mul.i.1, %add103.1
993 %xor.i.1 = xor i32 %add.i.1, %conv9.2
994 %shr.i49.1 = lshr i32 %conv.2, 15
995 %and.i50.1 = and i32 %shr.i49.1, 65537
996 %mul.i51.1 = mul i32 %and.i50.1, 65535
997 %add.i52.1 = add i32 %mul.i51.1, %add105.1
998 %xor.i53.1 = xor i32 %add.i52.1, %conv.2
999 %shr.i54.1 = lshr i32 %sub47.1, 15
1000 %and.i55.1 = and i32 %shr.i54.1, 65537
1001 %mul.i56.1 = mul i32 %and.i55.1, 65535
1002 %add.i57.1 = add i32 %mul.i56.1, %sub104.1
1003 %xor.i58.1 = xor i32 %add.i57.1, %sub47.1
1004 %shr.i59.1 = lshr i32 %sub47, 15
1005 %and.i60.1 = and i32 %shr.i59.1, 65537
1006 %mul.i61.1 = mul i32 %and.i60.1, 65535
1007 %add.i62.1 = add i32 %mul.i61.1, %sub106.1
1008 %xor.i63.1 = xor i32 %add.i62.1, %sub47
1009 %add108.1 = add i32 %xor.i53.1, %add113
1010 %add110.1 = add i32 %add108.1, %xor.i.1
1011 %add112.1 = add i32 %add110.1, %xor.i58.1
1012 %add113.1 = add i32 %add112.1, %xor.i63.1
1013 %add78.2 = add i32 %sub51.1, %sub51
1014 %sub86.2 = sub i32 %sub51, %sub51.1
1015 %add94.2 = add i32 %sub51.3, %sub51.2
1016 %sub102.2 = sub i32 %sub51.2, %sub51.3
1017 %add103.2 = add i32 %add94.2, %add78.2
1018 %sub104.2 = sub i32 %add78.2, %add94.2
1019 %add105.2 = add i32 %sub102.2, %sub86.2
1020 %sub106.2 = sub i32 %sub86.2, %sub102.2
1021 %shr.i.2 = lshr i32 %conv9.1, 15
1022 %and.i.2 = and i32 %shr.i.2, 65537
1023 %mul.i.2 = mul i32 %and.i.2, 65535
1024 %add.i.2 = add i32 %mul.i.2, %add103.2
1025 %xor.i.2 = xor i32 %add.i.2, %conv9.1
1026 %shr.i49.2 = lshr i32 %conv.1, 15
1027 %and.i50.2 = and i32 %shr.i49.2, 65537
1028 %mul.i51.2 = mul i32 %and.i50.2, 65535
1029 %add.i52.2 = add i32 %mul.i51.2, %add105.2
1030 %xor.i53.2 = xor i32 %add.i52.2, %conv.1
1031 %shr.i54.2 = lshr i32 %conv21.1, 15
1032 %and.i55.2 = and i32 %shr.i54.2, 65537
1033 %mul.i56.2 = mul i32 %and.i55.2, 65535
1034 %add.i57.2 = add i32 %mul.i56.2, %sub104.2
1035 %xor.i58.2 = xor i32 %add.i57.2, %conv21.1
1036 %shr.i59.2 = lshr i32 %add44, 15
1037 %and.i60.2 = and i32 %shr.i59.2, 65537
1038 %mul.i61.2 = mul i32 %and.i60.2, 65535
1039 %add.i62.2 = add i32 %mul.i61.2, %sub106.2
1040 %xor.i63.2 = xor i32 %add.i62.2, %add44
1041 %add108.2 = add i32 %xor.i53.2, %add113.1
1042 %add110.2 = add i32 %add108.2, %xor.i.2
1043 %add112.2 = add i32 %add110.2, %xor.i58.2
1044 %add113.2 = add i32 %add112.2, %xor.i63.2
1045 %add78.3 = add i32 %sub59.1, %sub59
1046 %sub86.3 = sub i32 %sub59, %sub59.1
1047 %add94.3 = add i32 %sub59.3, %sub59.2
1048 %sub102.3 = sub i32 %sub59.2, %sub59.3
1049 %add103.3 = add i32 %add94.3, %add78.3
1050 %sub104.3 = sub i32 %add78.3, %add94.3
1051 %add105.3 = add i32 %sub102.3, %sub86.3
1052 %sub106.3 = sub i32 %sub86.3, %sub102.3
1053 %shr.i.3 = lshr i32 %conv9, 15
1054 %and.i.3 = and i32 %shr.i.3, 65537
1055 %mul.i.3 = mul i32 %and.i.3, 65535
1056 %add.i.3 = add i32 %mul.i.3, %add103.3
1057 %xor.i.3 = xor i32 %add.i.3, %conv9
1058 %shr.i49.3 = lshr i32 %conv, 15
1059 %and.i50.3 = and i32 %shr.i49.3, 65537
1060 %mul.i51.3 = mul i32 %and.i50.3, 65535
1061 %add.i52.3 = add i32 %mul.i51.3, %add105.3
1062 %xor.i53.3 = xor i32 %add.i52.3, %conv
1063 %shr.i54.3 = lshr i32 %conv21, 15
1064 %and.i55.3 = and i32 %shr.i54.3, 65537
1065 %mul.i56.3 = mul i32 %and.i55.3, 65535
1066 %add.i57.3 = add i32 %mul.i56.3, %sub104.3
1067 %xor.i58.3 = xor i32 %add.i57.3, %conv21
1068 %shr.i59.3 = lshr i32 %conv33, 15
1069 %and.i60.3 = and i32 %shr.i59.3, 65537
1070 %mul.i61.3 = mul i32 %and.i60.3, 65535
1071 %add.i62.3 = add i32 %mul.i61.3, %sub106.3
1072 %xor.i63.3 = xor i32 %add.i62.3, %conv33
1073 %add108.3 = add i32 %xor.i53.3, %add113.2
1074 %add110.3 = add i32 %add108.3, %xor.i.3
1075 %add112.3 = add i32 %add110.3, %xor.i58.3
1076 %add113.3 = add i32 %add112.3, %xor.i63.3
1077 ret i32 %add113.3
1078 }