| blob | b8a55d7ef448da9ffff3b5c3b47b7223375f0d45 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3 ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4 ; RUN: FileCheck %s --check-prefix=CHECK-P8
5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
6 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7 ; RUN: FileCheck %s --check-prefix=CHECK-P9
8 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
9 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
10 ; RUN: FileCheck %s --check-prefix=CHECK-BE
12 define <2 x i64> @test2elt(<2 x double> %a) local_unnamed_addr #0 {
13 ; CHECK-P8-LABEL: test2elt:
14 ; CHECK-P8: # %bb.0: # %entry
15 ; CHECK-P8-NEXT: xvcvdpuxds v2, v2
16 ; CHECK-P8-NEXT: blr
17 ;
18 ; CHECK-P9-LABEL: test2elt:
19 ; CHECK-P9: # %bb.0: # %entry
20 ; CHECK-P9-NEXT: xvcvdpuxds v2, v2
21 ; CHECK-P9-NEXT: blr
22 ;
23 ; CHECK-BE-LABEL: test2elt:
24 ; CHECK-BE: # %bb.0: # %entry
25 ; CHECK-BE-NEXT: xvcvdpuxds v2, v2
26 ; CHECK-BE-NEXT: blr
27 entry:
28 %0 = fptoui <2 x double> %a to <2 x i64>
29 ret <2 x i64> %0
30 }
32 define void @test4elt(<4 x i64>* noalias nocapture sret(<4 x i64>) %agg.result, <4 x double>* nocapture readonly) local_unnamed_addr #1 {
33 ; CHECK-P8-LABEL: test4elt:
34 ; CHECK-P8: # %bb.0: # %entry
35 ; CHECK-P8-NEXT: li r5, 16
36 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
37 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
38 ; CHECK-P8-NEXT: xvcvdpuxds vs1, vs1
39 ; CHECK-P8-NEXT: xvcvdpuxds vs0, vs0
40 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
41 ; CHECK-P8-NEXT: stxvd2x vs1, 0, r3
42 ; CHECK-P8-NEXT: blr
43 ;
44 ; CHECK-P9-LABEL: test4elt:
45 ; CHECK-P9: # %bb.0: # %entry
46 ; CHECK-P9-NEXT: lxv vs0, 16(r4)
47 ; CHECK-P9-NEXT: lxv vs1, 0(r4)
48 ; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1
49 ; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0
50 ; CHECK-P9-NEXT: stxv vs0, 16(r3)
51 ; CHECK-P9-NEXT: stxv vs1, 0(r3)
52 ; CHECK-P9-NEXT: blr
53 ;
54 ; CHECK-BE-LABEL: test4elt:
55 ; CHECK-BE: # %bb.0: # %entry
56 ; CHECK-BE-NEXT: lxv vs0, 16(r4)
57 ; CHECK-BE-NEXT: lxv vs1, 0(r4)
58 ; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1
59 ; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0
60 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
61 ; CHECK-BE-NEXT: stxv vs1, 0(r3)
62 ; CHECK-BE-NEXT: blr
63 entry:
64 %a = load <4 x double>, <4 x double>* %0, align 32
65 %1 = fptoui <4 x double> %a to <4 x i64>
66 store <4 x i64> %1, <4 x i64>* %agg.result, align 32
67 ret void
68 }
70 define void @test8elt(<8 x i64>* noalias nocapture sret(<8 x i64>) %agg.result, <8 x double>* nocapture readonly) local_unnamed_addr #1 {
71 ; CHECK-P8-LABEL: test8elt:
72 ; CHECK-P8: # %bb.0: # %entry
73 ; CHECK-P8-NEXT: li r5, 16
74 ; CHECK-P8-NEXT: li r6, 32
75 ; CHECK-P8-NEXT: li r7, 48
76 ; CHECK-P8-NEXT: lxvd2x vs3, 0, r4
77 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
78 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
79 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r7
80 ; CHECK-P8-NEXT: xvcvdpuxds vs3, vs3
81 ; CHECK-P8-NEXT: xvcvdpuxds vs0, vs0
82 ; CHECK-P8-NEXT: xvcvdpuxds vs1, vs1
83 ; CHECK-P8-NEXT: xvcvdpuxds vs2, vs2
84 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r7
85 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r6
86 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
87 ; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
88 ; CHECK-P8-NEXT: blr
89 ;
90 ; CHECK-P9-LABEL: test8elt:
91 ; CHECK-P9: # %bb.0: # %entry
92 ; CHECK-P9-NEXT: lxv vs0, 48(r4)
93 ; CHECK-P9-NEXT: lxv vs1, 32(r4)
94 ; CHECK-P9-NEXT: lxv vs2, 16(r4)
95 ; CHECK-P9-NEXT: lxv vs3, 0(r4)
96 ; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3
97 ; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2
98 ; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1
99 ; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0
100 ; CHECK-P9-NEXT: stxv vs0, 48(r3)
101 ; CHECK-P9-NEXT: stxv vs1, 32(r3)
102 ; CHECK-P9-NEXT: stxv vs2, 16(r3)
103 ; CHECK-P9-NEXT: stxv vs3, 0(r3)
104 ; CHECK-P9-NEXT: blr
105 ;
106 ; CHECK-BE-LABEL: test8elt:
107 ; CHECK-BE: # %bb.0: # %entry
108 ; CHECK-BE-NEXT: lxv vs0, 48(r4)
109 ; CHECK-BE-NEXT: lxv vs1, 32(r4)
110 ; CHECK-BE-NEXT: lxv vs2, 16(r4)
111 ; CHECK-BE-NEXT: lxv vs3, 0(r4)
112 ; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3
113 ; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2
114 ; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1
115 ; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0
116 ; CHECK-BE-NEXT: stxv vs0, 48(r3)
117 ; CHECK-BE-NEXT: stxv vs1, 32(r3)
118 ; CHECK-BE-NEXT: stxv vs2, 16(r3)
119 ; CHECK-BE-NEXT: stxv vs3, 0(r3)
120 ; CHECK-BE-NEXT: blr
121 entry:
122 %a = load <8 x double>, <8 x double>* %0, align 64
123 %1 = fptoui <8 x double> %a to <8 x i64>
124 store <8 x i64> %1, <8 x i64>* %agg.result, align 64
125 ret void
126 }
128 define void @test16elt(<16 x i64>* noalias nocapture sret(<16 x i64>) %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #1 {
129 ; CHECK-P8-LABEL: test16elt:
130 ; CHECK-P8: # %bb.0: # %entry
131 ; CHECK-P8-NEXT: li r5, 16
132 ; CHECK-P8-NEXT: li r6, 32
133 ; CHECK-P8-NEXT: li r7, 64
134 ; CHECK-P8-NEXT: li r8, 96
135 ; CHECK-P8-NEXT: li r9, 112
136 ; CHECK-P8-NEXT: li r10, 80
137 ; CHECK-P8-NEXT: li r11, 48
138 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
139 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
140 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r7
141 ; CHECK-P8-NEXT: lxvd2x vs3, r4, r8
142 ; CHECK-P8-NEXT: lxvd2x vs4, r4, r9
143 ; CHECK-P8-NEXT: lxvd2x vs5, r4, r10
144 ; CHECK-P8-NEXT: lxvd2x vs6, r4, r11
145 ; CHECK-P8-NEXT: lxvd2x vs7, 0, r4
146 ; CHECK-P8-NEXT: xvcvdpuxds vs0, vs0
147 ; CHECK-P8-NEXT: xvcvdpuxds vs1, vs1
148 ; CHECK-P8-NEXT: xvcvdpuxds vs2, vs2
149 ; CHECK-P8-NEXT: xvcvdpuxds vs3, vs3
150 ; CHECK-P8-NEXT: xvcvdpuxds vs4, vs4
151 ; CHECK-P8-NEXT: xvcvdpuxds vs5, vs5
152 ; CHECK-P8-NEXT: xvcvdpuxds vs6, vs6
153 ; CHECK-P8-NEXT: xvcvdpuxds vs7, vs7
154 ; CHECK-P8-NEXT: stxvd2x vs4, r3, r9
155 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r8
156 ; CHECK-P8-NEXT: stxvd2x vs5, r3, r10
157 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r7
158 ; CHECK-P8-NEXT: stxvd2x vs6, r3, r11
159 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r6
160 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
161 ; CHECK-P8-NEXT: stxvd2x vs7, 0, r3
162 ; CHECK-P8-NEXT: blr
163 ;
164 ; CHECK-P9-LABEL: test16elt:
165 ; CHECK-P9: # %bb.0: # %entry
166 ; CHECK-P9-NEXT: lxv vs0, 112(r4)
167 ; CHECK-P9-NEXT: lxv vs1, 96(r4)
168 ; CHECK-P9-NEXT: lxv vs2, 80(r4)
169 ; CHECK-P9-NEXT: lxv vs3, 64(r4)
170 ; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3
171 ; CHECK-P9-NEXT: lxv vs4, 48(r4)
172 ; CHECK-P9-NEXT: lxv vs5, 32(r4)
173 ; CHECK-P9-NEXT: lxv vs6, 16(r4)
174 ; CHECK-P9-NEXT: lxv vs7, 0(r4)
175 ; CHECK-P9-NEXT: xvcvdpuxds vs7, vs7
176 ; CHECK-P9-NEXT: xvcvdpuxds vs6, vs6
177 ; CHECK-P9-NEXT: xvcvdpuxds vs5, vs5
178 ; CHECK-P9-NEXT: xvcvdpuxds vs4, vs4
179 ; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2
180 ; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1
181 ; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0
182 ; CHECK-P9-NEXT: stxv vs0, 112(r3)
183 ; CHECK-P9-NEXT: stxv vs1, 96(r3)
184 ; CHECK-P9-NEXT: stxv vs2, 80(r3)
185 ; CHECK-P9-NEXT: stxv vs3, 64(r3)
186 ; CHECK-P9-NEXT: stxv vs4, 48(r3)
187 ; CHECK-P9-NEXT: stxv vs5, 32(r3)
188 ; CHECK-P9-NEXT: stxv vs6, 16(r3)
189 ; CHECK-P9-NEXT: stxv vs7, 0(r3)
190 ; CHECK-P9-NEXT: blr
191 ;
192 ; CHECK-BE-LABEL: test16elt:
193 ; CHECK-BE: # %bb.0: # %entry
194 ; CHECK-BE-NEXT: lxv vs0, 112(r4)
195 ; CHECK-BE-NEXT: lxv vs1, 96(r4)
196 ; CHECK-BE-NEXT: lxv vs2, 80(r4)
197 ; CHECK-BE-NEXT: lxv vs3, 64(r4)
198 ; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3
199 ; CHECK-BE-NEXT: lxv vs4, 48(r4)
200 ; CHECK-BE-NEXT: lxv vs5, 32(r4)
201 ; CHECK-BE-NEXT: lxv vs6, 16(r4)
202 ; CHECK-BE-NEXT: lxv vs7, 0(r4)
203 ; CHECK-BE-NEXT: xvcvdpuxds vs7, vs7
204 ; CHECK-BE-NEXT: xvcvdpuxds vs6, vs6
205 ; CHECK-BE-NEXT: xvcvdpuxds vs5, vs5
206 ; CHECK-BE-NEXT: xvcvdpuxds vs4, vs4
207 ; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2
208 ; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1
209 ; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0
210 ; CHECK-BE-NEXT: stxv vs0, 112(r3)
211 ; CHECK-BE-NEXT: stxv vs1, 96(r3)
212 ; CHECK-BE-NEXT: stxv vs2, 80(r3)
213 ; CHECK-BE-NEXT: stxv vs3, 64(r3)
214 ; CHECK-BE-NEXT: stxv vs4, 48(r3)
215 ; CHECK-BE-NEXT: stxv vs5, 32(r3)
216 ; CHECK-BE-NEXT: stxv vs6, 16(r3)
217 ; CHECK-BE-NEXT: stxv vs7, 0(r3)
218 ; CHECK-BE-NEXT: blr
219 entry:
220 %a = load <16 x double>, <16 x double>* %0, align 128
221 %1 = fptoui <16 x double> %a to <16 x i64>
222 store <16 x i64> %1, <16 x i64>* %agg.result, align 128
223 ret void
224 }
226 define <2 x i64> @test2elt_signed(<2 x double> %a) local_unnamed_addr #0 {
227 ; CHECK-P8-LABEL: test2elt_signed:
228 ; CHECK-P8: # %bb.0: # %entry
229 ; CHECK-P8-NEXT: xvcvdpsxds v2, v2
230 ; CHECK-P8-NEXT: blr
231 ;
232 ; CHECK-P9-LABEL: test2elt_signed:
233 ; CHECK-P9: # %bb.0: # %entry
234 ; CHECK-P9-NEXT: xvcvdpsxds v2, v2
235 ; CHECK-P9-NEXT: blr
236 ;
237 ; CHECK-BE-LABEL: test2elt_signed:
238 ; CHECK-BE: # %bb.0: # %entry
239 ; CHECK-BE-NEXT: xvcvdpsxds v2, v2
240 ; CHECK-BE-NEXT: blr
241 entry:
242 %0 = fptosi <2 x double> %a to <2 x i64>
243 ret <2 x i64> %0
244 }
246 define void @test4elt_signed(<4 x i64>* noalias nocapture sret(<4 x i64>) %agg.result, <4 x double>* nocapture readonly) local_unnamed_addr #1 {
247 ; CHECK-P8-LABEL: test4elt_signed:
248 ; CHECK-P8: # %bb.0: # %entry
249 ; CHECK-P8-NEXT: li r5, 16
250 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
251 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
252 ; CHECK-P8-NEXT: xvcvdpsxds vs1, vs1
253 ; CHECK-P8-NEXT: xvcvdpsxds vs0, vs0
254 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
255 ; CHECK-P8-NEXT: stxvd2x vs1, 0, r3
256 ; CHECK-P8-NEXT: blr
257 ;
258 ; CHECK-P9-LABEL: test4elt_signed:
259 ; CHECK-P9: # %bb.0: # %entry
260 ; CHECK-P9-NEXT: lxv vs0, 16(r4)
261 ; CHECK-P9-NEXT: lxv vs1, 0(r4)
262 ; CHECK-P9-NEXT: xvcvdpsxds vs1, vs1
263 ; CHECK-P9-NEXT: xvcvdpsxds vs0, vs0
264 ; CHECK-P9-NEXT: stxv vs0, 16(r3)
265 ; CHECK-P9-NEXT: stxv vs1, 0(r3)
266 ; CHECK-P9-NEXT: blr
267 ;
268 ; CHECK-BE-LABEL: test4elt_signed:
269 ; CHECK-BE: # %bb.0: # %entry
270 ; CHECK-BE-NEXT: lxv vs0, 16(r4)
271 ; CHECK-BE-NEXT: lxv vs1, 0(r4)
272 ; CHECK-BE-NEXT: xvcvdpsxds vs1, vs1
273 ; CHECK-BE-NEXT: xvcvdpsxds vs0, vs0
274 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
275 ; CHECK-BE-NEXT: stxv vs1, 0(r3)
276 ; CHECK-BE-NEXT: blr
277 entry:
278 %a = load <4 x double>, <4 x double>* %0, align 32
279 %1 = fptosi <4 x double> %a to <4 x i64>
280 store <4 x i64> %1, <4 x i64>* %agg.result, align 32
281 ret void
282 }
284 define void @test8elt_signed(<8 x i64>* noalias nocapture sret(<8 x i64>) %agg.result, <8 x double>* nocapture readonly) local_unnamed_addr #1 {
285 ; CHECK-P8-LABEL: test8elt_signed:
286 ; CHECK-P8: # %bb.0: # %entry
287 ; CHECK-P8-NEXT: li r5, 16
288 ; CHECK-P8-NEXT: li r6, 32
289 ; CHECK-P8-NEXT: li r7, 48
290 ; CHECK-P8-NEXT: lxvd2x vs3, 0, r4
291 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
292 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
293 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r7
294 ; CHECK-P8-NEXT: xvcvdpsxds vs3, vs3
295 ; CHECK-P8-NEXT: xvcvdpsxds vs0, vs0
296 ; CHECK-P8-NEXT: xvcvdpsxds vs1, vs1
297 ; CHECK-P8-NEXT: xvcvdpsxds vs2, vs2
298 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r7
299 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r6
300 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
301 ; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
302 ; CHECK-P8-NEXT: blr
303 ;
304 ; CHECK-P9-LABEL: test8elt_signed:
305 ; CHECK-P9: # %bb.0: # %entry
306 ; CHECK-P9-NEXT: lxv vs0, 48(r4)
307 ; CHECK-P9-NEXT: lxv vs1, 32(r4)
308 ; CHECK-P9-NEXT: lxv vs2, 16(r4)
309 ; CHECK-P9-NEXT: lxv vs3, 0(r4)
310 ; CHECK-P9-NEXT: xvcvdpsxds vs3, vs3
311 ; CHECK-P9-NEXT: xvcvdpsxds vs2, vs2
312 ; CHECK-P9-NEXT: xvcvdpsxds vs1, vs1
313 ; CHECK-P9-NEXT: xvcvdpsxds vs0, vs0
314 ; CHECK-P9-NEXT: stxv vs0, 48(r3)
315 ; CHECK-P9-NEXT: stxv vs1, 32(r3)
316 ; CHECK-P9-NEXT: stxv vs2, 16(r3)
317 ; CHECK-P9-NEXT: stxv vs3, 0(r3)
318 ; CHECK-P9-NEXT: blr
319 ;
320 ; CHECK-BE-LABEL: test8elt_signed:
321 ; CHECK-BE: # %bb.0: # %entry
322 ; CHECK-BE-NEXT: lxv vs0, 48(r4)
323 ; CHECK-BE-NEXT: lxv vs1, 32(r4)
324 ; CHECK-BE-NEXT: lxv vs2, 16(r4)
325 ; CHECK-BE-NEXT: lxv vs3, 0(r4)
326 ; CHECK-BE-NEXT: xvcvdpsxds vs3, vs3
327 ; CHECK-BE-NEXT: xvcvdpsxds vs2, vs2
328 ; CHECK-BE-NEXT: xvcvdpsxds vs1, vs1
329 ; CHECK-BE-NEXT: xvcvdpsxds vs0, vs0
330 ; CHECK-BE-NEXT: stxv vs0, 48(r3)
331 ; CHECK-BE-NEXT: stxv vs1, 32(r3)
332 ; CHECK-BE-NEXT: stxv vs2, 16(r3)
333 ; CHECK-BE-NEXT: stxv vs3, 0(r3)
334 ; CHECK-BE-NEXT: blr
335 entry:
336 %a = load <8 x double>, <8 x double>* %0, align 64
337 %1 = fptosi <8 x double> %a to <8 x i64>
338 store <8 x i64> %1, <8 x i64>* %agg.result, align 64
339 ret void
340 }
342 define void @test16elt_signed(<16 x i64>* noalias nocapture sret(<16 x i64>) %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #1 {
343 ; CHECK-P8-LABEL: test16elt_signed:
344 ; CHECK-P8: # %bb.0: # %entry
345 ; CHECK-P8-NEXT: li r5, 16
346 ; CHECK-P8-NEXT: li r6, 32
347 ; CHECK-P8-NEXT: li r7, 64
348 ; CHECK-P8-NEXT: li r8, 96
349 ; CHECK-P8-NEXT: li r9, 112
350 ; CHECK-P8-NEXT: li r10, 80
351 ; CHECK-P8-NEXT: li r11, 48
352 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
353 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
354 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r7
355 ; CHECK-P8-NEXT: lxvd2x vs3, r4, r8
356 ; CHECK-P8-NEXT: lxvd2x vs4, r4, r9
357 ; CHECK-P8-NEXT: lxvd2x vs5, r4, r10
358 ; CHECK-P8-NEXT: lxvd2x vs6, r4, r11
359 ; CHECK-P8-NEXT: lxvd2x vs7, 0, r4
360 ; CHECK-P8-NEXT: xvcvdpsxds vs0, vs0
361 ; CHECK-P8-NEXT: xvcvdpsxds vs1, vs1
362 ; CHECK-P8-NEXT: xvcvdpsxds vs2, vs2
363 ; CHECK-P8-NEXT: xvcvdpsxds vs3, vs3
364 ; CHECK-P8-NEXT: xvcvdpsxds vs4, vs4
365 ; CHECK-P8-NEXT: xvcvdpsxds vs5, vs5
366 ; CHECK-P8-NEXT: xvcvdpsxds vs6, vs6
367 ; CHECK-P8-NEXT: xvcvdpsxds vs7, vs7
368 ; CHECK-P8-NEXT: stxvd2x vs4, r3, r9
369 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r8
370 ; CHECK-P8-NEXT: stxvd2x vs5, r3, r10
371 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r7
372 ; CHECK-P8-NEXT: stxvd2x vs6, r3, r11
373 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r6
374 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
375 ; CHECK-P8-NEXT: stxvd2x vs7, 0, r3
376 ; CHECK-P8-NEXT: blr
377 ;
378 ; CHECK-P9-LABEL: test16elt_signed:
379 ; CHECK-P9: # %bb.0: # %entry
380 ; CHECK-P9-NEXT: lxv vs0, 112(r4)
381 ; CHECK-P9-NEXT: lxv vs1, 96(r4)
382 ; CHECK-P9-NEXT: lxv vs2, 80(r4)
383 ; CHECK-P9-NEXT: lxv vs3, 64(r4)
384 ; CHECK-P9-NEXT: xvcvdpsxds vs3, vs3
385 ; CHECK-P9-NEXT: lxv vs4, 48(r4)
386 ; CHECK-P9-NEXT: lxv vs5, 32(r4)
387 ; CHECK-P9-NEXT: lxv vs6, 16(r4)
388 ; CHECK-P9-NEXT: lxv vs7, 0(r4)
389 ; CHECK-P9-NEXT: xvcvdpsxds vs7, vs7
390 ; CHECK-P9-NEXT: xvcvdpsxds vs6, vs6
391 ; CHECK-P9-NEXT: xvcvdpsxds vs5, vs5
392 ; CHECK-P9-NEXT: xvcvdpsxds vs4, vs4
393 ; CHECK-P9-NEXT: xvcvdpsxds vs2, vs2
394 ; CHECK-P9-NEXT: xvcvdpsxds vs1, vs1
395 ; CHECK-P9-NEXT: xvcvdpsxds vs0, vs0
396 ; CHECK-P9-NEXT: stxv vs0, 112(r3)
397 ; CHECK-P9-NEXT: stxv vs1, 96(r3)
398 ; CHECK-P9-NEXT: stxv vs2, 80(r3)
399 ; CHECK-P9-NEXT: stxv vs3, 64(r3)
400 ; CHECK-P9-NEXT: stxv vs4, 48(r3)
401 ; CHECK-P9-NEXT: stxv vs5, 32(r3)
402 ; CHECK-P9-NEXT: stxv vs6, 16(r3)
403 ; CHECK-P9-NEXT: stxv vs7, 0(r3)
404 ; CHECK-P9-NEXT: blr
405 ;
406 ; CHECK-BE-LABEL: test16elt_signed:
407 ; CHECK-BE: # %bb.0: # %entry
408 ; CHECK-BE-NEXT: lxv vs0, 112(r4)
409 ; CHECK-BE-NEXT: lxv vs1, 96(r4)
410 ; CHECK-BE-NEXT: lxv vs2, 80(r4)
411 ; CHECK-BE-NEXT: lxv vs3, 64(r4)
412 ; CHECK-BE-NEXT: xvcvdpsxds vs3, vs3
413 ; CHECK-BE-NEXT: lxv vs4, 48(r4)
414 ; CHECK-BE-NEXT: lxv vs5, 32(r4)
415 ; CHECK-BE-NEXT: lxv vs6, 16(r4)
416 ; CHECK-BE-NEXT: lxv vs7, 0(r4)
417 ; CHECK-BE-NEXT: xvcvdpsxds vs7, vs7
418 ; CHECK-BE-NEXT: xvcvdpsxds vs6, vs6
419 ; CHECK-BE-NEXT: xvcvdpsxds vs5, vs5
420 ; CHECK-BE-NEXT: xvcvdpsxds vs4, vs4
421 ; CHECK-BE-NEXT: xvcvdpsxds vs2, vs2
422 ; CHECK-BE-NEXT: xvcvdpsxds vs1, vs1
423 ; CHECK-BE-NEXT: xvcvdpsxds vs0, vs0
424 ; CHECK-BE-NEXT: stxv vs0, 112(r3)
425 ; CHECK-BE-NEXT: stxv vs1, 96(r3)
426 ; CHECK-BE-NEXT: stxv vs2, 80(r3)
427 ; CHECK-BE-NEXT: stxv vs3, 64(r3)
428 ; CHECK-BE-NEXT: stxv vs4, 48(r3)
429 ; CHECK-BE-NEXT: stxv vs5, 32(r3)
430 ; CHECK-BE-NEXT: stxv vs6, 16(r3)
431 ; CHECK-BE-NEXT: stxv vs7, 0(r3)
432 ; CHECK-BE-NEXT: blr
433 entry:
434 %a = load <16 x double>, <16 x double>* %0, align 128
435 %1 = fptosi <16 x double> %a to <16 x i64>
436 store <16 x i64> %1, <16 x i64>* %agg.result, align 128
437 ret void
438 }