1 # REQUIRES: aarch64, x86
2 # RUN: split-file %s %t.dir && cd %t.dir
4 # RUN: llvm-mc -filetype=obj -triple=arm64ec-windows funcs.s -o funcs-arm64ec.obj
5 # RUN: llvm-mc -filetype=obj -triple=aarch64-windows native-funcs.s -o funcs-aarch64.obj
6 # RUN: llvm-mc -filetype=obj -triple=x86_64-windows space.s -o space-x86_64.obj
7 # RUN: llvm-mc -filetype=obj -triple=aarch64-windows space.s -o space-aarch64.obj
8 # RUN: llvm-mc -filetype=obj -triple=arm64ec-windows %S/Inputs/loadconfig-arm64ec.s -o loadconfig-arm64ec.obj
11 # Test generating range extension thunks for ARM64EC code. Place some x86_64 chunks in a middle
12 # and make sure that thunks stay in ARM64EC code range.
14 # RUN: lld-link -machine:arm64ec -noentry -dll funcs-arm64ec.obj space-x86_64.obj loadconfig-arm64ec.obj -out:test.dll \
15 # RUN: -verbose 2>&1 | FileCheck -check-prefix=VERBOSE %s
16 # VERBOSE: Added 3 thunks with margin {{.*}} in 1 passes
18 # RUN: llvm-objdump -d test.dll | FileCheck --check-prefix=DISASM %s
20 # DISASM: Disassembly of section .code1:
22 # DISASM-NEXT: 0000000180004000 <.code1>:
23 # DISASM-NEXT: 180004000: 36000040 tbz w0, #0x0, 0x180004008 <.code1+0x8>
24 # DISASM-NEXT: 180004004: d65f03c0 ret
25 # DISASM-NEXT: 180004008: b0000050 adrp x16, 0x18000d000
26 # DISASM-NEXT: 18000400c: 91000210 add x16, x16, #0x0
27 # DISASM-NEXT: 180004010: d61f0200 br x16
29 # DISASM-NEXT: Disassembly of section .code2:
31 # DISASM-NEXT: 0000000180005000 <.code2>:
34 # DISASM-NEXT: Disassembly of section .code3:
36 # DISASM-NEXT: 0000000180006000 <.code3>:
38 # DISASM-NEXT: 18000d000: 36000060 tbz w0, #0x0, 0x18000d00c <.code3+0x700c>
39 # DISASM-NEXT: 18000d004: d65f03c0 ret
40 # DISASM-NEXT: 18000d008: 00000000 udf #0x0
41 # DISASM-NEXT: 18000d00c: 90000050 adrp x16, 0x180015000 <.code3+0xf000>
42 # DISASM-NEXT: 18000d010: 91006210 add x16, x16, #0x18
43 # DISASM-NEXT: 18000d014: d61f0200 br x16
45 # DISASM-NEXT: 180015018: 36000040 tbz w0, #0x0, 0x180015020 <.code3+0xf020>
46 # DISASM-NEXT: 18001501c: d65f03c0 ret
47 # DISASM-NEXT: 180015020: f0ffff70 adrp x16, 0x180004000 <.code1>
48 # DISASM-NEXT: 180015024: 91000210 add x16, x16, #0x0
49 # DISASM-NEXT: 180015028: d61f0200 br x16
51 # RUN: llvm-readobj --coff-load-config test.dll | FileCheck --check-prefix=LOADCFG %s
54 # LOADCFG-NEXT: 0x4000 - 0x4014 ARM64EC
55 # LOADCFG-NEXT: 0x5000 - 0x5300 X64
56 # LOADCFG-NEXT: 0x6000 - 0x1502C ARM64EC
60 # A similar test using a hybrid binary and native placeholder chunks.
62 # RUN: lld-link -machine:arm64x -noentry -dll funcs-arm64ec.obj space-aarch64.obj loadconfig-arm64ec.obj -out:testx.dll \
63 # RUN: -verbose 2>&1 | FileCheck -check-prefix=VERBOSE %s
64 # RUN: llvm-objdump -d testx.dll | FileCheck --check-prefix=DISASM %s
66 # RUN: llvm-readobj --coff-load-config testx.dll | FileCheck --check-prefix=LOADCFGX %s
69 # LOADCFGX-NEXT: 0x4000 - 0x4014 ARM64EC
70 # LOADCFGX-NEXT: 0x5000 - 0x5300 ARM64
71 # LOADCFGX-NEXT: 0x6000 - 0x1502C ARM64EC
75 # Test a hybrid ARM64X binary which requires range extension thunks for both native and EC relocations.
77 # RUN: lld-link -machine:arm64x -noentry -dll funcs-arm64ec.obj funcs-aarch64.obj loadconfig-arm64ec.obj -out:testx2.dll \
78 # RUN: -verbose 2>&1 | FileCheck -check-prefix=VERBOSEX %s
79 # VERBOSEX: Added 5 thunks with margin {{.*}} in 1 passes
81 # RUN: llvm-objdump -d testx2.dll | FileCheck --check-prefix=DISASMX %s
83 # DISASMX: Disassembly of section .code1:
85 # DISASMX-NEXT: 0000000180004000 <.code1>:
86 # DISASMX-NEXT: 180004000: 36000040 tbz w0, #0x0, 0x180004008 <.code1+0x8>
87 # DISASMX-NEXT: 180004004: d65f03c0 ret
88 # DISASMX-NEXT: 180004008: b0000050 adrp x16, 0x18000d000
89 # DISASMX-NEXT: 18000400c: 91000210 add x16, x16, #0x0
90 # DISASMX-NEXT: 180004010: d61f0200 br x16
92 # DISASMX-NEXT: Disassembly of section .code2:
94 # DISASMX-NEXT: 0000000180005000 <.code2>:
95 # DISASMX-NEXT: 180005000: 36000040 tbz w0, #0x0, 0x180005008 <.code2+0x8>
96 # DISASMX-NEXT: 180005004: d65f03c0 ret
97 # DISASMX-NEXT: 180005008: b0000090 adrp x16, 0x180016000
98 # DISASMX-NEXT: 18000500c: 91000210 add x16, x16, #0x0
99 # DISASMX-NEXT: 180005010: d61f0200 br x16
101 # DISASMX-NEXT: Disassembly of section .code3:
103 # DISASMX-NEXT: 0000000180006000 <.code3>:
105 # DISASMX-NEXT: 18000d000: 36000060 tbz w0, #0x0, 0x18000d00c <.code3+0x700c>
106 # DISASMX-NEXT: 18000d004: d65f03c0 ret
107 # DISASMX-NEXT: 18000d008: 00000000 udf #0x0
108 # DISASMX-NEXT: 18000d00c: 90000050 adrp x16, 0x180015000 <.code3+0xf000>
109 # DISASMX-NEXT: 18000d010: 91006210 add x16, x16, #0x18
110 # DISASMX-NEXT: 18000d014: d61f0200 br x16
112 # DISASMX-NEXT: 180015018: 36000040 tbz w0, #0x0, 0x180015020 <.code3+0xf020>
113 # DISASMX-NEXT: 18001501c: d65f03c0 ret
114 # DISASMX-NEXT: 180015020: f0ffff70 adrp x16, 0x180004000 <.code1>
115 # DISASMX-NEXT: 180015024: 91000210 add x16, x16, #0x0
116 # DISASMX-NEXT: 180015028: d61f0200 br x16
118 # DISASMX-NEXT: Disassembly of section .code4:
120 # DISASMX-NEXT: 0000000180016000 <.code4>:
121 # DISASMX-NEXT: 180016000: 36000040 tbz w0, #0x0, 0x180016008 <.code4+0x8>
122 # DISASMX-NEXT: 180016004: d65f03c0 ret
123 # DISASMX-NEXT: 180016008: f0ffff70 adrp x16, 0x180005000 <.code2>
124 # DISASMX-NEXT: 18001600c: 91000210 add x16, x16, #0x0
125 # DISASMX-NEXT: 180016010: d61f0200 br x16
127 # RUN: llvm-readobj --coff-load-config testx2.dll | FileCheck --check-prefix=LOADCFGX2 %s
129 # LOADCFGX2: CodeMap [
130 # LOADCFGX2-NEXT: 0x4000 - 0x4014 ARM64EC
131 # LOADCFGX2-NEXT: 0x5000 - 0x5014 ARM64
132 # LOADCFGX2-NEXT: 0x6000 - 0x1502C ARM64EC
133 # LOADCFGX2-NEXT: 0x16000 - 0x16014 ARM64
142 .section .code1, "xr"
147 .section .code3$a, "xr"
150 .section .code3$b, "xr"
156 .section .code3$c, "xr"
159 .section .code3$d, "xr"
166 .section .code2$a, "xr"
168 .section .code2$b, "xr"
170 .section .code2$c, "xr"
177 .section .code2, "xr"
182 .section .code4, "xr"