1 //===--- X86.cpp - Implement X86 target feature support -------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements X86 TargetInfo objects.
11 //===----------------------------------------------------------------------===//
14 #include "clang/Basic/Builtins.h"
15 #include "clang/Basic/Diagnostic.h"
16 #include "clang/Basic/TargetBuiltins.h"
17 #include "llvm/ADT/StringExtras.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/TargetParser/X86TargetParser.h"
26 static constexpr Builtin::Info BuiltinInfoX86
[] = {
27 #define BUILTIN(ID, TYPE, ATTRS) \
28 {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
29 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
30 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
31 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
32 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::HEADER, LANGS},
33 #include "clang/Basic/BuiltinsX86.def"
35 #define BUILTIN(ID, TYPE, ATTRS) \
36 {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
37 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
38 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
39 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
40 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::HEADER, LANGS},
41 #include "clang/Basic/BuiltinsX86_64.def"
44 static const char *const GCCRegNames
[] = {
45 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
46 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
47 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
48 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
49 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
50 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
51 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
52 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
53 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
54 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
55 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
56 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
57 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
58 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
59 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
60 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
61 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
62 "k2", "k3", "k4", "k5", "k6", "k7",
63 "cr0", "cr2", "cr3", "cr4", "cr8",
64 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
65 "bnd0", "bnd1", "bnd2", "bnd3",
66 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7",
69 const TargetInfo::AddlRegName AddlRegNames
[] = {
70 {{"al", "ah", "eax", "rax"}, 0},
71 {{"bl", "bh", "ebx", "rbx"}, 3},
72 {{"cl", "ch", "ecx", "rcx"}, 2},
73 {{"dl", "dh", "edx", "rdx"}, 1},
78 {{"r8d", "r8w", "r8b"}, 38},
79 {{"r9d", "r9w", "r9b"}, 39},
80 {{"r10d", "r10w", "r10b"}, 40},
81 {{"r11d", "r11w", "r11b"}, 41},
82 {{"r12d", "r12w", "r12b"}, 42},
83 {{"r13d", "r13w", "r13b"}, 43},
84 {{"r14d", "r14w", "r14b"}, 44},
85 {{"r15d", "r15w", "r15b"}, 45},
88 } // namespace targets
91 using namespace clang
;
92 using namespace clang::targets
;
94 bool X86TargetInfo::setFPMath(StringRef Name
) {
106 bool X86TargetInfo::initFeatureMap(
107 llvm::StringMap
<bool> &Features
, DiagnosticsEngine
&Diags
, StringRef CPU
,
108 const std::vector
<std::string
> &FeaturesVec
) const {
109 // FIXME: This *really* should not be here.
110 // X86_64 always has SSE2.
111 if (getTriple().getArch() == llvm::Triple::x86_64
)
112 setFeatureEnabled(Features
, "sse2", true);
114 using namespace llvm::X86
;
116 SmallVector
<StringRef
, 16> CPUFeatures
;
117 getFeaturesForCPU(CPU
, CPUFeatures
);
118 for (auto &F
: CPUFeatures
)
119 setFeatureEnabled(Features
, F
, true);
121 std::vector
<std::string
> UpdatedFeaturesVec
;
122 for (const auto &Feature
: FeaturesVec
) {
123 // Expand general-regs-only to -x86, -mmx and -sse
124 if (Feature
== "+general-regs-only") {
125 UpdatedFeaturesVec
.push_back("-x87");
126 UpdatedFeaturesVec
.push_back("-mmx");
127 UpdatedFeaturesVec
.push_back("-sse");
131 UpdatedFeaturesVec
.push_back(Feature
);
134 if (!TargetInfo::initFeatureMap(Features
, Diags
, CPU
, UpdatedFeaturesVec
))
137 // Can't do this earlier because we need to be able to explicitly enable
138 // or disable these features and the things that they depend upon.
140 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
141 auto I
= Features
.find("sse4.2");
142 if (I
!= Features
.end() && I
->getValue() &&
143 !llvm::is_contained(UpdatedFeaturesVec
, "-popcnt"))
144 Features
["popcnt"] = true;
146 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
148 I
= Features
.find("sse");
149 if (I
!= Features
.end() && I
->getValue() &&
150 !llvm::is_contained(UpdatedFeaturesVec
, "-mmx"))
151 Features
["mmx"] = true;
153 // Enable xsave if avx is enabled and xsave is not explicitly disabled.
154 I
= Features
.find("avx");
155 if (I
!= Features
.end() && I
->getValue() &&
156 !llvm::is_contained(UpdatedFeaturesVec
, "-xsave"))
157 Features
["xsave"] = true;
159 // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled.
160 I
= Features
.find("sse4.2");
161 if (I
!= Features
.end() && I
->getValue() &&
162 !llvm::is_contained(UpdatedFeaturesVec
, "-crc32"))
163 Features
["crc32"] = true;
168 void X86TargetInfo::setFeatureEnabled(llvm::StringMap
<bool> &Features
,
169 StringRef Name
, bool Enabled
) const {
170 if (Name
== "sse4") {
171 // We can get here via the __target__ attribute since that's not controlled
172 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
173 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
181 Features
[Name
] = Enabled
;
182 llvm::X86::updateImpliedFeatures(Name
, Enabled
, Features
);
185 /// handleTargetFeatures - Perform initialization based on the user
186 /// configured set of features.
187 bool X86TargetInfo::handleTargetFeatures(std::vector
<std::string
> &Features
,
188 DiagnosticsEngine
&Diags
) {
189 for (const auto &Feature
: Features
) {
190 if (Feature
[0] != '+')
193 if (Feature
== "+aes") {
195 } else if (Feature
== "+vaes") {
197 } else if (Feature
== "+pclmul") {
199 } else if (Feature
== "+vpclmulqdq") {
200 HasVPCLMULQDQ
= true;
201 } else if (Feature
== "+lzcnt") {
203 } else if (Feature
== "+rdrnd") {
205 } else if (Feature
== "+fsgsbase") {
207 } else if (Feature
== "+bmi") {
209 } else if (Feature
== "+bmi2") {
211 } else if (Feature
== "+popcnt") {
213 } else if (Feature
== "+rtm") {
215 } else if (Feature
== "+prfchw") {
217 } else if (Feature
== "+rdseed") {
219 } else if (Feature
== "+adx") {
221 } else if (Feature
== "+tbm") {
223 } else if (Feature
== "+lwp") {
225 } else if (Feature
== "+fma") {
227 } else if (Feature
== "+f16c") {
229 } else if (Feature
== "+gfni") {
231 } else if (Feature
== "+avx512cd") {
233 } else if (Feature
== "+avx512vpopcntdq") {
234 HasAVX512VPOPCNTDQ
= true;
235 } else if (Feature
== "+avx512vnni") {
236 HasAVX512VNNI
= true;
237 } else if (Feature
== "+avx512bf16") {
238 HasAVX512BF16
= true;
239 } else if (Feature
== "+avx512er") {
241 } else if (Feature
== "+avx512fp16") {
242 HasAVX512FP16
= true;
243 HasLegalHalfType
= true;
244 } else if (Feature
== "+avx512pf") {
246 } else if (Feature
== "+avx512dq") {
248 } else if (Feature
== "+avx512bitalg") {
249 HasAVX512BITALG
= true;
250 } else if (Feature
== "+avx512bw") {
252 } else if (Feature
== "+avx512vl") {
254 } else if (Feature
== "+avx512vbmi") {
255 HasAVX512VBMI
= true;
256 } else if (Feature
== "+avx512vbmi2") {
257 HasAVX512VBMI2
= true;
258 } else if (Feature
== "+avx512ifma") {
259 HasAVX512IFMA
= true;
260 } else if (Feature
== "+avx512vp2intersect") {
261 HasAVX512VP2INTERSECT
= true;
262 } else if (Feature
== "+sha") {
264 } else if (Feature
== "+shstk") {
266 } else if (Feature
== "+movbe") {
268 } else if (Feature
== "+sgx") {
270 } else if (Feature
== "+cx8") {
272 } else if (Feature
== "+cx16") {
274 } else if (Feature
== "+fxsr") {
276 } else if (Feature
== "+xsave") {
278 } else if (Feature
== "+xsaveopt") {
280 } else if (Feature
== "+xsavec") {
282 } else if (Feature
== "+xsaves") {
284 } else if (Feature
== "+mwaitx") {
286 } else if (Feature
== "+pku") {
288 } else if (Feature
== "+clflushopt") {
289 HasCLFLUSHOPT
= true;
290 } else if (Feature
== "+clwb") {
292 } else if (Feature
== "+wbnoinvd") {
294 } else if (Feature
== "+prefetchi") {
296 } else if (Feature
== "+prefetchwt1") {
297 HasPREFETCHWT1
= true;
298 } else if (Feature
== "+clzero") {
300 } else if (Feature
== "+cldemote") {
302 } else if (Feature
== "+rdpid") {
304 } else if (Feature
== "+rdpru") {
306 } else if (Feature
== "+kl") {
308 } else if (Feature
== "+widekl") {
310 } else if (Feature
== "+retpoline-external-thunk") {
311 HasRetpolineExternalThunk
= true;
312 } else if (Feature
== "+sahf") {
314 } else if (Feature
== "+waitpkg") {
316 } else if (Feature
== "+movdiri") {
318 } else if (Feature
== "+movdir64b") {
320 } else if (Feature
== "+pconfig") {
322 } else if (Feature
== "+ptwrite") {
324 } else if (Feature
== "+invpcid") {
326 } else if (Feature
== "+enqcmd") {
328 } else if (Feature
== "+hreset") {
330 } else if (Feature
== "+amx-bf16") {
332 } else if (Feature
== "+amx-fp16") {
334 } else if (Feature
== "+amx-int8") {
336 } else if (Feature
== "+amx-tile") {
338 } else if (Feature
== "+cmpccxadd") {
340 } else if (Feature
== "+raoint") {
342 } else if (Feature
== "+avxifma") {
344 } else if (Feature
== "+avxneconvert") {
345 HasAVXNECONVERT
= true;
346 } else if (Feature
== "+avxvnni") {
348 } else if (Feature
== "+avxvnniint8") {
349 HasAVXVNNIINT8
= true;
350 } else if (Feature
== "+serialize") {
352 } else if (Feature
== "+tsxldtrk") {
354 } else if (Feature
== "+uintr") {
356 } else if (Feature
== "+crc32") {
358 } else if (Feature
== "+x87") {
362 X86SSEEnum Level
= llvm::StringSwitch
<X86SSEEnum
>(Feature
)
363 .Case("+avx512f", AVX512F
)
366 .Case("+sse4.2", SSE42
)
367 .Case("+sse4.1", SSE41
)
368 .Case("+ssse3", SSSE3
)
373 SSELevel
= std::max(SSELevel
, Level
);
375 HasFloat16
= SSELevel
>= SSE2
;
377 HasBFloat16
= SSELevel
>= SSE2
;
379 MMX3DNowEnum ThreeDNowLevel
= llvm::StringSwitch
<MMX3DNowEnum
>(Feature
)
380 .Case("+3dnowa", AMD3DNowAthlon
)
381 .Case("+3dnow", AMD3DNow
)
383 .Default(NoMMX3DNow
);
384 MMX3DNowLevel
= std::max(MMX3DNowLevel
, ThreeDNowLevel
);
386 XOPEnum XLevel
= llvm::StringSwitch
<XOPEnum
>(Feature
)
389 .Case("+sse4a", SSE4A
)
391 XOPLevel
= std::max(XOPLevel
, XLevel
);
394 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
395 // matches the selected sse level.
396 if ((FPMath
== FP_SSE
&& SSELevel
< SSE1
) ||
397 (FPMath
== FP_387
&& SSELevel
>= SSE1
)) {
398 Diags
.Report(diag::err_target_unsupported_fpmath
)
399 << (FPMath
== FP_SSE
? "sse" : "387");
403 // FIXME: We should allow long double type on 32-bits to match with GCC.
404 // This requires backend to be able to lower f80 without x87 first.
405 if (!HasX87
&& LongDoubleFormat
== &llvm::APFloat::x87DoubleExtended())
406 HasLongDouble
= false;
411 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
412 /// definitions for this particular subtarget.
413 void X86TargetInfo::getTargetDefines(const LangOptions
&Opts
,
414 MacroBuilder
&Builder
) const {
415 // Inline assembly supports X86 flag outputs.
416 Builder
.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
418 std::string CodeModel
= getTargetOpts().CodeModel
;
419 if (CodeModel
== "default")
421 Builder
.defineMacro("__code_model_" + CodeModel
+ "__");
423 // Target identification.
424 if (getTriple().getArch() == llvm::Triple::x86_64
) {
425 Builder
.defineMacro("__amd64__");
426 Builder
.defineMacro("__amd64");
427 Builder
.defineMacro("__x86_64");
428 Builder
.defineMacro("__x86_64__");
429 if (getTriple().getArchName() == "x86_64h") {
430 Builder
.defineMacro("__x86_64h");
431 Builder
.defineMacro("__x86_64h__");
434 DefineStd(Builder
, "i386", Opts
);
437 Builder
.defineMacro("__SEG_GS");
438 Builder
.defineMacro("__SEG_FS");
439 Builder
.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
440 Builder
.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
442 // Subtarget options.
443 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
444 // truly should be based on -mtune options.
445 using namespace llvm::X86
;
450 // The rest are coming from the i386 define above.
451 Builder
.defineMacro("__tune_i386__");
457 defineCPUMacros(Builder
, "i486");
460 Builder
.defineMacro("__pentium_mmx__");
461 Builder
.defineMacro("__tune_pentium_mmx__");
465 defineCPUMacros(Builder
, "i586");
466 defineCPUMacros(Builder
, "pentium");
470 Builder
.defineMacro("__tune_pentium3__");
474 Builder
.defineMacro("__tune_pentium2__");
478 defineCPUMacros(Builder
, "i686");
479 defineCPUMacros(Builder
, "pentiumpro");
482 defineCPUMacros(Builder
, "pentium4");
487 defineCPUMacros(Builder
, "nocona");
491 defineCPUMacros(Builder
, "core2");
494 defineCPUMacros(Builder
, "atom");
497 defineCPUMacros(Builder
, "slm");
500 defineCPUMacros(Builder
, "goldmont");
502 case CK_GoldmontPlus
:
503 defineCPUMacros(Builder
, "goldmont_plus");
506 defineCPUMacros(Builder
, "tremont");
514 case CK_SkylakeClient
:
515 case CK_SkylakeServer
:
519 case CK_IcelakeClient
:
521 case CK_IcelakeServer
:
523 case CK_SapphireRapids
:
527 case CK_Sierraforest
:
529 case CK_Graniterapids
:
530 case CK_Emeraldrapids
:
531 // FIXME: Historically, we defined this legacy name, it would be nice to
532 // remove it at some point. We've never exposed fine-grained names for
533 // recent primary x86 CPUs, and we should keep it that way.
534 defineCPUMacros(Builder
, "corei7");
537 defineCPUMacros(Builder
, "knl");
542 defineCPUMacros(Builder
, "i586", /*Tuning*/false);
543 defineCPUMacros(Builder
, "pentium", /*Tuning*/false);
544 Builder
.defineMacro("__tune_lakemont__");
547 Builder
.defineMacro("__k6_2__");
548 Builder
.defineMacro("__tune_k6_2__");
551 if (CPU
!= CK_K6_2
) { // In case of fallthrough
552 // FIXME: GCC may be enabling these in cases where some other k6
553 // architecture is specified but -m3dnow is explicitly provided. The
554 // exact semantics need to be determined and emulated here.
555 Builder
.defineMacro("__k6_3__");
556 Builder
.defineMacro("__tune_k6_3__");
560 defineCPUMacros(Builder
, "k6");
564 defineCPUMacros(Builder
, "athlon");
565 if (SSELevel
!= NoSSE
) {
566 Builder
.defineMacro("__athlon_sse__");
567 Builder
.defineMacro("__tune_athlon_sse__");
573 defineCPUMacros(Builder
, "k8");
580 defineCPUMacros(Builder
, "amdfam10");
583 defineCPUMacros(Builder
, "btver1");
586 defineCPUMacros(Builder
, "btver2");
589 defineCPUMacros(Builder
, "bdver1");
592 defineCPUMacros(Builder
, "bdver2");
595 defineCPUMacros(Builder
, "bdver3");
598 defineCPUMacros(Builder
, "bdver4");
601 defineCPUMacros(Builder
, "znver1");
604 defineCPUMacros(Builder
, "znver2");
607 defineCPUMacros(Builder
, "znver3");
610 defineCPUMacros(Builder
, "znver4");
613 defineCPUMacros(Builder
, "geode");
617 // Target properties.
618 Builder
.defineMacro("__REGISTER_PREFIX__", "");
620 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
621 // functions in glibc header files that use FP Stack inline asm which the
622 // backend can't deal with (PR879).
623 Builder
.defineMacro("__NO_MATH_INLINES");
626 Builder
.defineMacro("__AES__");
629 Builder
.defineMacro("__VAES__");
632 Builder
.defineMacro("__PCLMUL__");
635 Builder
.defineMacro("__VPCLMULQDQ__");
637 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM,
638 // the feature flag only applies to 64-bit mode.
639 if (HasLAHFSAHF
|| getTriple().getArch() == llvm::Triple::x86
)
640 Builder
.defineMacro("__LAHF_SAHF__");
643 Builder
.defineMacro("__LZCNT__");
646 Builder
.defineMacro("__RDRND__");
649 Builder
.defineMacro("__FSGSBASE__");
652 Builder
.defineMacro("__BMI__");
655 Builder
.defineMacro("__BMI2__");
658 Builder
.defineMacro("__POPCNT__");
661 Builder
.defineMacro("__RTM__");
664 Builder
.defineMacro("__PRFCHW__");
667 Builder
.defineMacro("__RDSEED__");
670 Builder
.defineMacro("__ADX__");
673 Builder
.defineMacro("__TBM__");
676 Builder
.defineMacro("__LWP__");
679 Builder
.defineMacro("__MWAITX__");
682 Builder
.defineMacro("__MOVBE__");
686 Builder
.defineMacro("__XOP__");
689 Builder
.defineMacro("__FMA4__");
692 Builder
.defineMacro("__SSE4A__");
699 Builder
.defineMacro("__FMA__");
702 Builder
.defineMacro("__F16C__");
705 Builder
.defineMacro("__GFNI__");
708 Builder
.defineMacro("__AVX512CD__");
709 if (HasAVX512VPOPCNTDQ
)
710 Builder
.defineMacro("__AVX512VPOPCNTDQ__");
712 Builder
.defineMacro("__AVX512VNNI__");
714 Builder
.defineMacro("__AVX512BF16__");
716 Builder
.defineMacro("__AVX512ER__");
718 Builder
.defineMacro("__AVX512FP16__");
720 Builder
.defineMacro("__AVX512PF__");
722 Builder
.defineMacro("__AVX512DQ__");
724 Builder
.defineMacro("__AVX512BITALG__");
726 Builder
.defineMacro("__AVX512BW__");
728 Builder
.defineMacro("__AVX512VL__");
730 Builder
.defineMacro("__AVX512VBMI__");
732 Builder
.defineMacro("__AVX512VBMI2__");
734 Builder
.defineMacro("__AVX512IFMA__");
735 if (HasAVX512VP2INTERSECT
)
736 Builder
.defineMacro("__AVX512VP2INTERSECT__");
738 Builder
.defineMacro("__SHA__");
741 Builder
.defineMacro("__FXSR__");
743 Builder
.defineMacro("__XSAVE__");
745 Builder
.defineMacro("__XSAVEOPT__");
747 Builder
.defineMacro("__XSAVEC__");
749 Builder
.defineMacro("__XSAVES__");
751 Builder
.defineMacro("__PKU__");
753 Builder
.defineMacro("__CLFLUSHOPT__");
755 Builder
.defineMacro("__CLWB__");
757 Builder
.defineMacro("__WBNOINVD__");
759 Builder
.defineMacro("__SHSTK__");
761 Builder
.defineMacro("__SGX__");
763 Builder
.defineMacro("__PREFETCHI__");
765 Builder
.defineMacro("__PREFETCHWT1__");
767 Builder
.defineMacro("__CLZERO__");
769 Builder
.defineMacro("__KL__");
771 Builder
.defineMacro("__WIDEKL__");
773 Builder
.defineMacro("__RDPID__");
775 Builder
.defineMacro("__RDPRU__");
777 Builder
.defineMacro("__CLDEMOTE__");
779 Builder
.defineMacro("__WAITPKG__");
781 Builder
.defineMacro("__MOVDIRI__");
783 Builder
.defineMacro("__MOVDIR64B__");
785 Builder
.defineMacro("__PCONFIG__");
787 Builder
.defineMacro("__PTWRITE__");
789 Builder
.defineMacro("__INVPCID__");
791 Builder
.defineMacro("__ENQCMD__");
793 Builder
.defineMacro("__HRESET__");
795 Builder
.defineMacro("__AMX_TILE__");
797 Builder
.defineMacro("__AMX_INT8__");
799 Builder
.defineMacro("__AMX_BF16__");
801 Builder
.defineMacro("__AMX_FP16__");
803 Builder
.defineMacro("__CMPCCXADD__");
805 Builder
.defineMacro("__RAOINT__");
807 Builder
.defineMacro("__AVXIFMA__");
809 Builder
.defineMacro("__AVXNECONVERT__");
811 Builder
.defineMacro("__AVXVNNI__");
813 Builder
.defineMacro("__AVXVNNIINT8__");
815 Builder
.defineMacro("__SERIALIZE__");
817 Builder
.defineMacro("__TSXLDTRK__");
819 Builder
.defineMacro("__UINTR__");
821 Builder
.defineMacro("__CRC32__");
823 // Each case falls through to the previous one here.
826 Builder
.defineMacro("__AVX512F__");
829 Builder
.defineMacro("__AVX2__");
832 Builder
.defineMacro("__AVX__");
835 Builder
.defineMacro("__SSE4_2__");
838 Builder
.defineMacro("__SSE4_1__");
841 Builder
.defineMacro("__SSSE3__");
844 Builder
.defineMacro("__SSE3__");
847 Builder
.defineMacro("__SSE2__");
848 Builder
.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
851 Builder
.defineMacro("__SSE__");
852 Builder
.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
858 if (Opts
.MicrosoftExt
&& getTriple().getArch() == llvm::Triple::x86
) {
868 Builder
.defineMacro("_M_IX86_FP", Twine(2));
871 Builder
.defineMacro("_M_IX86_FP", Twine(1));
874 Builder
.defineMacro("_M_IX86_FP", Twine(0));
879 // Each case falls through to the previous one here.
880 switch (MMX3DNowLevel
) {
882 Builder
.defineMacro("__3dNOW_A__");
885 Builder
.defineMacro("__3dNOW__");
888 Builder
.defineMacro("__MMX__");
894 if (CPU
>= CK_i486
|| CPU
== CK_None
) {
895 Builder
.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
896 Builder
.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
897 Builder
.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
900 Builder
.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
901 if (HasCX16
&& getTriple().getArch() == llvm::Triple::x86_64
)
902 Builder
.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
905 Builder
.defineMacro("__SIZEOF_FLOAT128__", "16");
908 bool X86TargetInfo::isValidFeatureName(StringRef Name
) const {
909 return llvm::StringSwitch
<bool>(Name
)
911 .Case("3dnowa", true)
914 .Case("amx-bf16", true)
915 .Case("amx-fp16", true)
916 .Case("amx-int8", true)
917 .Case("amx-tile", true)
920 .Case("avx512f", true)
921 .Case("avx512cd", true)
922 .Case("avx512vpopcntdq", true)
923 .Case("avx512vnni", true)
924 .Case("avx512bf16", true)
925 .Case("avx512er", true)
926 .Case("avx512fp16", true)
927 .Case("avx512pf", true)
928 .Case("avx512dq", true)
929 .Case("avx512bitalg", true)
930 .Case("avx512bw", true)
931 .Case("avx512vl", true)
932 .Case("avx512vbmi", true)
933 .Case("avx512vbmi2", true)
934 .Case("avx512ifma", true)
935 .Case("avx512vp2intersect", true)
936 .Case("avxifma", true)
937 .Case("avxneconvert", true)
938 .Case("avxvnni", true)
939 .Case("avxvnniint8", true)
942 .Case("cldemote", true)
943 .Case("clflushopt", true)
945 .Case("clzero", true)
946 .Case("cmpccxadd", true)
949 .Case("enqcmd", true)
953 .Case("fsgsbase", true)
955 .Case("general-regs-only", true)
957 .Case("hreset", true)
958 .Case("invpcid", true)
960 .Case("widekl", true)
965 .Case("movdiri", true)
966 .Case("movdir64b", true)
967 .Case("mwaitx", true)
968 .Case("pclmul", true)
969 .Case("pconfig", true)
971 .Case("popcnt", true)
972 .Case("prefetchi", true)
973 .Case("prefetchwt1", true)
974 .Case("prfchw", true)
975 .Case("ptwrite", true)
976 .Case("raoint", true)
980 .Case("rdseed", true)
983 .Case("serialize", true)
992 .Case("sse4.1", true)
993 .Case("sse4.2", true)
996 .Case("tsxldtrk", true)
999 .Case("vpclmulqdq", true)
1000 .Case("wbnoinvd", true)
1001 .Case("waitpkg", true)
1004 .Case("xsave", true)
1005 .Case("xsavec", true)
1006 .Case("xsaves", true)
1007 .Case("xsaveopt", true)
1011 bool X86TargetInfo::hasFeature(StringRef Feature
) const {
1012 return llvm::StringSwitch
<bool>(Feature
)
1013 .Case("adx", HasADX
)
1014 .Case("aes", HasAES
)
1015 .Case("amx-bf16", HasAMXBF16
)
1016 .Case("amx-fp16", HasAMXFP16
)
1017 .Case("amx-int8", HasAMXINT8
)
1018 .Case("amx-tile", HasAMXTILE
)
1019 .Case("avx", SSELevel
>= AVX
)
1020 .Case("avx2", SSELevel
>= AVX2
)
1021 .Case("avx512f", SSELevel
>= AVX512F
)
1022 .Case("avx512cd", HasAVX512CD
)
1023 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ
)
1024 .Case("avx512vnni", HasAVX512VNNI
)
1025 .Case("avx512bf16", HasAVX512BF16
)
1026 .Case("avx512er", HasAVX512ER
)
1027 .Case("avx512fp16", HasAVX512FP16
)
1028 .Case("avx512pf", HasAVX512PF
)
1029 .Case("avx512dq", HasAVX512DQ
)
1030 .Case("avx512bitalg", HasAVX512BITALG
)
1031 .Case("avx512bw", HasAVX512BW
)
1032 .Case("avx512vl", HasAVX512VL
)
1033 .Case("avx512vbmi", HasAVX512VBMI
)
1034 .Case("avx512vbmi2", HasAVX512VBMI2
)
1035 .Case("avx512ifma", HasAVX512IFMA
)
1036 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT
)
1037 .Case("avxifma", HasAVXIFMA
)
1038 .Case("avxneconvert", HasAVXNECONVERT
)
1039 .Case("avxvnni", HasAVXVNNI
)
1040 .Case("avxvnniint8", HasAVXVNNIINT8
)
1041 .Case("bmi", HasBMI
)
1042 .Case("bmi2", HasBMI2
)
1043 .Case("cldemote", HasCLDEMOTE
)
1044 .Case("clflushopt", HasCLFLUSHOPT
)
1045 .Case("clwb", HasCLWB
)
1046 .Case("clzero", HasCLZERO
)
1047 .Case("cmpccxadd", HasCMPCCXADD
)
1048 .Case("crc32", HasCRC32
)
1049 .Case("cx8", HasCX8
)
1050 .Case("cx16", HasCX16
)
1051 .Case("enqcmd", HasENQCMD
)
1052 .Case("f16c", HasF16C
)
1053 .Case("fma", HasFMA
)
1054 .Case("fma4", XOPLevel
>= FMA4
)
1055 .Case("fsgsbase", HasFSGSBASE
)
1056 .Case("fxsr", HasFXSR
)
1057 .Case("gfni", HasGFNI
)
1058 .Case("hreset", HasHRESET
)
1059 .Case("invpcid", HasINVPCID
)
1061 .Case("widekl", HasWIDEKL
)
1062 .Case("lwp", HasLWP
)
1063 .Case("lzcnt", HasLZCNT
)
1064 .Case("mm3dnow", MMX3DNowLevel
>= AMD3DNow
)
1065 .Case("mm3dnowa", MMX3DNowLevel
>= AMD3DNowAthlon
)
1066 .Case("mmx", MMX3DNowLevel
>= MMX
)
1067 .Case("movbe", HasMOVBE
)
1068 .Case("movdiri", HasMOVDIRI
)
1069 .Case("movdir64b", HasMOVDIR64B
)
1070 .Case("mwaitx", HasMWAITX
)
1071 .Case("pclmul", HasPCLMUL
)
1072 .Case("pconfig", HasPCONFIG
)
1073 .Case("pku", HasPKU
)
1074 .Case("popcnt", HasPOPCNT
)
1075 .Case("prefetchi", HasPREFETCHI
)
1076 .Case("prefetchwt1", HasPREFETCHWT1
)
1077 .Case("prfchw", HasPRFCHW
)
1078 .Case("ptwrite", HasPTWRITE
)
1079 .Case("raoint", HasRAOINT
)
1080 .Case("rdpid", HasRDPID
)
1081 .Case("rdpru", HasRDPRU
)
1082 .Case("rdrnd", HasRDRND
)
1083 .Case("rdseed", HasRDSEED
)
1084 .Case("retpoline-external-thunk", HasRetpolineExternalThunk
)
1085 .Case("rtm", HasRTM
)
1086 .Case("sahf", HasLAHFSAHF
)
1087 .Case("serialize", HasSERIALIZE
)
1088 .Case("sgx", HasSGX
)
1089 .Case("sha", HasSHA
)
1090 .Case("shstk", HasSHSTK
)
1091 .Case("sse", SSELevel
>= SSE1
)
1092 .Case("sse2", SSELevel
>= SSE2
)
1093 .Case("sse3", SSELevel
>= SSE3
)
1094 .Case("ssse3", SSELevel
>= SSSE3
)
1095 .Case("sse4.1", SSELevel
>= SSE41
)
1096 .Case("sse4.2", SSELevel
>= SSE42
)
1097 .Case("sse4a", XOPLevel
>= SSE4A
)
1098 .Case("tbm", HasTBM
)
1099 .Case("tsxldtrk", HasTSXLDTRK
)
1100 .Case("uintr", HasUINTR
)
1101 .Case("vaes", HasVAES
)
1102 .Case("vpclmulqdq", HasVPCLMULQDQ
)
1103 .Case("wbnoinvd", HasWBNOINVD
)
1104 .Case("waitpkg", HasWAITPKG
)
1106 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86
)
1107 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64
)
1108 .Case("x87", HasX87
)
1109 .Case("xop", XOPLevel
>= XOP
)
1110 .Case("xsave", HasXSAVE
)
1111 .Case("xsavec", HasXSAVEC
)
1112 .Case("xsaves", HasXSAVES
)
1113 .Case("xsaveopt", HasXSAVEOPT
)
1117 // We can't use a generic validation scheme for the features accepted here
1118 // versus subtarget features accepted in the target attribute because the
1119 // bitfield structure that's initialized in the runtime only supports the
1120 // below currently rather than the full range of subtarget features. (See
1121 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
1122 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr
) const {
1123 return llvm::StringSwitch
<bool>(FeatureStr
)
1124 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) .Case(STR, true)
1125 #include "llvm/TargetParser/X86TargetParser.def"
1129 static llvm::X86::ProcessorFeatures
getFeature(StringRef Name
) {
1130 return llvm::StringSwitch
<llvm::X86::ProcessorFeatures
>(Name
)
1131 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \
1132 .Case(STR, llvm::X86::FEATURE_##ENUM)
1134 #include "llvm/TargetParser/X86TargetParser.def"
1136 // Note, this function should only be used after ensuring the value is
1137 // correct, so it asserts if the value is out of range.
1140 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name
) const {
1141 // Valid CPUs have a 'key feature' that compares just better than its key
1143 using namespace llvm::X86
;
1144 CPUKind Kind
= parseArchX86(Name
);
1145 if (Kind
!= CK_None
) {
1146 ProcessorFeatures KeyFeature
= getKeyFeature(Kind
);
1147 return (getFeaturePriority(KeyFeature
) << 1) + 1;
1150 // Now we know we have a feature, so get its priority and shift it a few so
1151 // that we have sufficient room for the CPUs (above).
1152 return getFeaturePriority(getFeature(Name
)) << 1;
1155 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name
) const {
1156 return llvm::StringSwitch
<bool>(Name
)
1157 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, true)
1158 #define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, true)
1159 #include "llvm/TargetParser/X86TargetParser.def"
1163 static StringRef
CPUSpecificCPUDispatchNameDealias(StringRef Name
) {
1164 return llvm::StringSwitch
<StringRef
>(Name
)
1165 #define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, NAME)
1166 #include "llvm/TargetParser/X86TargetParser.def"
1170 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name
) const {
1171 return llvm::StringSwitch
<char>(CPUSpecificCPUDispatchNameDealias(Name
))
1172 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, MANGLING)
1173 #include "llvm/TargetParser/X86TargetParser.def"
1177 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures(
1178 StringRef Name
, llvm::SmallVectorImpl
<StringRef
> &Features
) const {
1179 StringRef WholeList
=
1180 llvm::StringSwitch
<StringRef
>(CPUSpecificCPUDispatchNameDealias(Name
))
1181 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, FEATURES)
1182 #include "llvm/TargetParser/X86TargetParser.def"
1184 WholeList
.split(Features
, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false);
1187 StringRef
X86TargetInfo::getCPUSpecificTuneName(StringRef Name
) const {
1188 return llvm::StringSwitch
<StringRef
>(Name
)
1189 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, TUNE_NAME)
1190 #define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, TUNE_NAME)
1191 #include "llvm/TargetParser/X86TargetParser.def"
1195 // We can't use a generic validation scheme for the cpus accepted here
1196 // versus subtarget cpus accepted in the target attribute because the
1197 // variables intitialized by the runtime only support the below currently
1198 // rather than the full range of cpus.
1199 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr
) const {
1200 return llvm::StringSwitch
<bool>(FeatureStr
)
1201 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1202 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1203 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true)
1204 #define X86_CPU_SUBTYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1205 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true)
1206 #include "llvm/TargetParser/X86TargetParser.def"
1210 static unsigned matchAsmCCConstraint(const char *&Name
) {
1211 auto RV
= llvm::StringSwitch
<unsigned>(Name
)
1244 bool X86TargetInfo::validateAsmConstraint(
1245 const char *&Name
, TargetInfo::ConstraintInfo
&Info
) const {
1249 // Constant constraints.
1250 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1252 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1253 // x86_64 instructions.
1255 Info
.setRequiresImmediate();
1258 Info
.setRequiresImmediate(0, 31);
1261 Info
.setRequiresImmediate(0, 63);
1264 Info
.setRequiresImmediate(-128, 127);
1267 Info
.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1270 Info
.setRequiresImmediate(0, 3);
1273 Info
.setRequiresImmediate(0, 255);
1276 Info
.setRequiresImmediate(0, 127);
1278 // Register constraints.
1279 case 'Y': // 'Y' is the first character for several 2-character constraints.
1280 // Shift the pointer to the second character of the constraint.
1285 case 'z': // First SSE register.
1287 case 't': // Any SSE register, when SSE2 is enabled.
1288 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1289 case 'm': // Any MMX register, when inter-unit moves enabled.
1290 case 'k': // AVX512 arch mask registers: k1-k7.
1291 Info
.setAllowsRegister();
1294 case 'f': // Any x87 floating point stack register.
1295 // Constraint 'f' cannot be used for output operands.
1296 if (Info
.ConstraintStr
[0] == '=')
1298 Info
.setAllowsRegister();
1306 case 'A': // edx:eax.
1307 case 't': // Top of floating point stack.
1308 case 'u': // Second from top of floating point stack.
1309 case 'q': // Any register accessible as [r]l: a, b, c, and d.
1310 case 'y': // Any MMX register.
1311 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1312 case 'x': // Any SSE register.
1313 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1314 // for intermideate k reg operations).
1315 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1316 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1317 case 'l': // "Index" registers: any general register that can be used as an
1318 // index in a base+index memory access.
1319 Info
.setAllowsRegister();
1321 // Floating point constant constraints.
1322 case 'C': // SSE floating point constant.
1323 case 'G': // x87 floating point constant.
1326 // CC condition changes.
1327 if (auto Len
= matchAsmCCConstraint(Name
)) {
1329 Info
.setAllowsRegister();
1336 // Below is based on the following information:
1337 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1338 // | Processor Name | Cache Line Size (Bytes) | Source |
1339 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1340 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf |
1341 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) |
1342 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html |
1343 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html |
1344 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html |
1345 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html |
1346 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" |
1347 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html |
1348 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html |
1349 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html |
1350 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html |
1351 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" |
1352 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" |
1353 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" |
1354 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html |
1355 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" |
1356 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " |
1357 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1358 std::optional
<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
1359 using namespace llvm::X86
;
1399 case CK_GoldmontPlus
:
1403 case CK_SandyBridge
:
1407 case CK_SkylakeClient
:
1408 case CK_SkylakeServer
:
1409 case CK_Cascadelake
:
1414 case CK_SapphireRapids
:
1415 case CK_IcelakeClient
:
1417 case CK_IcelakeServer
:
1421 case CK_Sierraforest
:
1423 case CK_Graniterapids
:
1424 case CK_Emeraldrapids
:
1457 // The following currently have unknown cache line sizes (but they are probably all 64):
1460 return std::nullopt
;
1462 llvm_unreachable("Unknown CPU kind");
1465 bool X86TargetInfo::validateOutputSize(const llvm::StringMap
<bool> &FeatureMap
,
1466 StringRef Constraint
,
1467 unsigned Size
) const {
1468 // Strip off constraint modifiers.
1469 while (Constraint
[0] == '=' || Constraint
[0] == '+' || Constraint
[0] == '&')
1470 Constraint
= Constraint
.substr(1);
1472 return validateOperandSize(FeatureMap
, Constraint
, Size
);
1475 bool X86TargetInfo::validateInputSize(const llvm::StringMap
<bool> &FeatureMap
,
1476 StringRef Constraint
,
1477 unsigned Size
) const {
1478 return validateOperandSize(FeatureMap
, Constraint
, Size
);
1481 bool X86TargetInfo::validateOperandSize(const llvm::StringMap
<bool> &FeatureMap
,
1482 StringRef Constraint
,
1483 unsigned Size
) const {
1484 switch (Constraint
[0]) {
1488 // Registers k0-k7 (AVX512) size limit is 64 bit.
1496 // 'Y' is the first character for several 2-character constraints.
1497 switch (Constraint
[1]) {
1501 // 'Ym' is synonymous with 'y'.
1506 if (hasFeatureEnabled(FeatureMap
, "avx512f"))
1507 // ZMM0 can be used if target supports AVX512F.
1508 return Size
<= 512U;
1509 else if (hasFeatureEnabled(FeatureMap
, "avx"))
1510 // YMM0 can be used if target supports AVX.
1511 return Size
<= 256U;
1512 else if (hasFeatureEnabled(FeatureMap
, "sse"))
1513 return Size
<= 128U;
1518 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1519 if (SSELevel
< SSE2
)
1526 if (hasFeatureEnabled(FeatureMap
, "avx512f"))
1527 // 512-bit zmm registers can be used if target supports AVX512F.
1528 return Size
<= 512U;
1529 else if (hasFeatureEnabled(FeatureMap
, "avx"))
1530 // 256-bit ymm registers can be used if target supports AVX.
1531 return Size
<= 256U;
1532 return Size
<= 128U;
1539 std::string
X86TargetInfo::convertConstraint(const char *&Constraint
) const {
1540 switch (*Constraint
) {
1542 if (auto Len
= matchAsmCCConstraint(Constraint
)) {
1543 std::string Converted
= "{" + std::string(Constraint
, Len
) + "}";
1544 Constraint
+= Len
- 1;
1547 return std::string(1, *Constraint
);
1549 return std::string("{ax}");
1551 return std::string("{bx}");
1553 return std::string("{cx}");
1555 return std::string("{dx}");
1557 return std::string("{si}");
1559 return std::string("{di}");
1560 case 'p': // Keep 'p' constraint (address).
1561 return std::string("p");
1562 case 't': // top of floating point stack.
1563 return std::string("{st}");
1564 case 'u': // second from top of floating point stack.
1565 return std::string("{st(1)}"); // second from top of floating point stack.
1567 switch (Constraint
[1]) {
1569 // Break from inner switch and fall through (copy single char),
1570 // continue parsing after copying the current constraint into
1571 // the return string.
1579 // "^" hints llvm that this is a 2 letter constraint.
1580 // "Constraint++" is used to promote the string iterator
1581 // to the next constraint.
1582 return std::string("^") + std::string(Constraint
++, 2);
1586 return std::string(1, *Constraint
);
1590 void X86TargetInfo::fillValidCPUList(SmallVectorImpl
<StringRef
> &Values
) const {
1591 bool Only64Bit
= getTriple().getArch() != llvm::Triple::x86
;
1592 llvm::X86::fillValidCPUArchList(Values
, Only64Bit
);
1595 void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl
<StringRef
> &Values
) const {
1596 llvm::X86::fillValidTuneCPUList(Values
);
1599 ArrayRef
<const char *> X86TargetInfo::getGCCRegNames() const {
1600 return llvm::ArrayRef(GCCRegNames
);
1603 ArrayRef
<TargetInfo::AddlRegName
> X86TargetInfo::getGCCAddlRegNames() const {
1604 return llvm::ArrayRef(AddlRegNames
);
1607 ArrayRef
<Builtin::Info
> X86_32TargetInfo::getTargetBuiltins() const {
1608 return llvm::ArrayRef(BuiltinInfoX86
, clang::X86::LastX86CommonBuiltin
-
1609 Builtin::FirstTSBuiltin
+ 1);
1612 ArrayRef
<Builtin::Info
> X86_64TargetInfo::getTargetBuiltins() const {
1613 return llvm::ArrayRef(BuiltinInfoX86
,
1614 X86::LastTSBuiltin
- Builtin::FirstTSBuiltin
);