clang/test/CodeGen/PowerPC/builtins-ppc-build-pair-mma.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
   3 // RUN: -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-LE
   4 // RUN: %clang_cc1 -O3 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
   5 // RUN: -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-BE
   6
   7 // CHECK-LE-LABEL: @test1(
   8 // CHECK-LE-NEXT:  entry:
   9 // CHECK-LE-NEXT:    [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> [[VC4:%.*]], <16 x i8> [[VC3:%.*]], <16 x i8> [[VC2:%.*]], <16 x i8> [[VC1:%.*]])
  10 // CHECK-LE-NEXT:    store <512 x i1> [[TMP0]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2:![0-9]+]]
  11 // CHECK-LE-NEXT:    ret void
  12 //
  13 // CHECK-BE-LABEL: @test1(
  14 // CHECK-BE-NEXT:  entry:
  15 // CHECK-BE-NEXT:    [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> [[VC1:%.*]], <16 x i8> [[VC2:%.*]], <16 x i8> [[VC3:%.*]], <16 x i8> [[VC4:%.*]])
  16 // CHECK-BE-NEXT:    store <512 x i1> [[TMP0]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2:![0-9]+]]
  17 // CHECK-BE-NEXT:    ret void
  18 //
  19 void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc1, vector unsigned char vc2,
  20             vector unsigned char vc3, vector unsigned char vc4, unsigned char *resp) {
  21   __vector_quad vq = *((__vector_quad *)vqp);
  22   __vector_pair vp = *((__vector_pair *)vpp);
  23   __vector_quad res;
  24   __builtin_mma_build_acc(&res, vc1, vc2, vc3, vc4);
  25   *((__vector_quad *)resp) = res;
  26 }
  27
  28 // CHECK-LE-LABEL: @test2(
  29 // CHECK-LE-NEXT:  entry:
  30 // CHECK-LE-NEXT:    [[TMP0:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> [[VC2:%.*]], <16 x i8> [[VC1:%.*]])
  31 // CHECK-LE-NEXT:    store <256 x i1> [[TMP0]], ptr [[RESP:%.*]], align 32, !tbaa [[TBAA6:![0-9]+]]
  32 // CHECK-LE-NEXT:    ret void
  33 //
  34 // CHECK-BE-LABEL: @test2(
  35 // CHECK-BE-NEXT:  entry:
  36 // CHECK-BE-NEXT:    [[TMP0:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> [[VC1:%.*]], <16 x i8> [[VC2:%.*]])
  37 // CHECK-BE-NEXT:    store <256 x i1> [[TMP0]], ptr [[RESP:%.*]], align 32, !tbaa [[TBAA6:![0-9]+]]
  38 // CHECK-BE-NEXT:    ret void
  39 //
  40 void test2(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc1,
  41             vector unsigned char vc2, unsigned char *resp) {
  42   __vector_quad vq = *((__vector_quad *)vqp);
  43   __vector_pair vp = *((__vector_pair *)vpp);
  44   __vector_pair res;
  45   __builtin_vsx_build_pair(&res, vc1, vc2);
  46   *((__vector_pair *)resp) = res;
  47 }