[clang] Handle __declspec() attributes in using
[llvm-project.git] / clang / test / CodeGen / PowerPC / vector-compat-pixel-bool-ternary.c
blobd04875d58380a70a2a187c4308694437de4e0376
1 // RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
2 // RUN: -faltivec-src-compat=mixed -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
3 // RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
4 // RUN: -faltivec-src-compat=gcc -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1| FileCheck %s --check-prefix=ERROR
5 // RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
6 // RUN: -faltivec-src-compat=xl -triple powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
7 // RUN: %clang -mcpu=pwr8 -faltivec-src-compat=xl --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
8 // RUN: %clang -mcpu=pwr9 -faltivec-src-compat=xl --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
10 // CHECK-LABEL: @bi8(
11 // CHECK: [[A_ADDR:%.*]] = alloca <16 x i8>, align 16
12 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca <16 x i8>, align 16
13 // CHECK-NEXT: store <16 x i8> [[A:%.*]], ptr [[A_ADDR]], align 16
14 // CHECK-NEXT: store <16 x i8> [[B:%.*]], ptr [[B_ADDR]], align 16
15 // CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[A_ADDR]], align 16
16 // CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[B_ADDR]], align 16
17 // CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequb.p(i32 2, <16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
18 // CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
19 // CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
20 // CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
21 // CHECK-NEXT: ret i32 [[COND]]
23 // ERROR: error: used type '__attribute__((__vector_size__(16 * sizeof(char)))) char' (vector of 16 'char' values) where arithmetic or pointer type is required
24 int bi8(vector bool char a, vector bool char b) {
25 return a == b ? 3 : 7;
28 // CHECK-LABEL: @bi16(
29 // CHECK: [[A_ADDR:%.*]] = alloca <8 x i16>, align 16
30 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca <8 x i16>, align 16
31 // CHECK-NEXT: store <8 x i16> [[A:%.*]], ptr [[A_ADDR]], align 16
32 // CHECK-NEXT: store <8 x i16> [[B:%.*]], ptr [[B_ADDR]], align 16
33 // CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr [[A_ADDR]], align 16
34 // CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[B_ADDR]], align 16
35 // CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequh.p(i32 2, <8 x i16> [[TMP0]], <8 x i16> [[TMP1]])
36 // CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
37 // CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
38 // CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
39 // CHECK-NEXT: ret i32 [[COND]]
41 // ERROR: error: used type '__attribute__((__vector_size__(8 * sizeof(short)))) short' (vector of 8 'short' values) where arithmetic or pointer type is required
42 int bi16(vector bool short a, vector bool short b) {
43 return a == b ? 3 : 7;
46 // CHECK-LABEL: @bi32(
47 // CHECK: [[A_ADDR:%.*]] = alloca <4 x i32>, align 16
48 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca <4 x i32>, align 16
49 // CHECK-NEXT: store <4 x i32> [[A:%.*]], ptr [[A_ADDR]], align 16
50 // CHECK-NEXT: store <4 x i32> [[B:%.*]], ptr [[B_ADDR]], align 16
51 // CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[A_ADDR]], align 16
52 // CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[B_ADDR]], align 16
53 // CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequw.p(i32 2, <4 x i32> [[TMP0]], <4 x i32> [[TMP1]])
54 // CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
55 // CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
56 // CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
57 // CHECK-NEXT: ret i32 [[COND]]
59 // ERROR: error: used type '__attribute__((__vector_size__(4 * sizeof(long)))) long' (vector of 4 'long' values) where arithmetic or pointer type is required
60 int bi32(vector bool int a, vector bool int b) {
61 return a == b ? 3 : 7;
64 // CHECK-LABEL: @bi64(
65 // CHECK: [[A_ADDR:%.*]] = alloca <2 x i64>, align 16
66 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca <2 x i64>, align 16
67 // CHECK-NEXT: store <2 x i64> [[A:%.*]], ptr [[A_ADDR]], align 16
68 // CHECK-NEXT: store <2 x i64> [[B:%.*]], ptr [[B_ADDR]], align 16
69 // CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr [[A_ADDR]], align 16
70 // CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[B_ADDR]], align 16
71 // CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequd.p(i32 2, <2 x i64> [[TMP0]], <2 x i64> [[TMP1]])
72 // CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
73 // CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
74 // CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
75 // CHECK-NEXT: ret i32 [[COND]]
77 // ERROR: error: used type '__attribute__((__vector_size__(2 * sizeof(long long)))) long long' (vector of 2 'long long' values) where arithmetic or pointer type is required
78 int bi64(vector bool long long a, vector bool long long b) {
79 return a == b ? 3 : 7;
82 // CHECK-LABEL: @VecPixel(
83 // CHECK: [[A_ADDR:%.*]] = alloca <8 x i16>, align 16
84 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca <8 x i16>, align 16
85 // CHECK-NEXT: store <8 x i16> [[A:%.*]], ptr [[A_ADDR]], align 16
86 // CHECK-NEXT: store <8 x i16> [[B:%.*]], ptr [[B_ADDR]], align 16
87 // CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr [[A_ADDR]], align 16
88 // CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[B_ADDR]], align 16
89 // CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequh.p(i32 2, <8 x i16> [[TMP0]], <8 x i16> [[TMP1]])
90 // CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
91 // CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
92 // CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
93 // CHECK-NEXT: ret i32 [[COND]]
95 // ERROR: error: used type '__attribute__((__vector_size__(8 * sizeof(short)))) short' (vector of 8 'short' values) where arithmetic or pointer type is required
96 int VecPixel(vector pixel a, vector pixel b) {
97 return a == b ? 3 : 7;