clang/test/CodeGen/aarch64-neon-shifts.c

   1 // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
   2 // RUN:  -disable-O0-optnone -ffp-contract=fast -S -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s
   3
   4 // REQUIRES: aarch64-registered-target || arm-registered-target
   5
   6 #include <arm_neon.h>
   7
   8 uint8x8_t test_shift_vshr(uint8x8_t a) {
   9   // CHECK-LABEL: test_shift_vshr
  10   // CHECK: %{{.*}} = lshr <8 x i8> %a, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
  11   return vshr_n_u8(a, 5);
  12 }
  13
  14 int8x8_t test_shift_vshr_smax(int8x8_t a) {
  15   // CHECK-LABEL: test_shift_vshr_smax
  16   // CHECK: %{{.*}} = ashr <8 x i8> %a, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
  17   return vshr_n_s8(a, 8);
  18 }
  19
  20 uint8x8_t test_shift_vshr_umax(uint8x8_t a) {
  21   // CHECK-LABEL: test_shift_vshr_umax
  22   // CHECK: ret <8 x i8> zeroinitializer
  23   return vshr_n_u8(a, 8);
  24 }
  25
  26 uint8x8_t test_shift_vsra(uint8x8_t a, uint8x8_t b) {
  27   // CHECK-LABEL: test_shift_vsra
  28   // CHECK: %[[SHR:.*]] = lshr <8 x i8> %b, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
  29   // CHECK: %{{.*}} = add <8 x i8> %a, %[[SHR]]
  30   return vsra_n_u8(a, b, 5);
  31 }
  32
  33 int8x8_t test_shift_vsra_smax(int8x8_t a, int8x8_t b) {
  34   // CHECK-LABEL: test_shift_vsra_smax
  35   // CHECK: %[[SHR:.*]] = ashr <8 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
  36   // CHECK: %{{.*}} = add <8 x i8> %a, %[[SHR]]
  37   return vsra_n_s8(a, b, 8);
  38 }
  39
  40 uint8x8_t test_shift_vsra_umax(uint8x8_t a, uint8x8_t b) {
  41   // CHECK-LABEL: test_shift_vsra_umax
  42   // CHECK: [[RES:%.*]] = add <8 x i8> %a, zeroinitializer
  43   // CHECK: ret <8 x i8> [[RES]]
  44   return vsra_n_u8(a, b, 8);
  45 }