clang/test/CodeGen/attr-target-clones-aarch64.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-attributes --check-globals --include-generated-funcs
   2 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -S -emit-llvm -o - %s | FileCheck %s
   3 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature -fmv -S -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK-NOFMV
   4
   5 int __attribute__((target_clones("lse+aes", "sve2"))) ftc(void) { return 0; }
   6 int __attribute__((target_clones("sha2", "sha2+memtag2", " default "))) ftc_def(void) { return 1; }
   7 int __attribute__((target_clones("sha2", "default"))) ftc_dup1(void) { return 2; }
   8 int __attribute__((target_clones("fp", "crc+dotprod"))) ftc_dup2(void) { return 3; }
   9 int foo() {
  10   return ftc() + ftc_def() + ftc_dup1() + ftc_dup2();
  11 }
  12
  13 inline int __attribute__((target_clones("rng+simd", "rcpc+predres", "sve2-aes+wfxt"))) ftc_inline1(void) { return 1; }
  14 inline int __attribute__((target_clones("fp16", "fcma+sve2-bitperm", "default"))) ftc_inline2(void);
  15 inline int __attribute__((target_clones("bti", "sve+sb"))) ftc_inline3(void) { return 3; }
  16
  17 int __attribute__((target_clones("default"))) ftc_direct(void) { return 4; }
  18
  19 int __attribute__((target_clones("default"))) main() {
  20   return ftc_inline1() + ftc_inline2() + ftc_inline3() + ftc_direct();
  21 }
  22 inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))) ftc_inline2(void) { return 2; };
  23
  24
  25 // CHECK: @__aarch64_cpu_features = external dso_local global { i64 }
  26 // CHECK: @ftc.ifunc = weak_odr ifunc i32 (), ptr @ftc.resolver
  27 // CHECK: @ftc_def.ifunc = weak_odr ifunc i32 (), ptr @ftc_def.resolver
  28 // CHECK: @ftc_dup1.ifunc = weak_odr ifunc i32 (), ptr @ftc_dup1.resolver
  29 // CHECK: @ftc_dup2.ifunc = weak_odr ifunc i32 (), ptr @ftc_dup2.resolver
  30 // CHECK: @ftc_inline1.ifunc = weak_odr ifunc i32 (), ptr @ftc_inline1.resolver
  31 // CHECK: @ftc_inline2.ifunc = weak_odr ifunc i32 (), ptr @ftc_inline2.resolver
  32 // CHECK: @ftc_inline3.ifunc = weak_odr ifunc i32 (), ptr @ftc_inline3.resolver
  33
  34 // CHECK: Function Attrs: noinline nounwind optnone
  35 // CHECK-LABEL: @ftc._MaesMlse(
  36 // CHECK-NEXT:  entry:
  37 // CHECK-NEXT:    ret i32 0
  38 // CHECK: Function Attrs: noinline nounwind optnone
  39 // CHECK-LABEL: @ftc._Msve2(
  40 // CHECK-NEXT:  entry:
  41 // CHECK-NEXT:    ret i32 0
  42 // CHECK: Function Attrs: noinline nounwind optnone
  43 // CHECK-LABEL: @ftc(
  44 // CHECK-NEXT:  entry:
  45 // CHECK-NEXT:    ret i32 0
  46 // CHECK-LABEL: @ftc.resolver(
  47 // CHECK-NEXT:  resolver_entry:
  48 // CHECK-NEXT:    call void @init_cpu_features_resolver()
  49 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
  50 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 16512
  51 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 16512
  52 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
  53 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
  54 // CHECK:       resolver_return:
  55 // CHECK-NEXT:    ret ptr @ftc._MaesMlse
  56 // CHECK:       resolver_else:
  57 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
  58 // CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 68719476736
  59 // CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 68719476736
  60 // CHECK-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
  61 // CHECK-NEXT:    br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
  62 // CHECK:       resolver_return1:
  63 // CHECK-NEXT:    ret ptr @ftc._Msve2
  64 // CHECK:       resolver_else2:
  65 // CHECK-NEXT:    ret ptr @ftc
  66 // CHECK: Function Attrs: noinline nounwind optnone
  67 // CHECK-LABEL: @ftc_def._Msha2(
  68 // CHECK-NEXT:  entry:
  69 // CHECK-NEXT:    ret i32 1
  70 // CHECK: Function Attrs: noinline nounwind optnone
  71 // CHECK-LABEL: @ftc_def._Mmemtag2Msha2(
  72 // CHECK-NEXT:  entry:
  73 // CHECK-NEXT:    ret i32 1
  74 // CHECK: Function Attrs: noinline nounwind optnone
  75 // CHECK-LABEL: @ftc_def(
  76 // CHECK-NEXT:  entry:
  77 // CHECK-NEXT:    ret i32 1
  78 // CHECK-LABEL: @ftc_def.resolver(
  79 // CHECK-NEXT:  resolver_entry:
  80 // CHECK-NEXT:    call void @init_cpu_features_resolver()
  81 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
  82 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 17592186048512
  83 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 17592186048512
  84 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
  85 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
  86 // CHECK:       resolver_return:
  87 // CHECK-NEXT:    ret ptr @ftc_def._Mmemtag2Msha2
  88 // CHECK:       resolver_else:
  89 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
  90 // CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 4096
  91 // CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 4096
  92 // CHECK-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
  93 // CHECK-NEXT:    br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
  94 // CHECK:       resolver_return1:
  95 // CHECK-NEXT:    ret ptr @ftc_def._Msha2
  96 // CHECK:       resolver_else2:
  97 // CHECK-NEXT:    ret ptr @ftc_def
  98 // CHECK: Function Attrs: noinline nounwind optnone
  99 // CHECK-LABEL: @ftc_dup1._Msha2(
 100 // CHECK-NEXT:  entry:
 101 // CHECK-NEXT:    ret i32 2
 102 // CHECK: Function Attrs: noinline nounwind optnone
 103 // CHECK-LABEL: @ftc_dup1(
 104 // CHECK-NEXT:  entry:
 105 // CHECK-NEXT:    ret i32 2
 106 // CHECK-LABEL: @ftc_dup1.resolver(
 107 // CHECK-NEXT:  resolver_entry:
 108 // CHECK-NEXT:    call void @init_cpu_features_resolver()
 109 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 110 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 4096
 111 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4096
 112 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 113 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 114 // CHECK:       resolver_return:
 115 // CHECK-NEXT:    ret ptr @ftc_dup1._Msha2
 116 // CHECK:       resolver_else:
 117 // CHECK-NEXT:    ret ptr @ftc_dup1
 118 // CHECK: Function Attrs: noinline nounwind optnone
 119 // CHECK-LABEL: @ftc_dup2._Mfp(
 120 // CHECK-NEXT:  entry:
 121 // CHECK-NEXT:    ret i32 3
 122 // CHECK: Function Attrs: noinline nounwind optnone
 123 // CHECK-LABEL: @ftc_dup2._McrcMdotprod(
 124 // CHECK-NEXT:  entry:
 125 // CHECK-NEXT:    ret i32 3
 126 // CHECK: Function Attrs: noinline nounwind optnone
 127 // CHECK-LABEL: @ftc_dup2(
 128 // CHECK-NEXT:  entry:
 129 // CHECK-NEXT:    ret i32 3
 130 // CHECK-LABEL: @ftc_dup2.resolver(
 131 // CHECK-NEXT:  resolver_entry:
 132 // CHECK-NEXT:    call void @init_cpu_features_resolver()
 133 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 134 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 1040
 135 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1040
 136 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 137 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 138 // CHECK:       resolver_return:
 139 // CHECK-NEXT:    ret ptr @ftc_dup2._McrcMdotprod
 140 // CHECK:       resolver_else:
 141 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 142 // CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 256
 143 // CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 256
 144 // CHECK-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
 145 // CHECK-NEXT:    br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 146 // CHECK:       resolver_return1:
 147 // CHECK-NEXT:    ret ptr @ftc_dup2._Mfp
 148 // CHECK:       resolver_else2:
 149 // CHECK-NEXT:    ret ptr @ftc_dup2
 150 // CHECK: Function Attrs: noinline nounwind optnone
 151 // CHECK-LABEL: @foo(
 152 // CHECK-NEXT:  entry:
 153 // CHECK-NEXT:    [[CALL:%.*]] = call i32 @ftc.ifunc()
 154 // CHECK-NEXT:    [[CALL1:%.*]] = call i32 @ftc_def.ifunc()
 155 // CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]
 156 // CHECK-NEXT:    [[CALL2:%.*]] = call i32 @ftc_dup1.ifunc()
 157 // CHECK-NEXT:    [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]]
 158 // CHECK-NEXT:    [[CALL4:%.*]] = call i32 @ftc_dup2.ifunc()
 159 // CHECK-NEXT:    [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]]
 160 // CHECK-NEXT:    ret i32 [[ADD5]]
 161 // CHECK: Function Attrs: noinline nounwind optnone
 162 // CHECK-LABEL: @ftc_direct(
 163 // CHECK-NEXT:  entry:
 164 // CHECK-NEXT:    ret i32 4
 165 // CHECK: Function Attrs: noinline nounwind optnone
 166 // CHECK-LABEL: @main(
 167 // CHECK-NEXT:  entry:
 168 // CHECK-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 169 // CHECK-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 170 // CHECK-NEXT:    [[CALL:%.*]] = call i32 @ftc_inline1.ifunc()
 171 // CHECK-NEXT:    [[CALL1:%.*]] = call i32 @ftc_inline2.ifunc()
 172 // CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]
 173 // CHECK-NEXT:    [[CALL2:%.*]] = call i32 @ftc_inline3.ifunc()
 174 // CHECK-NEXT:    [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]]
 175 // CHECK-NEXT:    [[CALL4:%.*]] = call i32 @ftc_direct()
 176 // CHECK-NEXT:    [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]]
 177 // CHECK-NEXT:    ret i32 [[ADD5]]
 178 // CHECK-LABEL: @ftc_inline1.resolver(
 179 // CHECK-NEXT:  resolver_entry:
 180 // CHECK-NEXT:    call void @init_cpu_features_resolver()
 181 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 182 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 18014535948435456
 183 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 18014535948435456
 184 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 185 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 186 // CHECK:       resolver_return:
 187 // CHECK-NEXT:    ret ptr @ftc_inline1._Msve2-aesMwfxt
 188 // CHECK:       resolver_else:
 189 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 190 // CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 140737492549632
 191 // CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 140737492549632
 192 // CHECK-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
 193 // CHECK-NEXT:    br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 194 // CHECK:       resolver_return1:
 195 // CHECK-NEXT:    ret ptr @ftc_inline1._MpredresMrcpc
 196 // CHECK:       resolver_else2:
 197 // CHECK-NEXT:    [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 198 // CHECK-NEXT:    [[TMP9:%.*]] = and i64 [[TMP8]], 513
 199 // CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 513
 200 // CHECK-NEXT:    [[TMP11:%.*]] = and i1 true, [[TMP10]]
 201 // CHECK-NEXT:    br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
 202 // CHECK:       resolver_return3:
 203 // CHECK-NEXT:    ret ptr @ftc_inline1._MrngMsimd
 204 // CHECK:       resolver_else4:
 205 // CHECK-NEXT:    ret ptr @ftc_inline1
 206 // CHECK-LABEL: @ftc_inline2.resolver(
 207 // CHECK-NEXT:  resolver_entry:
 208 // CHECK-NEXT:    call void @init_cpu_features_resolver()
 209 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 210 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 549757911040
 211 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 549757911040
 212 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 213 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 214 // CHECK:       resolver_return:
 215 // CHECK-NEXT:    ret ptr @ftc_inline2._MfcmaMsve2-bitperm
 216 // CHECK:       resolver_else:
 217 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 218 // CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 65536
 219 // CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 65536
 220 // CHECK-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
 221 // CHECK-NEXT:    br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 222 // CHECK:       resolver_return1:
 223 // CHECK-NEXT:    ret ptr @ftc_inline2._Mfp16
 224 // CHECK:       resolver_else2:
 225 // CHECK-NEXT:    ret ptr @ftc_inline2
 226 // CHECK-LABEL: @ftc_inline3.resolver(
 227 // CHECK-NEXT:  resolver_entry:
 228 // CHECK-NEXT:    call void @init_cpu_features_resolver()
 229 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 230 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 70369817919488
 231 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 70369817919488
 232 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 233 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 234 // CHECK:       resolver_return:
 235 // CHECK-NEXT:    ret ptr @ftc_inline3._MsbMsve
 236 // CHECK:       resolver_else:
 237 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 238 // CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 1125899906842624
 239 // CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 1125899906842624
 240 // CHECK-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
 241 // CHECK-NEXT:    br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 242 // CHECK:       resolver_return1:
 243 // CHECK-NEXT:    ret ptr @ftc_inline3._Mbti
 244 // CHECK:       resolver_else2:
 245 // CHECK-NEXT:    ret ptr @ftc_inline3
 246 // CHECK: Function Attrs: noinline nounwind optnone
 247 // CHECK-LABEL: @ftc_inline1._MrngMsimd(
 248 // CHECK-NEXT:  entry:
 249 // CHECK-NEXT:    ret i32 1
 250 // CHECK: Function Attrs: noinline nounwind optnone
 251 // CHECK-LABEL: @ftc_inline1._MpredresMrcpc(
 252 // CHECK-NEXT:  entry:
 253 // CHECK-NEXT:    ret i32 1
 254 // CHECK: Function Attrs: noinline nounwind optnone
 255 // CHECK-LABEL: @ftc_inline1._Msve2-aesMwfxt(
 256 // CHECK-NEXT:  entry:
 257 // CHECK-NEXT:    ret i32 1
 258 // CHECK: Function Attrs: noinline nounwind optnone
 259 // CHECK-LABEL: @ftc_inline1(
 260 // CHECK-NEXT:  entry:
 261 // CHECK-NEXT:    ret i32 1
 262 // CHECK: Function Attrs: noinline nounwind optnone
 263 // CHECK-LABEL: @ftc_inline2._Mfp16(
 264 // CHECK-NEXT:  entry:
 265 // CHECK-NEXT:    ret i32 2
 266 // CHECK: Function Attrs: noinline nounwind optnone
 267 // CHECK-LABEL: @ftc_inline2._MfcmaMsve2-bitperm(
 268 // CHECK-NEXT:  entry:
 269 // CHECK-NEXT:    ret i32 2
 270 // CHECK: Function Attrs: noinline nounwind optnone
 271 // CHECK-LABEL: @ftc_inline2(
 272 // CHECK-NEXT:  entry:
 273 // CHECK-NEXT:    ret i32 2
 274 // CHECK: Function Attrs: noinline nounwind optnone
 275 // CHECK-LABEL: @ftc_inline3._Mbti(
 276 // CHECK-NEXT:  entry:
 277 // CHECK-NEXT:    ret i32 3
 278 // CHECK: Function Attrs: noinline nounwind optnone
 279 // CHECK-LABEL: @ftc_inline3._MsbMsve(
 280 // CHECK-NEXT:  entry:
 281 // CHECK-NEXT:    ret i32 3
 282 // CHECK: Function Attrs: noinline nounwind optnone
 283 // CHECK-LABEL: @ftc_inline3(
 284 // CHECK-NEXT:  entry:
 285 // CHECK-NEXT:    ret i32 3
 286 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
 287 // CHECK-NOFMV-LABEL: @ftc(
 288 // CHECK-NOFMV-NEXT:  entry:
 289 // CHECK-NOFMV-NEXT:    ret i32 0
 290 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
 291 // CHECK-NOFMV-LABEL: @ftc_def(
 292 // CHECK-NOFMV-NEXT:  entry:
 293 // CHECK-NOFMV-NEXT:    ret i32 1
 294 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
 295 // CHECK-NOFMV-LABEL: @ftc_dup1(
 296 // CHECK-NOFMV-NEXT:  entry:
 297 // CHECK-NOFMV-NEXT:    ret i32 2
 298 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
 299 // CHECK-NOFMV-LABEL: @ftc_dup2(
 300 // CHECK-NOFMV-NEXT:  entry:
 301 // CHECK-NOFMV-NEXT:    ret i32 3
 302 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
 303 // CHECK-NOFMV-LABEL: @foo(
 304 // CHECK-NOFMV-NEXT:  entry:
 305 // CHECK-NOFMV-NEXT:    [[CALL:%.*]] = call i32 @ftc()
 306 // CHECK-NOFMV-NEXT:    [[CALL1:%.*]] = call i32 @ftc_def()
 307 // CHECK-NOFMV-NEXT:    [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]
 308 // CHECK-NOFMV-NEXT:    [[CALL2:%.*]] = call i32 @ftc_dup1()
 309 // CHECK-NOFMV-NEXT:    [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]]
 310 // CHECK-NOFMV-NEXT:    [[CALL4:%.*]] = call i32 @ftc_dup2()
 311 // CHECK-NOFMV-NEXT:    [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]]
 312 // CHECK-NOFMV-NEXT:    ret i32 [[ADD5]]
 313 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
 314 // CHECK-NOFMV-LABEL: @ftc_direct(
 315 // CHECK-NOFMV-NEXT:  entry:
 316 // CHECK-NOFMV-NEXT:    ret i32 4
 317 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
 318 // CHECK-NOFMV-LABEL: @main(
 319 // CHECK-NOFMV-NEXT:  entry:
 320 // CHECK-NOFMV-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 321 // CHECK-NOFMV-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 322 // CHECK-NOFMV-NEXT:    [[CALL:%.*]] = call i32 @ftc_inline1()
 323 // CHECK-NOFMV-NEXT:    [[CALL1:%.*]] = call i32 @ftc_inline2()
 324 // CHECK-NOFMV-NEXT:    [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]
 325 // CHECK-NOFMV-NEXT:    [[CALL2:%.*]] = call i32 @ftc_inline3()
 326 // CHECK-NOFMV-NEXT:    [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]]
 327 // CHECK-NOFMV-NEXT:    [[CALL4:%.*]] = call i32 @ftc_direct()
 328 // CHECK-NOFMV-NEXT:    [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]]
 329 // CHECK-NOFMV-NEXT:    ret i32 [[ADD5]]
 330
 331 // CHECK: attributes #0 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+lse,+neon" }
 332 // CHECK: attributes #1 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+sve2" }
 333 // CHECK: attributes #2 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
 334 // CHECK: attributes #3 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+sha2" }
 335 // CHECK: attributes #4 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+mte,+neon,+sha2" }
 336 // CHECK: attributes #5 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon" }
 337 // CHECK: attributes #6 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+dotprod,+fp-armv8,+neon" }
 338 // CHECK: attributes #7 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+rand" }
 339 // CHECK: attributes #8 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+predres,+rcpc" }
 340 // CHECK: attributes #9 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-aes,+wfxt" }
 341 // CHECK: attributes #10 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon" }
 342 // CHECK: attributes #11 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+complxnum,+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-bitperm" }
 343 // CHECK: attributes #12 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti" }
 344 // CHECK: attributes #13 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sb,+sve" }
 345
 346 // CHECK-NOFMV: attributes #0 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv" }
 347 // CHECK-NOFMV: attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv" }