bolt/lib/Core/Relocation.cpp

   1 //===- bolt/Core/Relocation.cpp - Object file relocations -----------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements the Relocation class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "bolt/Core/Relocation.h"
  14 #include "llvm/MC/MCContext.h"
  15 #include "llvm/MC/MCExpr.h"
  16 #include "llvm/MC/MCStreamer.h"
  17 #include "llvm/MC/MCSymbol.h"
  18 #include "llvm/Object/ELF.h"
  19
  20 using namespace llvm;
  21 using namespace bolt;
  22
  23 namespace ELFReserved {
  24 enum {
  25   R_RISCV_TPREL_I = 49,
  26   R_RISCV_TPREL_S = 50,
  27 };
  28 } // namespace ELFReserved
  29
  30 Triple::ArchType Relocation::Arch;
  31
  32 static bool isSupportedX86(uint64_t Type) {
  33   switch (Type) {
  34   default:
  35     return false;
  36   case ELF::R_X86_64_8:
  37   case ELF::R_X86_64_16:
  38   case ELF::R_X86_64_32:
  39   case ELF::R_X86_64_32S:
  40   case ELF::R_X86_64_64:
  41   case ELF::R_X86_64_PC8:
  42   case ELF::R_X86_64_PC32:
  43   case ELF::R_X86_64_PC64:
  44   case ELF::R_X86_64_PLT32:
  45   case ELF::R_X86_64_GOTPC64:
  46   case ELF::R_X86_64_GOTPCREL:
  47   case ELF::R_X86_64_GOTTPOFF:
  48   case ELF::R_X86_64_TPOFF32:
  49   case ELF::R_X86_64_GOTPCRELX:
  50   case ELF::R_X86_64_REX_GOTPCRELX:
  51     return true;
  52   }
  53 }
  54
  55 static bool isSupportedAArch64(uint64_t Type) {
  56   switch (Type) {
  57   default:
  58     return false;
  59   case ELF::R_AARCH64_CALL26:
  60   case ELF::R_AARCH64_JUMP26:
  61   case ELF::R_AARCH64_TSTBR14:
  62   case ELF::R_AARCH64_CONDBR19:
  63   case ELF::R_AARCH64_ADR_PREL_LO21:
  64   case ELF::R_AARCH64_ADR_PREL_PG_HI21:
  65   case ELF::R_AARCH64_ADR_PREL_PG_HI21_NC:
  66   case ELF::R_AARCH64_LDST64_ABS_LO12_NC:
  67   case ELF::R_AARCH64_ADD_ABS_LO12_NC:
  68   case ELF::R_AARCH64_LDST128_ABS_LO12_NC:
  69   case ELF::R_AARCH64_LDST32_ABS_LO12_NC:
  70   case ELF::R_AARCH64_LDST16_ABS_LO12_NC:
  71   case ELF::R_AARCH64_LDST8_ABS_LO12_NC:
  72   case ELF::R_AARCH64_ADR_GOT_PAGE:
  73   case ELF::R_AARCH64_TLSDESC_ADR_PREL21:
  74   case ELF::R_AARCH64_TLSDESC_ADR_PAGE21:
  75   case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
  76   case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12:
  77   case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
  78   case ELF::R_AARCH64_LD64_GOT_LO12_NC:
  79   case ELF::R_AARCH64_TLSDESC_LD64_LO12:
  80   case ELF::R_AARCH64_TLSDESC_ADD_LO12:
  81   case ELF::R_AARCH64_TLSDESC_CALL:
  82   case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
  83   case ELF::R_AARCH64_PREL16:
  84   case ELF::R_AARCH64_PREL32:
  85   case ELF::R_AARCH64_PREL64:
  86   case ELF::R_AARCH64_ABS16:
  87   case ELF::R_AARCH64_ABS32:
  88   case ELF::R_AARCH64_ABS64:
  89   case ELF::R_AARCH64_MOVW_UABS_G0:
  90   case ELF::R_AARCH64_MOVW_UABS_G0_NC:
  91   case ELF::R_AARCH64_MOVW_UABS_G1:
  92   case ELF::R_AARCH64_MOVW_UABS_G1_NC:
  93   case ELF::R_AARCH64_MOVW_UABS_G2:
  94   case ELF::R_AARCH64_MOVW_UABS_G2_NC:
  95   case ELF::R_AARCH64_MOVW_UABS_G3:
  96     return true;
  97   }
  98 }
  99
 100 static bool isSupportedRISCV(uint64_t Type) {
 101   switch (Type) {
 102   default:
 103     return false;
 104   case ELF::R_RISCV_JAL:
 105   case ELF::R_RISCV_CALL:
 106   case ELF::R_RISCV_CALL_PLT:
 107   case ELF::R_RISCV_BRANCH:
 108   case ELF::R_RISCV_RELAX:
 109   case ELF::R_RISCV_GOT_HI20:
 110   case ELF::R_RISCV_PCREL_HI20:
 111   case ELF::R_RISCV_PCREL_LO12_I:
 112   case ELF::R_RISCV_PCREL_LO12_S:
 113   case ELF::R_RISCV_RVC_JUMP:
 114   case ELF::R_RISCV_RVC_BRANCH:
 115   case ELF::R_RISCV_ADD32:
 116   case ELF::R_RISCV_SUB32:
 117   case ELF::R_RISCV_HI20:
 118   case ELF::R_RISCV_LO12_I:
 119   case ELF::R_RISCV_LO12_S:
 120   case ELF::R_RISCV_64:
 121   case ELF::R_RISCV_TLS_GOT_HI20:
 122   case ELF::R_RISCV_TPREL_HI20:
 123   case ELF::R_RISCV_TPREL_ADD:
 124   case ELF::R_RISCV_TPREL_LO12_I:
 125   case ELF::R_RISCV_TPREL_LO12_S:
 126   case ELFReserved::R_RISCV_TPREL_I:
 127   case ELFReserved::R_RISCV_TPREL_S:
 128     return true;
 129   }
 130 }
 131
 132 static size_t getSizeForTypeX86(uint64_t Type) {
 133   switch (Type) {
 134   default:
 135     errs() << object::getELFRelocationTypeName(ELF::EM_X86_64, Type) << '\n';
 136     llvm_unreachable("unsupported relocation type");
 137   case ELF::R_X86_64_8:
 138   case ELF::R_X86_64_PC8:
 139     return 1;
 140   case ELF::R_X86_64_16:
 141     return 2;
 142   case ELF::R_X86_64_PLT32:
 143   case ELF::R_X86_64_PC32:
 144   case ELF::R_X86_64_32S:
 145   case ELF::R_X86_64_32:
 146   case ELF::R_X86_64_GOTPCREL:
 147   case ELF::R_X86_64_GOTTPOFF:
 148   case ELF::R_X86_64_TPOFF32:
 149   case ELF::R_X86_64_GOTPCRELX:
 150   case ELF::R_X86_64_REX_GOTPCRELX:
 151     return 4;
 152   case ELF::R_X86_64_PC64:
 153   case ELF::R_X86_64_64:
 154   case ELF::R_X86_64_GOTPC64:
 155     return 8;
 156   }
 157 }
 158
 159 static size_t getSizeForTypeAArch64(uint64_t Type) {
 160   switch (Type) {
 161   default:
 162     errs() << object::getELFRelocationTypeName(ELF::EM_AARCH64, Type) << '\n';
 163     llvm_unreachable("unsupported relocation type");
 164   case ELF::R_AARCH64_ABS16:
 165   case ELF::R_AARCH64_PREL16:
 166     return 2;
 167   case ELF::R_AARCH64_CALL26:
 168   case ELF::R_AARCH64_JUMP26:
 169   case ELF::R_AARCH64_TSTBR14:
 170   case ELF::R_AARCH64_CONDBR19:
 171   case ELF::R_AARCH64_ADR_PREL_LO21:
 172   case ELF::R_AARCH64_ADR_PREL_PG_HI21:
 173   case ELF::R_AARCH64_ADR_PREL_PG_HI21_NC:
 174   case ELF::R_AARCH64_LDST64_ABS_LO12_NC:
 175   case ELF::R_AARCH64_ADD_ABS_LO12_NC:
 176   case ELF::R_AARCH64_LDST128_ABS_LO12_NC:
 177   case ELF::R_AARCH64_LDST32_ABS_LO12_NC:
 178   case ELF::R_AARCH64_LDST16_ABS_LO12_NC:
 179   case ELF::R_AARCH64_LDST8_ABS_LO12_NC:
 180   case ELF::R_AARCH64_ADR_GOT_PAGE:
 181   case ELF::R_AARCH64_TLSDESC_ADR_PREL21:
 182   case ELF::R_AARCH64_TLSDESC_ADR_PAGE21:
 183   case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
 184   case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12:
 185   case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
 186   case ELF::R_AARCH64_LD64_GOT_LO12_NC:
 187   case ELF::R_AARCH64_TLSDESC_LD64_LO12:
 188   case ELF::R_AARCH64_TLSDESC_ADD_LO12:
 189   case ELF::R_AARCH64_TLSDESC_CALL:
 190   case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
 191   case ELF::R_AARCH64_PREL32:
 192   case ELF::R_AARCH64_MOVW_UABS_G0:
 193   case ELF::R_AARCH64_MOVW_UABS_G0_NC:
 194   case ELF::R_AARCH64_MOVW_UABS_G1:
 195   case ELF::R_AARCH64_MOVW_UABS_G1_NC:
 196   case ELF::R_AARCH64_MOVW_UABS_G2:
 197   case ELF::R_AARCH64_MOVW_UABS_G2_NC:
 198   case ELF::R_AARCH64_MOVW_UABS_G3:
 199   case ELF::R_AARCH64_ABS32:
 200     return 4;
 201   case ELF::R_AARCH64_ABS64:
 202   case ELF::R_AARCH64_PREL64:
 203     return 8;
 204   }
 205 }
 206
 207 static size_t getSizeForTypeRISCV(uint64_t Type) {
 208   switch (Type) {
 209   default:
 210     errs() << object::getELFRelocationTypeName(ELF::EM_RISCV, Type) << '\n';
 211     llvm_unreachable("unsupported relocation type");
 212   case ELF::R_RISCV_RVC_JUMP:
 213   case ELF::R_RISCV_RVC_BRANCH:
 214     return 2;
 215   case ELF::R_RISCV_JAL:
 216   case ELF::R_RISCV_BRANCH:
 217   case ELF::R_RISCV_PCREL_HI20:
 218   case ELF::R_RISCV_PCREL_LO12_I:
 219   case ELF::R_RISCV_PCREL_LO12_S:
 220   case ELF::R_RISCV_32_PCREL:
 221   case ELF::R_RISCV_CALL:
 222   case ELF::R_RISCV_CALL_PLT:
 223   case ELF::R_RISCV_ADD32:
 224   case ELF::R_RISCV_SUB32:
 225   case ELF::R_RISCV_HI20:
 226   case ELF::R_RISCV_LO12_I:
 227   case ELF::R_RISCV_LO12_S:
 228     return 4;
 229   case ELF::R_RISCV_64:
 230   case ELF::R_RISCV_GOT_HI20:
 231   case ELF::R_RISCV_TLS_GOT_HI20:
 232     // See extractValueRISCV for why this is necessary.
 233     return 8;
 234   }
 235 }
 236
 237 static bool skipRelocationTypeX86(uint64_t Type) {
 238   return Type == ELF::R_X86_64_NONE;
 239 }
 240
 241 static bool skipRelocationTypeAArch64(uint64_t Type) {
 242   return Type == ELF::R_AARCH64_NONE || Type == ELF::R_AARCH64_LD_PREL_LO19;
 243 }
 244
 245 static bool skipRelocationTypeRISCV(uint64_t Type) {
 246   switch (Type) {
 247   default:
 248     return false;
 249   case ELF::R_RISCV_NONE:
 250   case ELF::R_RISCV_RELAX:
 251     return true;
 252   }
 253 }
 254
 255 static bool skipRelocationProcessX86(uint64_t &Type, uint64_t Contents) {
 256   return false;
 257 }
 258
 259 static bool skipRelocationProcessAArch64(uint64_t &Type, uint64_t Contents) {
 260   auto IsMov = [](uint64_t Contents) -> bool {
 261     // The bits 28-23 are 0b100101
 262     return (Contents & 0x1f800000) == 0x12800000;
 263   };
 264
 265   auto IsB = [](uint64_t Contents) -> bool {
 266     // The bits 31-26 are 0b000101
 267     return (Contents & 0xfc000000) == 0x14000000;
 268   };
 269
 270   auto IsAdr = [](uint64_t Contents) -> bool {
 271     // The bits 31-24 are 0b0xx10000
 272     return (Contents & 0x9f000000) == 0x10000000;
 273   };
 274
 275   auto IsAddImm = [](uint64_t Contents) -> bool {
 276     // The bits 30-23 are 0b00100010
 277     return (Contents & 0x7F800000) == 0x11000000;
 278   };
 279
 280   auto IsNop = [](uint64_t Contents) -> bool { return Contents == 0xd503201f; };
 281
 282   // The linker might eliminate the instruction and replace it with NOP, ignore
 283   if (IsNop(Contents))
 284     return true;
 285
 286   // The linker might relax ADRP+LDR instruction sequence for loading symbol
 287   // address from GOT table to ADRP+ADD sequence that would point to the
 288   // binary-local symbol. Change relocation type in order to process it right.
 289   if (Type == ELF::R_AARCH64_LD64_GOT_LO12_NC && IsAddImm(Contents)) {
 290     Type = ELF::R_AARCH64_ADD_ABS_LO12_NC;
 291     return false;
 292   }
 293
 294   // The linker might perform TLS relocations relaxations, such as
 295   // changed TLS access model (e.g. changed global dynamic model
 296   // to initial exec), thus changing the instructions. The static
 297   // relocations might be invalid at this point and we might no
 298   // need to process these relocations anymore.
 299   // More information could be found by searching
 300   // elfNN_aarch64_tls_relax in bfd
 301   switch (Type) {
 302   default:
 303     break;
 304   case ELF::R_AARCH64_TLSDESC_LD64_LO12:
 305   case ELF::R_AARCH64_TLSDESC_ADR_PAGE21:
 306   case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
 307   case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: {
 308     if (IsMov(Contents))
 309       return true;
 310   }
 311   }
 312
 313   // The linker might replace load/store instruction with jump and
 314   // veneer due to errata 843419
 315   // https://documentation-service.arm.com/static/5fa29fddb209f547eebd361d
 316   // Thus load/store relocations for these instructions must be ignored
 317   // NOTE: We only process GOT and TLS relocations this way since the
 318   // addend used in load/store instructions won't change after bolt
 319   // (it is important since the instruction in veneer won't have relocation)
 320   switch (Type) {
 321   default:
 322     break;
 323   case ELF::R_AARCH64_LD64_GOT_LO12_NC:
 324   case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
 325   case ELF::R_AARCH64_TLSDESC_LD64_LO12: {
 326     if (IsB(Contents))
 327       return true;
 328   }
 329   }
 330
 331   // The linker might relax ADRP+ADD or ADRP+LDR sequences to the ADR+NOP
 332   switch (Type) {
 333   default:
 334     break;
 335   case ELF::R_AARCH64_ADR_PREL_PG_HI21:
 336   case ELF::R_AARCH64_ADD_ABS_LO12_NC:
 337   case ELF::R_AARCH64_ADR_GOT_PAGE:
 338   case ELF::R_AARCH64_LD64_GOT_LO12_NC:
 339     if (IsAdr(Contents))
 340       return true;
 341   }
 342
 343   return false;
 344 }
 345
 346 static bool skipRelocationProcessRISCV(uint64_t &Type, uint64_t Contents) {
 347   return false;
 348 }
 349
 350 static uint64_t encodeValueX86(uint64_t Type, uint64_t Value, uint64_t PC) {
 351   switch (Type) {
 352   default:
 353     llvm_unreachable("unsupported relocation");
 354   case ELF::R_X86_64_64:
 355   case ELF::R_X86_64_32:
 356     break;
 357   case ELF::R_X86_64_PC32:
 358     Value -= PC;
 359     break;
 360   }
 361   return Value;
 362 }
 363
 364 static uint64_t encodeValueAArch64(uint64_t Type, uint64_t Value, uint64_t PC) {
 365   switch (Type) {
 366   default:
 367     llvm_unreachable("unsupported relocation");
 368   case ELF::R_AARCH64_ABS16:
 369   case ELF::R_AARCH64_ABS32:
 370   case ELF::R_AARCH64_ABS64:
 371     break;
 372   case ELF::R_AARCH64_PREL16:
 373   case ELF::R_AARCH64_PREL32:
 374   case ELF::R_AARCH64_PREL64:
 375     Value -= PC;
 376     break;
 377   case ELF::R_AARCH64_CALL26:
 378     Value -= PC;
 379     assert(isInt<28>(Value) && "only PC +/- 128MB is allowed for direct call");
 380     // Immediate goes in bits 25:0 of BL.
 381     // OP 1001_01 goes in bits 31:26 of BL.
 382     Value = ((Value >> 2) & 0x3ffffff) | 0x94000000ULL;
 383     break;
 384   case ELF::R_AARCH64_JUMP26:
 385     Value -= PC;
 386     assert(isInt<28>(Value) &&
 387            "only PC +/- 128MB is allowed for direct branch");
 388     // Immediate goes in bits 25:0 of B.
 389     // OP 0001_01 goes in bits 31:26 of B.
 390     Value = ((Value >> 2) & 0x3ffffff) | 0x14000000ULL;
 391     break;
 392   }
 393   return Value;
 394 }
 395
 396 static uint64_t encodeValueRISCV(uint64_t Type, uint64_t Value, uint64_t PC) {
 397   switch (Type) {
 398   default:
 399     llvm_unreachable("unsupported relocation");
 400   case ELF::R_RISCV_64:
 401     break;
 402   }
 403   return Value;
 404 }
 405
 406 static uint64_t extractValueX86(uint64_t Type, uint64_t Contents, uint64_t PC) {
 407   if (Type == ELF::R_X86_64_32S)
 408     return SignExtend64<32>(Contents);
 409   if (Relocation::isPCRelative(Type))
 410     return SignExtend64(Contents, 8 * Relocation::getSizeForType(Type));
 411   return Contents;
 412 }
 413
 414 static uint64_t extractValueAArch64(uint64_t Type, uint64_t Contents,
 415                                     uint64_t PC) {
 416   switch (Type) {
 417   default:
 418     errs() << object::getELFRelocationTypeName(ELF::EM_AARCH64, Type) << '\n';
 419     llvm_unreachable("unsupported relocation type");
 420   case ELF::R_AARCH64_ABS16:
 421   case ELF::R_AARCH64_ABS32:
 422   case ELF::R_AARCH64_ABS64:
 423     return Contents;
 424   case ELF::R_AARCH64_PREL16:
 425     return static_cast<int64_t>(PC) + SignExtend64<16>(Contents & 0xffff);
 426   case ELF::R_AARCH64_PREL32:
 427     return static_cast<int64_t>(PC) + SignExtend64<32>(Contents & 0xffffffff);
 428   case ELF::R_AARCH64_PREL64:
 429     return static_cast<int64_t>(PC) + Contents;
 430   case ELF::R_AARCH64_TLSDESC_CALL:
 431   case ELF::R_AARCH64_JUMP26:
 432   case ELF::R_AARCH64_CALL26:
 433     // Immediate goes in bits 25:0 of B and BL.
 434     Contents &= ~0xfffffffffc000000ULL;
 435     return static_cast<int64_t>(PC) + SignExtend64<28>(Contents << 2);
 436   case ELF::R_AARCH64_TSTBR14:
 437     // Immediate:15:2 goes in bits 18:5 of TBZ, TBNZ
 438     Contents &= ~0xfffffffffff8001fULL;
 439     return static_cast<int64_t>(PC) + SignExtend64<16>(Contents >> 3);
 440   case ELF::R_AARCH64_CONDBR19:
 441     // Immediate:20:2 goes in bits 23:5 of Bcc, CBZ, CBNZ
 442     Contents &= ~0xffffffffff00001fULL;
 443     return static_cast<int64_t>(PC) + SignExtend64<21>(Contents >> 3);
 444   case ELF::R_AARCH64_ADR_GOT_PAGE:
 445   case ELF::R_AARCH64_TLSDESC_ADR_PREL21:
 446   case ELF::R_AARCH64_TLSDESC_ADR_PAGE21:
 447   case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
 448   case ELF::R_AARCH64_ADR_PREL_LO21:
 449   case ELF::R_AARCH64_ADR_PREL_PG_HI21:
 450   case ELF::R_AARCH64_ADR_PREL_PG_HI21_NC: {
 451     // Bits 32:12 of Symbol address goes in bits 30:29 + 23:5 of ADRP
 452     // and ADR instructions
 453     bool IsAdr = !!(((Contents >> 31) & 0x1) == 0);
 454     Contents &= ~0xffffffff9f00001fUll;
 455     uint64_t LowBits = (Contents >> 29) & 0x3;
 456     uint64_t HighBits = (Contents >> 5) & 0x7ffff;
 457     Contents = LowBits | (HighBits << 2);
 458     if (IsAdr)
 459       return static_cast<int64_t>(PC) + SignExtend64<21>(Contents);
 460
 461     // ADRP instruction
 462     Contents = static_cast<int64_t>(PC) + SignExtend64<33>(Contents << 12);
 463     Contents &= ~0xfffUll;
 464     return Contents;
 465   }
 466   case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
 467   case ELF::R_AARCH64_TLSDESC_LD64_LO12:
 468   case ELF::R_AARCH64_LD64_GOT_LO12_NC:
 469   case ELF::R_AARCH64_LDST64_ABS_LO12_NC: {
 470     // Immediate goes in bits 21:10 of LD/ST instruction, taken
 471     // from bits 11:3 of Symbol address
 472     Contents &= ~0xffffffffffc003ffU;
 473     return Contents >> (10 - 3);
 474   }
 475   case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12:
 476   case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
 477   case ELF::R_AARCH64_TLSDESC_ADD_LO12:
 478   case ELF::R_AARCH64_ADD_ABS_LO12_NC: {
 479     // Immediate goes in bits 21:10 of ADD instruction
 480     Contents &= ~0xffffffffffc003ffU;
 481     return Contents >> (10 - 0);
 482   }
 483   case ELF::R_AARCH64_LDST128_ABS_LO12_NC: {
 484     // Immediate goes in bits 21:10 of ADD instruction, taken
 485     // from bits 11:4 of Symbol address
 486     Contents &= ~0xffffffffffc003ffU;
 487     return Contents >> (10 - 4);
 488   }
 489   case ELF::R_AARCH64_LDST32_ABS_LO12_NC: {
 490     // Immediate goes in bits 21:10 of ADD instruction, taken
 491     // from bits 11:2 of Symbol address
 492     Contents &= ~0xffffffffffc003ffU;
 493     return Contents >> (10 - 2);
 494   }
 495   case ELF::R_AARCH64_LDST16_ABS_LO12_NC: {
 496     // Immediate goes in bits 21:10 of ADD instruction, taken
 497     // from bits 11:1 of Symbol address
 498     Contents &= ~0xffffffffffc003ffU;
 499     return Contents >> (10 - 1);
 500   }
 501   case ELF::R_AARCH64_LDST8_ABS_LO12_NC: {
 502     // Immediate goes in bits 21:10 of ADD instruction, taken
 503     // from bits 11:0 of Symbol address
 504     Contents &= ~0xffffffffffc003ffU;
 505     return Contents >> (10 - 0);
 506   }
 507   case ELF::R_AARCH64_MOVW_UABS_G3:
 508   case ELF::R_AARCH64_MOVW_UABS_G2_NC:
 509   case ELF::R_AARCH64_MOVW_UABS_G2:
 510   case ELF::R_AARCH64_MOVW_UABS_G1_NC:
 511   case ELF::R_AARCH64_MOVW_UABS_G1:
 512   case ELF::R_AARCH64_MOVW_UABS_G0_NC:
 513   case ELF::R_AARCH64_MOVW_UABS_G0:
 514     // The shift goes in bits 22:21 of MOV* instructions
 515     uint8_t Shift = (Contents >> 21) & 0x3;
 516     // Immediate goes in bits 20:5
 517     Contents = (Contents >> 5) & 0xffff;
 518     return Contents << (16 * Shift);
 519   }
 520 }
 521
 522 static uint64_t extractUImmRISCV(uint32_t Contents) {
 523   return SignExtend64<32>(Contents & 0xfffff000);
 524 }
 525
 526 static uint64_t extractIImmRISCV(uint32_t Contents) {
 527   return SignExtend64<12>(Contents >> 20);
 528 }
 529
 530 static uint64_t extractSImmRISCV(uint32_t Contents) {
 531   return SignExtend64<12>(((Contents >> 7) & 0x1f) | ((Contents >> 25) << 5));
 532 }
 533
 534 static uint64_t extractJImmRISCV(uint32_t Contents) {
 535   return SignExtend64<21>(
 536       (((Contents >> 21) & 0x3ff) << 1) | (((Contents >> 20) & 0x1) << 11) |
 537       (((Contents >> 12) & 0xff) << 12) | (((Contents >> 31) & 0x1) << 20));
 538 }
 539
 540 static uint64_t extractBImmRISCV(uint32_t Contents) {
 541   return SignExtend64<13>(
 542       (((Contents >> 8) & 0xf) << 1) | (((Contents >> 25) & 0x3f) << 5) |
 543       (((Contents >> 7) & 0x1) << 11) | (((Contents >> 31) & 0x1) << 12));
 544 }
 545
 546 static uint64_t extractValueRISCV(uint64_t Type, uint64_t Contents,
 547                                   uint64_t PC) {
 548   switch (Type) {
 549   default:
 550     errs() << object::getELFRelocationTypeName(ELF::EM_RISCV, Type) << '\n';
 551     llvm_unreachable("unsupported relocation type");
 552   case ELF::R_RISCV_JAL:
 553     return extractJImmRISCV(Contents);
 554   case ELF::R_RISCV_CALL:
 555   case ELF::R_RISCV_CALL_PLT:
 556     return extractUImmRISCV(Contents);
 557   case ELF::R_RISCV_BRANCH:
 558     return extractBImmRISCV(Contents);
 559   case ELF::R_RISCV_GOT_HI20:
 560   case ELF::R_RISCV_TLS_GOT_HI20:
 561     // We need to know the exact address of the GOT entry so we extract the
 562     // value from both the AUIPC and L[D|W]. We cannot rely on the symbol in the
 563     // relocation for this since it simply refers to the object that is stored
 564     // in the GOT entry, not to the entry itself.
 565     return extractUImmRISCV(Contents & 0xffffffff) +
 566            extractIImmRISCV(Contents >> 32);
 567   case ELF::R_RISCV_PCREL_HI20:
 568   case ELF::R_RISCV_HI20:
 569     return extractUImmRISCV(Contents);
 570   case ELF::R_RISCV_PCREL_LO12_I:
 571   case ELF::R_RISCV_LO12_I:
 572     return extractIImmRISCV(Contents);
 573   case ELF::R_RISCV_PCREL_LO12_S:
 574   case ELF::R_RISCV_LO12_S:
 575     return extractSImmRISCV(Contents);
 576   case ELF::R_RISCV_RVC_JUMP:
 577     return SignExtend64<11>(Contents >> 2);
 578   case ELF::R_RISCV_RVC_BRANCH:
 579     return SignExtend64<8>(((Contents >> 2) & 0x1f) | ((Contents >> 5) & 0xe0));
 580   case ELF::R_RISCV_ADD32:
 581   case ELF::R_RISCV_SUB32:
 582   case ELF::R_RISCV_64:
 583     return Contents;
 584   }
 585 }
 586
 587 static bool isGOTX86(uint64_t Type) {
 588   switch (Type) {
 589   default:
 590     return false;
 591   case ELF::R_X86_64_GOT32:
 592   case ELF::R_X86_64_GOTPCREL:
 593   case ELF::R_X86_64_GOTTPOFF:
 594   case ELF::R_X86_64_GOTOFF64:
 595   case ELF::R_X86_64_GOTPC32:
 596   case ELF::R_X86_64_GOT64:
 597   case ELF::R_X86_64_GOTPCREL64:
 598   case ELF::R_X86_64_GOTPC64:
 599   case ELF::R_X86_64_GOTPLT64:
 600   case ELF::R_X86_64_GOTPC32_TLSDESC:
 601   case ELF::R_X86_64_GOTPCRELX:
 602   case ELF::R_X86_64_REX_GOTPCRELX:
 603     return true;
 604   }
 605 }
 606
 607 static bool isGOTAArch64(uint64_t Type) {
 608   switch (Type) {
 609   default:
 610     return false;
 611   case ELF::R_AARCH64_ADR_GOT_PAGE:
 612   case ELF::R_AARCH64_LD64_GOT_LO12_NC:
 613   case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
 614   case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
 615   case ELF::R_AARCH64_TLSDESC_ADR_PREL21:
 616   case ELF::R_AARCH64_TLSDESC_ADR_PAGE21:
 617   case ELF::R_AARCH64_TLSDESC_LD64_LO12:
 618   case ELF::R_AARCH64_TLSDESC_ADD_LO12:
 619   case ELF::R_AARCH64_TLSDESC_CALL:
 620     return true;
 621   }
 622 }
 623
 624 static bool isGOTRISCV(uint64_t Type) {
 625   switch (Type) {
 626   default:
 627     return false;
 628   case ELF::R_RISCV_GOT_HI20:
 629   case ELF::R_RISCV_TLS_GOT_HI20:
 630     return true;
 631   }
 632 }
 633
 634 static bool isTLSX86(uint64_t Type) {
 635   switch (Type) {
 636   default:
 637     return false;
 638   case ELF::R_X86_64_TPOFF32:
 639   case ELF::R_X86_64_TPOFF64:
 640   case ELF::R_X86_64_GOTTPOFF:
 641     return true;
 642   }
 643 }
 644
 645 static bool isTLSAArch64(uint64_t Type) {
 646   switch (Type) {
 647   default:
 648     return false;
 649   case ELF::R_AARCH64_TLSDESC_ADR_PREL21:
 650   case ELF::R_AARCH64_TLSDESC_ADR_PAGE21:
 651   case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
 652   case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12:
 653   case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
 654   case ELF::R_AARCH64_TLSDESC_LD64_LO12:
 655   case ELF::R_AARCH64_TLSDESC_ADD_LO12:
 656   case ELF::R_AARCH64_TLSDESC_CALL:
 657   case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
 658     return true;
 659   }
 660 }
 661
 662 static bool isTLSRISCV(uint64_t Type) {
 663   switch (Type) {
 664   default:
 665     return false;
 666   case ELF::R_RISCV_TLS_GOT_HI20:
 667   case ELF::R_RISCV_TPREL_HI20:
 668   case ELF::R_RISCV_TPREL_ADD:
 669   case ELF::R_RISCV_TPREL_LO12_I:
 670   case ELF::R_RISCV_TPREL_LO12_S:
 671   case ELFReserved::R_RISCV_TPREL_I:
 672   case ELFReserved::R_RISCV_TPREL_S:
 673     return true;
 674   }
 675 }
 676
 677 static bool isPCRelativeX86(uint64_t Type) {
 678   switch (Type) {
 679   default:
 680     llvm_unreachable("Unknown relocation type");
 681   case ELF::R_X86_64_64:
 682   case ELF::R_X86_64_32:
 683   case ELF::R_X86_64_32S:
 684   case ELF::R_X86_64_16:
 685   case ELF::R_X86_64_8:
 686   case ELF::R_X86_64_TPOFF32:
 687     return false;
 688   case ELF::R_X86_64_PC8:
 689   case ELF::R_X86_64_PC32:
 690   case ELF::R_X86_64_PC64:
 691   case ELF::R_X86_64_GOTPCREL:
 692   case ELF::R_X86_64_PLT32:
 693   case ELF::R_X86_64_GOTOFF64:
 694   case ELF::R_X86_64_GOTPC32:
 695   case ELF::R_X86_64_GOTPC64:
 696   case ELF::R_X86_64_GOTTPOFF:
 697   case ELF::R_X86_64_GOTPCRELX:
 698   case ELF::R_X86_64_REX_GOTPCRELX:
 699     return true;
 700   }
 701 }
 702
 703 static bool isPCRelativeAArch64(uint64_t Type) {
 704   switch (Type) {
 705   default:
 706     llvm_unreachable("Unknown relocation type");
 707   case ELF::R_AARCH64_ABS16:
 708   case ELF::R_AARCH64_ABS32:
 709   case ELF::R_AARCH64_ABS64:
 710   case ELF::R_AARCH64_LDST64_ABS_LO12_NC:
 711   case ELF::R_AARCH64_ADD_ABS_LO12_NC:
 712   case ELF::R_AARCH64_LDST128_ABS_LO12_NC:
 713   case ELF::R_AARCH64_LDST32_ABS_LO12_NC:
 714   case ELF::R_AARCH64_LDST16_ABS_LO12_NC:
 715   case ELF::R_AARCH64_LDST8_ABS_LO12_NC:
 716   case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
 717   case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12:
 718   case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
 719   case ELF::R_AARCH64_LD64_GOT_LO12_NC:
 720   case ELF::R_AARCH64_TLSDESC_LD64_LO12:
 721   case ELF::R_AARCH64_TLSDESC_ADD_LO12:
 722   case ELF::R_AARCH64_MOVW_UABS_G0:
 723   case ELF::R_AARCH64_MOVW_UABS_G0_NC:
 724   case ELF::R_AARCH64_MOVW_UABS_G1:
 725   case ELF::R_AARCH64_MOVW_UABS_G1_NC:
 726   case ELF::R_AARCH64_MOVW_UABS_G2:
 727   case ELF::R_AARCH64_MOVW_UABS_G2_NC:
 728   case ELF::R_AARCH64_MOVW_UABS_G3:
 729     return false;
 730   case ELF::R_AARCH64_TLSDESC_CALL:
 731   case ELF::R_AARCH64_CALL26:
 732   case ELF::R_AARCH64_JUMP26:
 733   case ELF::R_AARCH64_TSTBR14:
 734   case ELF::R_AARCH64_CONDBR19:
 735   case ELF::R_AARCH64_ADR_PREL_LO21:
 736   case ELF::R_AARCH64_ADR_PREL_PG_HI21:
 737   case ELF::R_AARCH64_ADR_PREL_PG_HI21_NC:
 738   case ELF::R_AARCH64_ADR_GOT_PAGE:
 739   case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
 740   case ELF::R_AARCH64_TLSDESC_ADR_PREL21:
 741   case ELF::R_AARCH64_TLSDESC_ADR_PAGE21:
 742   case ELF::R_AARCH64_PREL16:
 743   case ELF::R_AARCH64_PREL32:
 744   case ELF::R_AARCH64_PREL64:
 745     return true;
 746   }
 747 }
 748
 749 static bool isPCRelativeRISCV(uint64_t Type) {
 750   switch (Type) {
 751   default:
 752     llvm_unreachable("Unknown relocation type");
 753   case ELF::R_RISCV_ADD32:
 754   case ELF::R_RISCV_SUB32:
 755   case ELF::R_RISCV_HI20:
 756   case ELF::R_RISCV_LO12_I:
 757   case ELF::R_RISCV_LO12_S:
 758   case ELF::R_RISCV_64:
 759     return false;
 760   case ELF::R_RISCV_JAL:
 761   case ELF::R_RISCV_CALL:
 762   case ELF::R_RISCV_CALL_PLT:
 763   case ELF::R_RISCV_BRANCH:
 764   case ELF::R_RISCV_GOT_HI20:
 765   case ELF::R_RISCV_PCREL_HI20:
 766   case ELF::R_RISCV_PCREL_LO12_I:
 767   case ELF::R_RISCV_PCREL_LO12_S:
 768   case ELF::R_RISCV_RVC_JUMP:
 769   case ELF::R_RISCV_RVC_BRANCH:
 770   case ELF::R_RISCV_32_PCREL:
 771   case ELF::R_RISCV_TLS_GOT_HI20:
 772     return true;
 773   }
 774 }
 775
 776 bool Relocation::isSupported(uint64_t Type) {
 777   switch (Arch) {
 778   default:
 779     return false;
 780   case Triple::aarch64:
 781     return isSupportedAArch64(Type);
 782   case Triple::riscv64:
 783     return isSupportedRISCV(Type);
 784   case Triple::x86_64:
 785     return isSupportedX86(Type);
 786   }
 787 }
 788
 789 size_t Relocation::getSizeForType(uint64_t Type) {
 790   switch (Arch) {
 791   default:
 792     llvm_unreachable("Unsupported architecture");
 793   case Triple::aarch64:
 794     return getSizeForTypeAArch64(Type);
 795   case Triple::riscv64:
 796     return getSizeForTypeRISCV(Type);
 797   case Triple::x86_64:
 798     return getSizeForTypeX86(Type);
 799   }
 800 }
 801
 802 bool Relocation::skipRelocationType(uint64_t Type) {
 803   switch (Arch) {
 804   default:
 805     llvm_unreachable("Unsupported architecture");
 806   case Triple::aarch64:
 807     return skipRelocationTypeAArch64(Type);
 808   case Triple::riscv64:
 809     return skipRelocationTypeRISCV(Type);
 810   case Triple::x86_64:
 811     return skipRelocationTypeX86(Type);
 812   }
 813 }
 814
 815 bool Relocation::skipRelocationProcess(uint64_t &Type, uint64_t Contents) {
 816   switch (Arch) {
 817   default:
 818     llvm_unreachable("Unsupported architecture");
 819   case Triple::aarch64:
 820     return skipRelocationProcessAArch64(Type, Contents);
 821   case Triple::riscv64:
 822     return skipRelocationProcessRISCV(Type, Contents);
 823   case Triple::x86_64:
 824     return skipRelocationProcessX86(Type, Contents);
 825   }
 826 }
 827
 828 uint64_t Relocation::encodeValue(uint64_t Type, uint64_t Value, uint64_t PC) {
 829   switch (Arch) {
 830   default:
 831     llvm_unreachable("Unsupported architecture");
 832   case Triple::aarch64:
 833     return encodeValueAArch64(Type, Value, PC);
 834   case Triple::riscv64:
 835     return encodeValueRISCV(Type, Value, PC);
 836   case Triple::x86_64:
 837     return encodeValueX86(Type, Value, PC);
 838   }
 839 }
 840
 841 uint64_t Relocation::extractValue(uint64_t Type, uint64_t Contents,
 842                                   uint64_t PC) {
 843   switch (Arch) {
 844   default:
 845     llvm_unreachable("Unsupported architecture");
 846   case Triple::aarch64:
 847     return extractValueAArch64(Type, Contents, PC);
 848   case Triple::riscv64:
 849     return extractValueRISCV(Type, Contents, PC);
 850   case Triple::x86_64:
 851     return extractValueX86(Type, Contents, PC);
 852   }
 853 }
 854
 855 bool Relocation::isGOT(uint64_t Type) {
 856   switch (Arch) {
 857   default:
 858     llvm_unreachable("Unsupported architecture");
 859   case Triple::aarch64:
 860     return isGOTAArch64(Type);
 861   case Triple::riscv64:
 862     return isGOTRISCV(Type);
 863   case Triple::x86_64:
 864     return isGOTX86(Type);
 865   }
 866 }
 867
 868 bool Relocation::isX86GOTPCRELX(uint64_t Type) {
 869   if (Arch != Triple::x86_64)
 870     return false;
 871   return Type == ELF::R_X86_64_GOTPCRELX || Type == ELF::R_X86_64_REX_GOTPCRELX;
 872 }
 873
 874 bool Relocation::isX86GOTPC64(uint64_t Type) {
 875   if (Arch != Triple::x86_64)
 876     return false;
 877   return Type == ELF::R_X86_64_GOTPC64;
 878 }
 879
 880 bool Relocation::isNone(uint64_t Type) { return Type == getNone(); }
 881
 882 bool Relocation::isRelative(uint64_t Type) {
 883   switch (Arch) {
 884   default:
 885     llvm_unreachable("Unsupported architecture");
 886   case Triple::aarch64:
 887     return Type == ELF::R_AARCH64_RELATIVE;
 888   case Triple::riscv64:
 889     return Type == ELF::R_RISCV_RELATIVE;
 890   case Triple::x86_64:
 891     return Type == ELF::R_X86_64_RELATIVE;
 892   }
 893 }
 894
 895 bool Relocation::isIRelative(uint64_t Type) {
 896   switch (Arch) {
 897   default:
 898     llvm_unreachable("Unsupported architecture");
 899   case Triple::aarch64:
 900     return Type == ELF::R_AARCH64_IRELATIVE;
 901   case Triple::riscv64:
 902     llvm_unreachable("not implemented");
 903   case Triple::x86_64:
 904     return Type == ELF::R_X86_64_IRELATIVE;
 905   }
 906 }
 907
 908 bool Relocation::isTLS(uint64_t Type) {
 909   switch (Arch) {
 910   default:
 911     llvm_unreachable("Unsupported architecture");
 912   case Triple::aarch64:
 913     return isTLSAArch64(Type);
 914   case Triple::riscv64:
 915     return isTLSRISCV(Type);
 916   case Triple::x86_64:
 917     return isTLSX86(Type);
 918   }
 919 }
 920
 921 bool Relocation::isInstructionReference(uint64_t Type) {
 922   if (Arch != Triple::riscv64)
 923     return false;
 924
 925   switch (Type) {
 926   default:
 927     return false;
 928   case ELF::R_RISCV_PCREL_LO12_I:
 929   case ELF::R_RISCV_PCREL_LO12_S:
 930     return true;
 931   }
 932 }
 933
 934 uint64_t Relocation::getNone() {
 935   switch (Arch) {
 936   default:
 937     llvm_unreachable("Unsupported architecture");
 938   case Triple::aarch64:
 939     return ELF::R_AARCH64_NONE;
 940   case Triple::riscv64:
 941     return ELF::R_RISCV_NONE;
 942   case Triple::x86_64:
 943     return ELF::R_X86_64_NONE;
 944   }
 945 }
 946
 947 uint64_t Relocation::getPC32() {
 948   switch (Arch) {
 949   default:
 950     llvm_unreachable("Unsupported architecture");
 951   case Triple::aarch64:
 952     return ELF::R_AARCH64_PREL32;
 953   case Triple::riscv64:
 954     return ELF::R_RISCV_32_PCREL;
 955   case Triple::x86_64:
 956     return ELF::R_X86_64_PC32;
 957   }
 958 }
 959
 960 uint64_t Relocation::getPC64() {
 961   switch (Arch) {
 962   default:
 963     llvm_unreachable("Unsupported architecture");
 964   case Triple::aarch64:
 965     return ELF::R_AARCH64_PREL64;
 966   case Triple::riscv64:
 967     llvm_unreachable("not implemented");
 968   case Triple::x86_64:
 969     return ELF::R_X86_64_PC64;
 970   }
 971 }
 972
 973 bool Relocation::isPCRelative(uint64_t Type) {
 974   switch (Arch) {
 975   default:
 976     llvm_unreachable("Unsupported architecture");
 977   case Triple::aarch64:
 978     return isPCRelativeAArch64(Type);
 979   case Triple::riscv64:
 980     return isPCRelativeRISCV(Type);
 981   case Triple::x86_64:
 982     return isPCRelativeX86(Type);
 983   }
 984 }
 985
 986 uint64_t Relocation::getAbs64() {
 987   switch (Arch) {
 988   default:
 989     llvm_unreachable("Unsupported architecture");
 990   case Triple::aarch64:
 991     return ELF::R_AARCH64_ABS64;
 992   case Triple::riscv64:
 993     return ELF::R_RISCV_64;
 994   case Triple::x86_64:
 995     return ELF::R_X86_64_64;
 996   }
 997 }
 998
 999 uint64_t Relocation::getRelative() {
1000   switch (Arch) {
1001   default:
1002     llvm_unreachable("Unsupported architecture");
1003   case Triple::aarch64:
1004     return ELF::R_AARCH64_RELATIVE;
1005   case Triple::riscv64:
1006     llvm_unreachable("not implemented");
1007   case Triple::x86_64:
1008     return ELF::R_X86_64_RELATIVE;
1009   }
1010 }
1011
1012 size_t Relocation::emit(MCStreamer *Streamer) const {
1013   const size_t Size = getSizeForType(Type);
1014   const auto *Value = createExpr(Streamer);
1015   Streamer->emitValue(Value, Size);
1016   return Size;
1017 }
1018
1019 const MCExpr *Relocation::createExpr(MCStreamer *Streamer) const {
1020   MCContext &Ctx = Streamer->getContext();
1021   const MCExpr *Value = nullptr;
1022
1023   if (Symbol && Addend) {
1024     Value = MCBinaryExpr::createAdd(MCSymbolRefExpr::create(Symbol, Ctx),
1025                                     MCConstantExpr::create(Addend, Ctx), Ctx);
1026   } else if (Symbol) {
1027     Value = MCSymbolRefExpr::create(Symbol, Ctx);
1028   } else {
1029     Value = MCConstantExpr::create(Addend, Ctx);
1030   }
1031
1032   if (isPCRelative(Type)) {
1033     MCSymbol *TempLabel = Ctx.createNamedTempSymbol();
1034     Streamer->emitLabel(TempLabel);
1035     Value = MCBinaryExpr::createSub(
1036         Value, MCSymbolRefExpr::create(TempLabel, Ctx), Ctx);
1037   }
1038
1039   return Value;
1040 }
1041
1042 const MCExpr *Relocation::createExpr(MCStreamer *Streamer,
1043                                      const MCExpr *RetainedValue) const {
1044   const auto *Value = createExpr(Streamer);
1045
1046   if (RetainedValue) {
1047     Value = MCBinaryExpr::create(getComposeOpcodeFor(Type), RetainedValue,
1048                                  Value, Streamer->getContext());
1049   }
1050
1051   return Value;
1052 }
1053
1054 MCBinaryExpr::Opcode Relocation::getComposeOpcodeFor(uint64_t Type) {
1055   assert(Arch == Triple::riscv64 && "only implemented for RISC-V");
1056
1057   switch (Type) {
1058   default:
1059     llvm_unreachable("not implemented");
1060   case ELF::R_RISCV_ADD32:
1061     return MCBinaryExpr::Add;
1062   case ELF::R_RISCV_SUB32:
1063     return MCBinaryExpr::Sub;
1064   }
1065 }
1066
1067 void Relocation::print(raw_ostream &OS) const {
1068   switch (Arch) {
1069   default:
1070     OS << "RType:" << Twine::utohexstr(Type);
1071     break;
1072
1073   case Triple::aarch64:
1074     static const char *const AArch64RelocNames[] = {
1075 #define ELF_RELOC(name, value) #name,
1076 #include "llvm/BinaryFormat/ELFRelocs/AArch64.def"
1077 #undef ELF_RELOC
1078     };
1079     assert(Type < ArrayRef(AArch64RelocNames).size());
1080     OS << AArch64RelocNames[Type];
1081     break;
1082
1083   case Triple::riscv64:
1084     // RISC-V relocations are not sequentially numbered so we cannot use an
1085     // array
1086     switch (Type) {
1087     default:
1088       llvm_unreachable("illegal RISC-V relocation");
1089 #define ELF_RELOC(name, value)                                                 \
1090   case value:                                                                  \
1091     OS << #name;                                                               \
1092     break;
1093 #include "llvm/BinaryFormat/ELFRelocs/RISCV.def"
1094 #undef ELF_RELOC
1095     }
1096     break;
1097
1098   case Triple::x86_64:
1099     static const char *const X86RelocNames[] = {
1100 #define ELF_RELOC(name, value) #name,
1101 #include "llvm/BinaryFormat/ELFRelocs/x86_64.def"
1102 #undef ELF_RELOC
1103     };
1104     assert(Type < ArrayRef(X86RelocNames).size());
1105     OS << X86RelocNames[Type];
1106     break;
1107   }
1108   OS << ", 0x" << Twine::utohexstr(Offset);
1109   if (Symbol) {
1110     OS << ", " << Symbol->getName();
1111   }
1112   if (int64_t(Addend) < 0)
1113     OS << ", -0x" << Twine::utohexstr(-int64_t(Addend));
1114   else
1115     OS << ", 0x" << Twine::utohexstr(Addend);
1116   OS << ", 0x" << Twine::utohexstr(Value);
1117 }