[RISCV] Refactor predicates for rvv intrinsic patterns.
[llvm-project.git] / llvm / docs / AMDGPU / gfx1030_sbase_020892.rst
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10 sbase
11 =====
13 A 64-bit base address for scalar memory operations.
15 *Size:* 2 dwords.
17 *Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`