[RISCV] Refactor predicates for rvv intrinsic patterns.
[llvm-project.git] / llvm / docs / AMDGPU / gfx10_saddr_beaa25.rst
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8 .. _amdgpu_synid_gfx10_saddr_beaa25:
10 saddr
11 =====
13 An optional 64-bit flat global address. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
15 See :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>` for description of available addressing modes.
17 *Size:* 2 dwords.
19 *Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`off<amdgpu_synid_off>`