[RISCV] Refactor predicates for rvv intrinsic patterns.
[llvm-project.git] / llvm / docs / AMDGPU / gfx10_sdata_6fbc49.rst
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8 .. _amdgpu_synid_gfx10_sdata_6fbc49:
10 sdata
11 =====
13 Instruction input.
15 *Size:* 1 dword.
17 *Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`