[RISCV] Refactor predicates for rvv intrinsic patterns.
[llvm-project.git] / llvm / docs / AMDGPU / gfx10_vaddr_a5639c.rst
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8 .. _amdgpu_synid_gfx10_vaddr_a5639c:
10 vaddr
11 =====
13 Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
15 This operand may be specified using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`.
17 *Size:* 1-12 dwords. Actual size depends on opcode, :ref:`dim<amdgpu_synid_dim>` and :ref:`a16<amdgpu_synid_a16>`.
19 *Operands:* :ref:`v<amdgpu_synid_v>`