[RISCV] Refactor predicates for rvv intrinsic patterns.
[llvm-project.git] / llvm / docs / AMDGPU / gfx11_vdata0_6802ce.rst
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8 .. _amdgpu_synid_gfx11_vdata0_6802ce:
10 vdata0
11 ======
13 Instruction input.
15 *Size:* 1 dword.
17 *Operands:* :ref:`v<amdgpu_synid_v>`