[RISCV] Refactor predicates for rvv intrinsic patterns.
[llvm-project.git] / llvm / docs / AMDGPU / gfx11_vsrc_1c4e7f.rst
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8 .. _amdgpu_synid_gfx11_vsrc_1c4e7f:
10 vsrc
11 ====
13 Instruction input.
15 *Size:* 16 bits.
17 *Operands:* :ref:`v<amdgpu_synid_v16>`