[RISCV] Refactor predicates for rvv intrinsic patterns.
[llvm-project.git] / llvm / docs / AMDGPU / gfx7_ssrc_b0d552.rst
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8 .. _amdgpu_synid_gfx7_ssrc_b0d552:
10 ssrc
11 ====
13 Instruction input.
15 *Size:* 2 dwords.
17 *Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`