[RISCV] Refactor predicates for rvv intrinsic patterns.
[llvm-project.git] / llvm / docs / AMDGPU / gfx7_vdst_a49b76.rst
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10 vdst
11 ====
13 Instruction output: data read from a memory buffer.
15 *Size:* 3 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
17 *Operands:* :ref:`v<amdgpu_synid_v>`