[RISCV] Refactor predicates for rvv intrinsic patterns.
[llvm-project.git] / llvm / docs / AMDGPU / gfx90a_vdst_f5eb9d.rst
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10 vdst
11 ====
13 Image data to be loaded by an image instruction.
15 *Size:* depends on :ref:`dmask<amdgpu_synid_dmask>`:
17 * :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies 1 dword.
20 *Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`