1 =======================
2 Writing an LLVM Backend
3 =======================
16 This document describes techniques for writing compiler backends that convert
17 the LLVM Intermediate Representation (IR) to code for a specified machine or
18 other languages. Code intended for a specific machine can take the form of
19 either assembly code or binary code (usable for a JIT compiler).
21 The backend of LLVM features a target-independent code generator that may
22 create output for several types of target CPUs --- including X86, PowerPC,
23 ARM, and SPARC. The backend may also be used to generate code targeted at SPUs
24 of the Cell processor or GPUs to support the execution of compute kernels.
26 The document focuses on existing examples found in subdirectories of
27 ``llvm/lib/Target`` in a downloaded LLVM release. In particular, this document
28 focuses on the example of creating a static compiler (one that emits text
29 assembly) for a SPARC target, because SPARC has fairly standard
30 characteristics, such as a RISC instruction set and straightforward calling
36 The audience for this document is anyone who needs to write an LLVM backend to
37 generate code for a specific hardware or software target.
42 These essential documents must be read before reading this document:
44 * `LLVM Language Reference Manual <LangRef.html>`_ --- a reference manual for
45 the LLVM assembly language.
47 * :doc:`CodeGenerator` --- a guide to the components (classes and code
48 generation algorithms) for translating the LLVM internal representation into
49 machine code for a specified target. Pay particular attention to the
50 descriptions of code generation stages: Instruction Selection, Scheduling and
51 Formation, SSA-based Optimization, Register Allocation, Prolog/Epilog Code
52 Insertion, Late Machine Code Optimizations, and Code Emission.
54 * :doc:`TableGen/index` --- a document that describes the TableGen
55 (``tblgen``) application that manages domain-specific information to support
56 LLVM code generation. TableGen processes input from a target description
57 file (``.td`` suffix) and generates C++ code that can be used for code
60 * :doc:`WritingAnLLVMPass` --- The assembly printer is a ``FunctionPass``, as
61 are several ``SelectionDAG`` processing steps.
63 To follow the SPARC examples in this document, have a copy of `The SPARC
64 Architecture Manual, Version 8 <http://www.sparc.org/standards/V8.pdf>`_ for
65 reference. For details about the ARM instruction set, refer to the `ARM
66 Architecture Reference Manual <http://infocenter.arm.com/>`_. For more about
67 the GNU Assembler format (``GAS``), see `Using As
68 <http://sourceware.org/binutils/docs/as/index.html>`_, especially for the
69 assembly printer. "Using As" contains a list of target machine dependent
75 To write a compiler backend for LLVM that converts the LLVM IR to code for a
76 specified target (machine or other language), follow these steps:
78 * Create a subclass of the ``TargetMachine`` class that describes
79 characteristics of your target machine. Copy existing examples of specific
80 ``TargetMachine`` class and header files; for example, start with
81 ``SparcTargetMachine.cpp`` and ``SparcTargetMachine.h``, but change the file
82 names for your target. Similarly, change code that references "``Sparc``" to
83 reference your target.
85 * Describe the register set of the target. Use TableGen to generate code for
86 register definition, register aliases, and register classes from a
87 target-specific ``RegisterInfo.td`` input file. You should also write
88 additional code for a subclass of the ``TargetRegisterInfo`` class that
89 represents the class register file data used for register allocation and also
90 describes the interactions between registers.
92 * Describe the instruction set of the target. Use TableGen to generate code
93 for target-specific instructions from target-specific versions of
94 ``TargetInstrFormats.td`` and ``TargetInstrInfo.td``. You should write
95 additional code for a subclass of the ``TargetInstrInfo`` class to represent
96 machine instructions supported by the target machine.
98 * Describe the selection and conversion of the LLVM IR from a Directed Acyclic
99 Graph (DAG) representation of instructions to native target-specific
100 instructions. Use TableGen to generate code that matches patterns and
101 selects instructions based on additional information in a target-specific
102 version of ``TargetInstrInfo.td``. Write code for ``XXXISelDAGToDAG.cpp``,
103 where ``XXX`` identifies the specific target, to perform pattern matching and
104 DAG-to-DAG instruction selection. Also write code in ``XXXISelLowering.cpp``
105 to replace or remove operations and data types that are not supported
106 natively in a SelectionDAG.
108 * Write code for an assembly printer that converts LLVM IR to a GAS format for
109 your target machine. You should add assembly strings to the instructions
110 defined in your target-specific version of ``TargetInstrInfo.td``. You
111 should also write code for a subclass of ``AsmPrinter`` that performs the
112 LLVM-to-assembly conversion and a trivial subclass of ``TargetAsmInfo``.
114 * Optionally, add support for subtargets (i.e., variants with different
115 capabilities). You should also write code for a subclass of the
116 ``TargetSubtarget`` class, which allows you to use the ``-mcpu=`` and
117 ``-mattr=`` command-line options.
119 * Optionally, add JIT support and create a machine code emitter (subclass of
120 ``TargetJITInfo``) that is used to emit binary code directly into memory.
122 In the ``.cpp`` and ``.h``. files, initially stub up these methods and then
123 implement them later. Initially, you may not know which private members that
124 the class will need and which components will need to be subclassed.
129 To actually create your compiler backend, you need to create and modify a few
130 files. The absolute minimum is discussed here. But to actually use the LLVM
131 target-independent code generator, you must perform the steps described in the
132 :doc:`LLVM Target-Independent Code Generator <CodeGenerator>` document.
134 First, you should create a subdirectory under ``lib/Target`` to hold all the
135 files related to your target. If your target is called "Dummy", create the
136 directory ``lib/Target/Dummy``.
138 In this new directory, create a ``CMakeLists.txt``. It is easiest to copy a
139 ``CMakeLists.txt`` of another target and modify it. It should at least contain
140 the ``LLVM_TARGET_DEFINITIONS`` variable. The library can be named ``LLVMDummy``
141 (for example, see the MIPS target). Alternatively, you can split the library
142 into ``LLVMDummyCodeGen`` and ``LLVMDummyAsmPrinter``, the latter of which
143 should be implemented in a subdirectory below ``lib/Target/Dummy`` (for example,
144 see the PowerPC target).
146 Note that these two naming schemes are hardcoded into ``llvm-config``. Using
147 any other naming scheme will confuse ``llvm-config`` and produce a lot of
148 (seemingly unrelated) linker errors when linking ``llc``.
150 To make your target actually do something, you need to implement a subclass of
151 ``TargetMachine``. This implementation should typically be in the file
152 ``lib/Target/DummyTargetMachine.cpp``, but any file in the ``lib/Target``
153 directory will be built and should work. To use LLVM's target independent code
154 generator, you should do what all current machine backends do: create a
155 subclass of ``LLVMTargetMachine``. (To create a target from scratch, create a
156 subclass of ``TargetMachine``.)
158 To get LLVM to actually build and link your target, you need to run ``cmake``
159 with ``-DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD=Dummy``. This will build your
160 target without needing to add it to the list of all the targets.
162 Once your target is stable, you can add it to the ``LLVM_ALL_TARGETS`` variable
163 located in the main ``CMakeLists.txt``.
168 ``LLVMTargetMachine`` is designed as a base class for targets implemented with
169 the LLVM target-independent code generator. The ``LLVMTargetMachine`` class
170 should be specialized by a concrete target class that implements the various
171 virtual methods. ``LLVMTargetMachine`` is defined as a subclass of
172 ``TargetMachine`` in ``include/llvm/Target/TargetMachine.h``. The
173 ``TargetMachine`` class implementation (``TargetMachine.cpp``) also processes
174 numerous command-line options.
176 To create a concrete target-specific subclass of ``LLVMTargetMachine``, start
177 by copying an existing ``TargetMachine`` class and header. You should name the
178 files that you create to reflect your specific target. For instance, for the
179 SPARC target, name the files ``SparcTargetMachine.h`` and
180 ``SparcTargetMachine.cpp``.
182 For a target machine ``XXX``, the implementation of ``XXXTargetMachine`` must
183 have access methods to obtain objects that represent target components. These
184 methods are named ``get*Info``, and are intended to obtain the instruction set
185 (``getInstrInfo``), register set (``getRegisterInfo``), stack frame layout
186 (``getFrameInfo``), and similar information. ``XXXTargetMachine`` must also
187 implement the ``getDataLayout`` method to access an object with target-specific
188 data characteristics, such as data type size and alignment requirements.
190 For instance, for the SPARC target, the header file ``SparcTargetMachine.h``
191 declares prototypes for several ``get*Info`` and ``getDataLayout`` methods that
192 simply return a class member.
200 class SparcTargetMachine : public LLVMTargetMachine {
201 const DataLayout DataLayout; // Calculates type size & alignment
202 SparcSubtarget Subtarget;
203 SparcInstrInfo InstrInfo;
204 TargetFrameInfo FrameInfo;
207 virtual const TargetAsmInfo *createTargetAsmInfo() const;
210 SparcTargetMachine(const Module &M, const std::string &FS);
212 virtual const SparcInstrInfo *getInstrInfo() const {return &InstrInfo; }
213 virtual const TargetFrameInfo *getFrameInfo() const {return &FrameInfo; }
214 virtual const TargetSubtarget *getSubtargetImpl() const{return &Subtarget; }
215 virtual const TargetRegisterInfo *getRegisterInfo() const {
216 return &InstrInfo.getRegisterInfo();
218 virtual const DataLayout *getDataLayout() const { return &DataLayout; }
219 static unsigned getModuleMatchQuality(const Module &M);
221 // Pass Pipeline Configuration
222 virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
223 virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
226 } // end namespace llvm
229 * ``getRegisterInfo()``
231 * ``getDataLayout()``
232 * ``getSubtargetImpl()``
234 For some targets, you also need to support the following methods:
236 * ``getTargetLowering()``
239 Some architectures, such as GPUs, do not support jumping to an arbitrary
240 program location and implement branching using masked execution and loop using
241 special instructions around the loop body. In order to avoid CFG modifications
242 that introduce irreducible control flow not handled by such hardware, a target
243 must call `setRequiresStructuredCFG(true)` when being initialized.
245 In addition, the ``XXXTargetMachine`` constructor should specify a
246 ``TargetDescription`` string that determines the data layout for the target
247 machine, including characteristics such as pointer size, alignment, and
248 endianness. For example, the constructor for ``SparcTargetMachine`` contains
253 SparcTargetMachine::SparcTargetMachine(const Module &M, const std::string &FS)
254 : DataLayout("E-p:32:32-f128:128:128"),
255 Subtarget(M, FS), InstrInfo(Subtarget),
256 FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) {
259 Hyphens separate portions of the ``TargetDescription`` string.
261 * An upper-case "``E``" in the string indicates a big-endian target data model.
262 A lower-case "``e``" indicates little-endian.
264 * "``p:``" is followed by pointer information: size, ABI alignment, and
265 preferred alignment. If only two figures follow "``p:``", then the first
266 value is pointer size, and the second value is both ABI and preferred
269 * Then a letter for numeric type alignment: "``i``", "``f``", "``v``", or
270 "``a``" (corresponding to integer, floating point, vector, or aggregate).
271 "``i``", "``v``", or "``a``" are followed by ABI alignment and preferred
272 alignment. "``f``" is followed by three values: the first indicates the size
273 of a long double, then ABI alignment, and then ABI preferred alignment.
278 You must also register your target with the ``TargetRegistry``, which is what
279 other LLVM tools use to be able to lookup and use your target at runtime. The
280 ``TargetRegistry`` can be used directly, but for most targets there are helper
281 templates which should take care of the work for you.
283 All targets should declare a global ``Target`` object which is used to
284 represent the target during registration. Then, in the target's ``TargetInfo``
285 library, the target should define that object and use the ``RegisterTarget``
286 template to register the target. For example, the Sparc registration code
291 Target llvm::getTheSparcTarget();
293 extern "C" void LLVMInitializeSparcTargetInfo() {
294 RegisterTarget<Triple::sparc, /*HasJIT=*/false>
295 X(getTheSparcTarget(), "sparc", "Sparc");
298 This allows the ``TargetRegistry`` to look up the target by name or by target
299 triple. In addition, most targets will also register additional features which
300 are available in separate libraries. These registration steps are separate,
301 because some clients may wish to only link in some parts of the target --- the
302 JIT code generator does not require the use of the assembler printer, for
303 example. Here is an example of registering the Sparc assembly printer:
307 extern "C" void LLVMInitializeSparcAsmPrinter() {
308 RegisterAsmPrinter<SparcAsmPrinter> X(getTheSparcTarget());
311 For more information, see "`llvm/Target/TargetRegistry.h
312 </doxygen/TargetRegistry_8h-source.html>`_".
314 Register Set and Register Classes
315 =================================
317 You should describe a concrete target-specific class that represents the
318 register file of a target machine. This class is called ``XXXRegisterInfo``
319 (where ``XXX`` identifies the target) and represents the class register file
320 data that is used for register allocation. It also describes the interactions
323 You also need to define register classes to categorize related registers. A
324 register class should be added for groups of registers that are all treated the
325 same way for some instruction. Typical examples are register classes for
326 integer, floating-point, or vector registers. A register allocator allows an
327 instruction to use any register in a specified register class to perform the
328 instruction in a similar manner. Register classes allocate virtual registers
329 to instructions from these sets, and register classes let the
330 target-independent register allocator automatically choose the actual
333 Much of the code for registers, including register definition, register
334 aliases, and register classes, is generated by TableGen from
335 ``XXXRegisterInfo.td`` input files and placed in ``XXXGenRegisterInfo.h.inc``
336 and ``XXXGenRegisterInfo.inc`` output files. Some of the code in the
337 implementation of ``XXXRegisterInfo`` requires hand-coding.
342 The ``XXXRegisterInfo.td`` file typically starts with register definitions for
343 a target machine. The ``Register`` class (specified in ``Target.td``) is used
344 to define an object for each register. The specified string ``n`` becomes the
345 ``Name`` of the register. The basic ``Register`` object does not have any
346 subregisters and does not specify any aliases.
350 class Register<string n> {
351 string Namespace = "";
355 int SpillAlignment = 0;
356 list<Register> Aliases = [];
357 list<Register> SubRegs = [];
358 list<int> DwarfNumbers = [];
361 For example, in the ``X86RegisterInfo.td`` file, there are register definitions
362 that utilize the ``Register`` class, such as:
366 def AL : Register<"AL">, DwarfRegNum<[0, 0, 0]>;
368 This defines the register ``AL`` and assigns it values (with ``DwarfRegNum``)
369 that are used by ``gcc``, ``gdb``, or a debug information writer to identify a
370 register. For register ``AL``, ``DwarfRegNum`` takes an array of 3 values
371 representing 3 different modes: the first element is for X86-64, the second for
372 exception handling (EH) on X86-32, and the third is generic. -1 is a special
373 Dwarf number that indicates the gcc number is undefined, and -2 indicates the
374 register number is invalid for this mode.
376 From the previously described line in the ``X86RegisterInfo.td`` file, TableGen
377 generates this code in the ``X86GenRegisterInfo.inc`` file:
381 static const unsigned GR8[] = { X86::AL, ... };
383 const unsigned AL_AliasSet[] = { X86::AX, X86::EAX, X86::RAX, 0 };
385 const TargetRegisterDesc RegisterDescriptors[] = {
387 { "AL", "AL", AL_AliasSet, Empty_SubRegsSet, Empty_SubRegsSet, AL_SuperRegsSet }, ...
389 From the register info file, TableGen generates a ``TargetRegisterDesc`` object
390 for each register. ``TargetRegisterDesc`` is defined in
391 ``include/llvm/Target/TargetRegisterInfo.h`` with the following fields:
395 struct TargetRegisterDesc {
396 const char *AsmName; // Assembly language name for the register
397 const char *Name; // Printable name for the reg (for debugging)
398 const unsigned *AliasSet; // Register Alias Set
399 const unsigned *SubRegs; // Sub-register set
400 const unsigned *ImmSubRegs; // Immediate sub-register set
401 const unsigned *SuperRegs; // Super-register set
404 TableGen uses the entire target description file (``.td``) to determine text
405 names for the register (in the ``AsmName`` and ``Name`` fields of
406 ``TargetRegisterDesc``) and the relationships of other registers to the defined
407 register (in the other ``TargetRegisterDesc`` fields). In this example, other
408 definitions establish the registers "``AX``", "``EAX``", and "``RAX``" as
409 aliases for one another, so TableGen generates a null-terminated array
410 (``AL_AliasSet``) for this register alias set.
412 The ``Register`` class is commonly used as a base class for more complex
413 classes. In ``Target.td``, the ``Register`` class is the base for the
414 ``RegisterWithSubRegs`` class that is used to define registers that need to
415 specify subregisters in the ``SubRegs`` list, as shown here:
419 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
420 let SubRegs = subregs;
423 In ``SparcRegisterInfo.td``, additional register classes are defined for SPARC:
424 a ``Register`` subclass, ``SparcReg``, and further subclasses: ``Ri``, ``Rf``,
425 and ``Rd``. SPARC registers are identified by 5-bit ID numbers, which is a
426 feature common to these subclasses. Note the use of "``let``" expressions to
427 override values that are initially defined in a superclass (such as ``SubRegs``
428 field in the ``Rd`` class).
432 class SparcReg<string n> : Register<n> {
434 let Namespace = "SP";
436 // Ri - 32-bit integer registers
437 class Ri<bits<5> num, string n> :
441 // Rf - 32-bit floating-point registers
442 class Rf<bits<5> num, string n> :
446 // Rd - Slots in the FP register file for 64-bit floating-point values.
447 class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> {
449 let SubRegs = subregs;
452 In the ``SparcRegisterInfo.td`` file, there are register definitions that
453 utilize these subclasses of ``Register``, such as:
457 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
458 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
460 def F0 : Rf< 0, "F0">, DwarfRegNum<[32]>;
461 def F1 : Rf< 1, "F1">, DwarfRegNum<[33]>;
463 def D0 : Rd< 0, "F0", [F0, F1]>, DwarfRegNum<[32]>;
464 def D1 : Rd< 2, "F2", [F2, F3]>, DwarfRegNum<[34]>;
466 The last two registers shown above (``D0`` and ``D1``) are double-precision
467 floating-point registers that are aliases for pairs of single-precision
468 floating-point sub-registers. In addition to aliases, the sub-register and
469 super-register relationships of the defined register are in fields of a
470 register's ``TargetRegisterDesc``.
472 Defining a Register Class
473 -------------------------
475 The ``RegisterClass`` class (specified in ``Target.td``) is used to define an
476 object that represents a group of related registers and also defines the
477 default allocation order of the registers. A target description file
478 ``XXXRegisterInfo.td`` that uses ``Target.td`` can construct register classes
479 using the following class:
483 class RegisterClass<string namespace,
484 list<ValueType> regTypes, int alignment, dag regList> {
485 string Namespace = namespace;
486 list<ValueType> RegTypes = regTypes;
487 int Size = 0; // spill size, in bits; zero lets tblgen pick the size
488 int Alignment = alignment;
490 // CopyCost is the cost of copying a value between two registers
491 // default value 1 means a single instruction
492 // A negative value means copying is extremely expensive or impossible
494 dag MemberList = regList;
496 // for register classes that are subregisters of this class
497 list<RegisterClass> SubRegClassList = [];
499 code MethodProtos = [{}]; // to insert arbitrary code
500 code MethodBodies = [{}];
503 To define a ``RegisterClass``, use the following 4 arguments:
505 * The first argument of the definition is the name of the namespace.
507 * The second argument is a list of ``ValueType`` register type values that are
508 defined in ``include/llvm/CodeGen/ValueTypes.td``. Defined values include
509 integer types (such as ``i16``, ``i32``, and ``i1`` for Boolean),
510 floating-point types (``f32``, ``f64``), and vector types (for example,
511 ``v8i16`` for an ``8 x i16`` vector). All registers in a ``RegisterClass``
512 must have the same ``ValueType``, but some registers may store vector data in
513 different configurations. For example a register that can process a 128-bit
514 vector may be able to handle 16 8-bit integer elements, 8 16-bit integers, 4
515 32-bit integers, and so on.
517 * The third argument of the ``RegisterClass`` definition specifies the
518 alignment required of the registers when they are stored or loaded to
521 * The final argument, ``regList``, specifies which registers are in this class.
522 If an alternative allocation order method is not specified, then ``regList``
523 also defines the order of allocation used by the register allocator. Besides
524 simply listing registers with ``(add R0, R1, ...)``, more advanced set
525 operators are available. See ``include/llvm/Target/Target.td`` for more
528 In ``SparcRegisterInfo.td``, three ``RegisterClass`` objects are defined:
529 ``FPRegs``, ``DFPRegs``, and ``IntRegs``. For all three register classes, the
530 first argument defines the namespace with the string "``SP``". ``FPRegs``
531 defines a group of 32 single-precision floating-point registers (``F0`` to
532 ``F31``); ``DFPRegs`` defines a group of 16 double-precision registers
537 // F0, F1, F2, ..., F31
538 def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>;
540 def DFPRegs : RegisterClass<"SP", [f64], 64,
541 (add D0, D1, D2, D3, D4, D5, D6, D7, D8,
542 D9, D10, D11, D12, D13, D14, D15)>;
544 def IntRegs : RegisterClass<"SP", [i32], 32,
545 (add L0, L1, L2, L3, L4, L5, L6, L7,
546 I0, I1, I2, I3, I4, I5,
547 O0, O1, O2, O3, O4, O5, O7,
549 // Non-allocatable regs:
553 I7, // return address
555 G5, G6, G7 // reserved for kernel
558 Using ``SparcRegisterInfo.td`` with TableGen generates several output files
559 that are intended for inclusion in other source code that you write.
560 ``SparcRegisterInfo.td`` generates ``SparcGenRegisterInfo.h.inc``, which should
561 be included in the header file for the implementation of the SPARC register
562 implementation that you write (``SparcRegisterInfo.h``). In
563 ``SparcGenRegisterInfo.h.inc`` a new structure is defined called
564 ``SparcGenRegisterInfo`` that uses ``TargetRegisterInfo`` as its base. It also
565 specifies types, based upon the defined register classes: ``DFPRegsClass``,
566 ``FPRegsClass``, and ``IntRegsClass``.
568 ``SparcRegisterInfo.td`` also generates ``SparcGenRegisterInfo.inc``, which is
569 included at the bottom of ``SparcRegisterInfo.cpp``, the SPARC register
570 implementation. The code below shows only the generated integer registers and
571 associated register classes. The order of registers in ``IntRegs`` reflects
572 the order in the definition of ``IntRegs`` in the target description file.
576 // IntRegs Register Class...
577 static const unsigned IntRegs[] = {
578 SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5,
579 SP::L6, SP::L7, SP::I0, SP::I1, SP::I2, SP::I3,
580 SP::I4, SP::I5, SP::O0, SP::O1, SP::O2, SP::O3,
581 SP::O4, SP::O5, SP::O7, SP::G1, SP::G2, SP::G3,
582 SP::G4, SP::O6, SP::I6, SP::I7, SP::G0, SP::G5,
586 // IntRegsVTs Register Class Value Types...
587 static const MVT::ValueType IntRegsVTs[] = {
591 namespace SP { // Register class instances
592 DFPRegsClass DFPRegsRegClass;
593 FPRegsClass FPRegsRegClass;
594 IntRegsClass IntRegsRegClass;
596 // IntRegs Sub-register Classes...
597 static const TargetRegisterClass* const IntRegsSubRegClasses [] = {
601 // IntRegs Super-register Classes..
602 static const TargetRegisterClass* const IntRegsSuperRegClasses [] = {
606 // IntRegs Register Class sub-classes...
607 static const TargetRegisterClass* const IntRegsSubclasses [] = {
611 // IntRegs Register Class super-classes...
612 static const TargetRegisterClass* const IntRegsSuperclasses [] = {
616 IntRegsClass::IntRegsClass() : TargetRegisterClass(IntRegsRegClassID,
617 IntRegsVTs, IntRegsSubclasses, IntRegsSuperclasses, IntRegsSubRegClasses,
618 IntRegsSuperRegClasses, 4, 4, 1, IntRegs, IntRegs + 32) {}
621 The register allocators will avoid using reserved registers, and callee saved
622 registers are not used until all the volatile registers have been used. That
623 is usually good enough, but in some cases it may be necessary to provide custom
626 Implement a subclass of ``TargetRegisterInfo``
627 ----------------------------------------------
629 The final step is to hand code portions of ``XXXRegisterInfo``, which
630 implements the interface described in ``TargetRegisterInfo.h`` (see
631 :ref:`TargetRegisterInfo`). These functions return ``0``, ``NULL``, or
632 ``false``, unless overridden. Here is a list of functions that are overridden
633 for the SPARC implementation in ``SparcRegisterInfo.cpp``:
635 * ``getCalleeSavedRegs`` --- Returns a list of callee-saved registers in the
636 order of the desired callee-save stack frame offset.
638 * ``getReservedRegs`` --- Returns a bitset indexed by physical register
639 numbers, indicating if a particular register is unavailable.
641 * ``hasFP`` --- Return a Boolean indicating if a function should have a
642 dedicated frame pointer register.
644 * ``eliminateCallFramePseudoInstr`` --- If call frame setup or destroy pseudo
645 instructions are used, this can be called to eliminate them.
647 * ``eliminateFrameIndex`` --- Eliminate abstract frame indices from
648 instructions that may use them.
650 * ``emitPrologue`` --- Insert prologue code into the function.
652 * ``emitEpilogue`` --- Insert epilogue code into the function.
659 During the early stages of code generation, the LLVM IR code is converted to a
660 ``SelectionDAG`` with nodes that are instances of the ``SDNode`` class
661 containing target instructions. An ``SDNode`` has an opcode, operands, type
662 requirements, and operation properties. For example, is an operation
663 commutative, does an operation load from memory. The various operation node
664 types are described in the ``include/llvm/CodeGen/SelectionDAGNodes.h`` file
665 (values of the ``NodeType`` enum in the ``ISD`` namespace).
667 TableGen uses the following target description (``.td``) input files to
668 generate much of the code for instruction definition:
670 * ``Target.td`` --- Where the ``Instruction``, ``Operand``, ``InstrInfo``, and
671 other fundamental classes are defined.
673 * ``TargetSelectionDAG.td`` --- Used by ``SelectionDAG`` instruction selection
674 generators, contains ``SDTC*`` classes (selection DAG type constraint),
675 definitions of ``SelectionDAG`` nodes (such as ``imm``, ``cond``, ``bb``,
676 ``add``, ``fadd``, ``sub``), and pattern support (``Pattern``, ``Pat``,
677 ``PatFrag``, ``PatLeaf``, ``ComplexPattern``.
679 * ``XXXInstrFormats.td`` --- Patterns for definitions of target-specific
682 * ``XXXInstrInfo.td`` --- Target-specific definitions of instruction templates,
683 condition codes, and instructions of an instruction set. For architecture
684 modifications, a different file name may be used. For example, for Pentium
685 with SSE instruction, this file is ``X86InstrSSE.td``, and for Pentium with
686 MMX, this file is ``X86InstrMMX.td``.
688 There is also a target-specific ``XXX.td`` file, where ``XXX`` is the name of
689 the target. The ``XXX.td`` file includes the other ``.td`` input files, but
690 its contents are only directly important for subtargets.
692 You should describe a concrete target-specific class ``XXXInstrInfo`` that
693 represents machine instructions supported by a target machine.
694 ``XXXInstrInfo`` contains an array of ``XXXInstrDescriptor`` objects, each of
695 which describes one instruction. An instruction descriptor defines:
699 * List of implicit register definitions and uses
700 * Target-independent properties (such as memory access, is commutable)
701 * Target-specific flags
703 The Instruction class (defined in ``Target.td``) is mostly used as a base for
704 more complex instruction classes.
709 string Namespace = "";
710 dag OutOperandList; // A dag containing the MI def operand list.
711 dag InOperandList; // A dag containing the MI use operand list.
712 string AsmString = ""; // The .s format to print the instruction with.
713 list<dag> Pattern; // Set to the DAG pattern for this instruction.
714 list<Register> Uses = [];
715 list<Register> Defs = [];
716 list<Predicate> Predicates = []; // predicates turned into isel match code
717 ... remainder not shown for space ...
720 A ``SelectionDAG`` node (``SDNode``) should contain an object representing a
721 target-specific instruction that is defined in ``XXXInstrInfo.td``. The
722 instruction objects should represent instructions from the architecture manual
723 of the target machine (such as the SPARC Architecture Manual for the SPARC
726 A single instruction from the architecture manual is often modeled as multiple
727 target instructions, depending upon its operands. For example, a manual might
728 describe an add instruction that takes a register or an immediate operand. An
729 LLVM target could model this with two instructions named ``ADDri`` and
732 You should define a class for each instruction category and define each opcode
733 as a subclass of the category with appropriate parameters such as the fixed
734 binary encoding of opcodes and extended opcodes. You should map the register
735 bits to the bits of the instruction in which they are encoded (for the JIT).
736 Also you should specify how the instruction should be printed when the
737 automatic assembly printer is used.
739 As is described in the SPARC Architecture Manual, Version 8, there are three
740 major 32-bit formats for instructions. Format 1 is only for the ``CALL``
741 instruction. Format 2 is for branch on condition codes and ``SETHI`` (set high
742 bits of a register) instructions. Format 3 is for other instructions.
744 Each of these formats has corresponding classes in ``SparcInstrFormat.td``.
745 ``InstSP`` is a base class for other instruction classes. Additional base
746 classes are specified for more precise formats: for example in
747 ``SparcInstrFormat.td``, ``F2_1`` is for ``SETHI``, and ``F2_2`` is for
748 branches. There are three other base classes: ``F3_1`` for register/register
749 operations, ``F3_2`` for register/immediate operations, and ``F3_3`` for
750 floating-point operations. ``SparcInstrInfo.td`` also adds the base class
751 ``Pseudo`` for synthetic SPARC instructions.
753 ``SparcInstrInfo.td`` largely consists of operand and instruction definitions
754 for the SPARC target. In ``SparcInstrInfo.td``, the following target
755 description file entry, ``LDrr``, defines the Load Integer instruction for a
756 Word (the ``LD`` SPARC opcode) from a memory address to a register. The first
757 parameter, the value 3 (``11``\ :sub:`2`), is the operation value for this
758 category of operation. The second parameter (``000000``\ :sub:`2`) is the
759 specific operation value for ``LD``/Load Word. The third parameter is the
760 output destination, which is a register operand and defined in the ``Register``
761 target description file (``IntRegs``).
765 def LDrr : F3_1 <3, 0b000000, (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr),
767 [(set i32:$dst, (load ADDRrr:$addr))]>;
769 The fourth parameter is the input source, which uses the address operand
770 ``MEMrr`` that is defined earlier in ``SparcInstrInfo.td``:
774 def MEMrr : Operand<i32> {
775 let PrintMethod = "printMemOperand";
776 let MIOperandInfo = (ops IntRegs, IntRegs);
779 The fifth parameter is a string that is used by the assembly printer and can be
780 left as an empty string until the assembly printer interface is implemented.
781 The sixth and final parameter is the pattern used to match the instruction
782 during the SelectionDAG Select Phase described in :doc:`CodeGenerator`.
783 This parameter is detailed in the next section, :ref:`instruction-selector`.
785 Instruction class definitions are not overloaded for different operand types,
786 so separate versions of instructions are needed for register, memory, or
787 immediate value operands. For example, to perform a Load Integer instruction
788 for a Word from an immediate operand to a register, the following instruction
793 def LDri : F3_2 <3, 0b000000, (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr),
795 [(set i32:$rd, (load ADDRri:$addr))]>;
797 Writing these definitions for so many similar instructions can involve a lot of
798 cut and paste. In ``.td`` files, the ``multiclass`` directive enables the
799 creation of templates to define several instruction classes at once (using the
800 ``defm`` directive). For example in ``SparcInstrInfo.td``, the ``multiclass``
801 pattern ``F3_12`` is defined to create 2 instruction classes each time
802 ``F3_12`` is invoked:
806 multiclass F3_12 <string OpcStr, bits<6> Op3Val, SDNode OpNode> {
807 def rr : F3_1 <2, Op3Val,
808 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs1),
809 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
810 [(set i32:$rd, (OpNode i32:$rs1, i32:$rs2))]>;
811 def ri : F3_2 <2, Op3Val,
812 (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
813 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
814 [(set i32:$rd, (OpNode i32:$rs1, simm13:$simm13))]>;
817 So when the ``defm`` directive is used for the ``XOR`` and ``ADD``
818 instructions, as seen below, it creates four instruction objects: ``XORrr``,
819 ``XORri``, ``ADDrr``, and ``ADDri``.
823 defm XOR : F3_12<"xor", 0b000011, xor>;
824 defm ADD : F3_12<"add", 0b000000, add>;
826 ``SparcInstrInfo.td`` also includes definitions for condition codes that are
827 referenced by branch instructions. The following definitions in
828 ``SparcInstrInfo.td`` indicate the bit location of the SPARC condition code.
829 For example, the 10\ :sup:`th` bit represents the "greater than" condition for
830 integers, and the 22\ :sup:`nd` bit represents the "greater than" condition for
835 def ICC_NE : ICC_VAL< 9>; // Not Equal
836 def ICC_E : ICC_VAL< 1>; // Equal
837 def ICC_G : ICC_VAL<10>; // Greater
839 def FCC_U : FCC_VAL<23>; // Unordered
840 def FCC_G : FCC_VAL<22>; // Greater
841 def FCC_UG : FCC_VAL<21>; // Unordered or Greater
844 (Note that ``Sparc.h`` also defines enums that correspond to the same SPARC
845 condition codes. Care must be taken to ensure the values in ``Sparc.h``
846 correspond to the values in ``SparcInstrInfo.td``. I.e., ``SPCC::ICC_NE = 9``,
847 ``SPCC::FCC_U = 23`` and so on.)
849 Instruction Operand Mapping
850 ---------------------------
852 The code generator backend maps instruction operands to fields in the
853 instruction. Whenever a bit in the instruction encoding ``Inst`` is assigned
854 to field without a concrete value, an operand from the ``outs`` or ``ins`` list
855 is expected to have a matching name. This operand then populates that undefined
856 field. For example, the Sparc target defines the ``XNORrr`` instruction as a
857 ``F3_1`` format instruction having three operands: the output ``$rd``, and the
858 inputs ``$rs1``, and ``$rs2``.
862 def XNORrr : F3_1<2, 0b000111,
863 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
864 "xnor $rs1, $rs2, $rd",
865 [(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>;
867 The instruction templates in ``SparcInstrFormats.td`` show the base class for
868 ``F3_1`` is ``InstSP``.
872 class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction {
874 let Namespace = "SP";
876 let Inst{31-30} = op;
877 dag OutOperandList = outs;
878 dag InOperandList = ins;
879 let AsmString = asmstr;
880 let Pattern = pattern;
883 ``InstSP`` defines the ``op`` field, and uses it to define bits 30 and 31 of the
884 instruction, but does not assign a value to it.
888 class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
889 : InstSP<outs, ins, asmstr, pattern> {
893 let op{1} = 1; // Op = 2 or 3
894 let Inst{29-25} = rd;
895 let Inst{24-19} = op3;
896 let Inst{18-14} = rs1;
899 ``F3`` defines the ``rd``, ``op3``, and ``rs1`` fields, and uses them in the
900 instruction, and again does not assign values.
904 class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
905 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
906 bits<8> asi = 0; // asi not currently used
910 let Inst{13} = 0; // i field = 0
911 let Inst{12-5} = asi; // address space identifier
915 ``F3_1`` assigns a value to ``op`` and ``op3`` fields, and defines the ``rs2``
916 field. Therefore, a ``F3_1`` format instruction will require a definition for
917 ``rd``, ``rs1``, and ``rs2`` in order to fully specify the instruction encoding.
919 The ``XNORrr`` instruction then provides those three operands in its
920 OutOperandList and InOperandList, which bind to the corresponding fields, and
921 thus complete the instruction encoding.
923 For some instructions, a single operand may contain sub-operands. As shown
924 earlier, the instruction ``LDrr`` uses an input operand of type ``MEMrr``. This
925 operand type contains two register sub-operands, defined by the
926 ``MIOperandInfo`` value to be ``(ops IntRegs, IntRegs)``.
930 def LDrr : F3_1 <3, 0b000000, (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr),
932 [(set i32:$dst, (load ADDRrr:$addr))]>;
934 As this instruction is also the ``F3_1`` format, it will expect operands named
935 ``rd``, ``rs1``, and ``rs2`` as well. In order to allow this, a complex operand
936 can optionally give names to each of its sub-operands. In this example
937 ``MEMrr``'s first sub-operand is named ``$rs1``, the second ``$rs2``, and the
938 operand as a whole is also given the name ``$addr``.
940 When a particular instruction doesn't use all the operands that the instruction
941 format defines, a constant value may instead be bound to one or all. For
942 example, the ``RDASR`` instruction only takes a single register operand, so we
943 assign a constant zero to ``rs2``:
948 def RDASR : F3_1<2, 0b101000,
949 (outs IntRegs:$rd), (ins ASRRegs:$rs1),
952 Instruction Operand Name Mapping
953 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
955 TableGen will also generate a function called getNamedOperandIdx() which
956 can be used to look up an operand's index in a MachineInstr based on its
957 TableGen name. Setting the UseNamedOperandTable bit in an instruction's
958 TableGen definition will add all of its operands to an enumeration in the
959 llvm::XXX:OpName namespace and also add an entry for it into the OperandMap
960 table, which can be queried using getNamedOperandIdx()
964 int DstIndex = SP::getNamedOperandIdx(SP::XNORrr, SP::OpName::dst); // => 0
965 int BIndex = SP::getNamedOperandIdx(SP::XNORrr, SP::OpName::b); // => 1
966 int CIndex = SP::getNamedOperandIdx(SP::XNORrr, SP::OpName::c); // => 2
967 int DIndex = SP::getNamedOperandIdx(SP::XNORrr, SP::OpName::d); // => -1
971 The entries in the OpName enum are taken verbatim from the TableGen definitions,
972 so operands with lowercase names will have lower case entries in the enum.
974 To include the getNamedOperandIdx() function in your backend, you will need
975 to define a few preprocessor macros in XXXInstrInfo.cpp and XXXInstrInfo.h.
982 #define GET_INSTRINFO_NAMED_OPS // For getNamedOperandIdx() function
983 #include "XXXGenInstrInfo.inc"
989 #define GET_INSTRINFO_OPERAND_ENUM // For OpName enum
990 #include "XXXGenInstrInfo.inc"
993 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
994 } // End namespace XXX
996 Instruction Operand Types
997 ^^^^^^^^^^^^^^^^^^^^^^^^^
999 TableGen will also generate an enumeration consisting of all named Operand
1000 types defined in the backend, in the llvm::XXX::OpTypes namespace.
1001 Some common immediate Operand types (for instance i8, i32, i64, f32, f64)
1002 are defined for all targets in ``include/llvm/Target/Target.td``, and are
1003 available in each Target's OpTypes enum. Also, only named Operand types appear
1004 in the enumeration: anonymous types are ignored.
1005 For example, the X86 backend defines ``brtarget`` and ``brtarget8``, both
1006 instances of the TableGen ``Operand`` class, which represent branch target
1009 .. code-block:: text
1011 def brtarget : Operand<OtherVT>;
1012 def brtarget8 : Operand<OtherVT>;
1028 OPERAND_TYPE_LIST_END
1029 } // End namespace OpTypes
1030 } // End namespace X86
1032 In typical TableGen fashion, to use the enum, you will need to define a
1037 #define GET_INSTRINFO_OPERAND_TYPES_ENUM // For OpTypes enum
1038 #include "XXXGenInstrInfo.inc"
1041 Instruction Scheduling
1042 ----------------------
1044 Instruction itineraries can be queried using MCDesc::getSchedClass(). The
1045 value can be named by an enumeration in llvm::XXX::Sched namespace generated
1046 by TableGen in XXXGenInstrInfo.inc. The name of the schedule classes are
1047 the same as provided in XXXSchedule.td plus a default NoItinerary class.
1049 The schedule models are generated by TableGen by the SubtargetEmitter,
1050 using the ``CodeGenSchedModels`` class. This is distinct from the itinerary
1051 method of specifying machine resource use. The tool ``utils/schedcover.py``
1052 can be used to determine which instructions have been covered by the
1053 schedule model description and which haven't. The first step is to use the
1054 instructions below to create an output file. Then run ``schedcover.py`` on the
1057 .. code-block:: shell
1059 $ <src>/utils/schedcover.py <build>/lib/Target/AArch64/tblGenSubtarget.with
1060 instruction, default, CortexA53Model, CortexA57Model, CycloneModel, ExynosM3Model, FalkorModel, KryoModel, ThunderX2T99Model, ThunderXT8XModel
1061 ABSv16i8, WriteV, , , CyWriteV3, M3WriteNMISC1, FalkorWr_2VXVY_2cyc, KryoWrite_2cyc_XY_XY_150ln, ,
1062 ABSv1i64, WriteV, , , CyWriteV3, M3WriteNMISC1, FalkorWr_1VXVY_2cyc, KryoWrite_2cyc_XY_noRSV_67ln, ,
1065 To capture the debug output from generating a schedule model, change to the
1066 appropriate target directory and use the following command:
1067 command with the ``subtarget-emitter`` debug option:
1069 .. code-block:: shell
1071 $ <build>/bin/llvm-tblgen -debug-only=subtarget-emitter -gen-subtarget \
1072 -I <src>/lib/Target/<target> -I <src>/include \
1073 -I <src>/lib/Target <src>/lib/Target/<target>/<target>.td \
1074 -o <build>/lib/Target/<target>/<target>GenSubtargetInfo.inc.tmp \
1075 > tblGenSubtarget.dbg 2>&1
1077 Where ``<build>`` is the build directory, ``src`` is the source directory,
1078 and ``<target>`` is the name of the target.
1079 To double check that the above command is what is needed, one can capture the
1080 exact TableGen command from a build by using:
1082 .. code-block:: shell
1084 $ VERBOSE=1 make ...
1086 and search for ``llvm-tblgen`` commands in the output.
1089 Instruction Relation Mapping
1090 ----------------------------
1092 This TableGen feature is used to relate instructions with each other. It is
1093 particularly useful when you have multiple instruction formats and need to
1094 switch between them after instruction selection. This entire feature is driven
1095 by relation models which can be defined in ``XXXInstrInfo.td`` files
1096 according to the target-specific instruction set. Relation models are defined
1097 using ``InstrMapping`` class as a base. TableGen parses all the models
1098 and generates instruction relation maps using the specified information.
1099 Relation maps are emitted as tables in the ``XXXGenInstrInfo.inc`` file
1100 along with the functions to query them. For the detailed information on how to
1101 use this feature, please refer to :doc:`HowToUseInstrMappings`.
1103 Implement a subclass of ``TargetInstrInfo``
1104 -------------------------------------------
1106 The final step is to hand code portions of ``XXXInstrInfo``, which implements
1107 the interface described in ``TargetInstrInfo.h`` (see :ref:`TargetInstrInfo`).
1108 These functions return ``0`` or a Boolean or they assert, unless overridden.
1109 Here's a list of functions that are overridden for the SPARC implementation in
1110 ``SparcInstrInfo.cpp``:
1112 * ``isLoadFromStackSlot`` --- If the specified machine instruction is a direct
1113 load from a stack slot, return the register number of the destination and the
1114 ``FrameIndex`` of the stack slot.
1116 * ``isStoreToStackSlot`` --- If the specified machine instruction is a direct
1117 store to a stack slot, return the register number of the destination and the
1118 ``FrameIndex`` of the stack slot.
1120 * ``copyPhysReg`` --- Copy values between a pair of physical registers.
1122 * ``storeRegToStackSlot`` --- Store a register value to a stack slot.
1124 * ``loadRegFromStackSlot`` --- Load a register value from a stack slot.
1126 * ``storeRegToAddr`` --- Store a register value to memory.
1128 * ``loadRegFromAddr`` --- Load a register value from memory.
1130 * ``foldMemoryOperand`` --- Attempt to combine instructions of any load or
1131 store instruction for the specified operand(s).
1133 Branch Folding and If Conversion
1134 --------------------------------
1136 Performance can be improved by combining instructions or by eliminating
1137 instructions that are never reached. The ``analyzeBranch`` method in
1138 ``XXXInstrInfo`` may be implemented to examine conditional instructions and
1139 remove unnecessary instructions. ``analyzeBranch`` looks at the end of a
1140 machine basic block (MBB) for opportunities for improvement, such as branch
1141 folding and if conversion. The ``BranchFolder`` and ``IfConverter`` machine
1142 function passes (see the source files ``BranchFolding.cpp`` and
1143 ``IfConversion.cpp`` in the ``lib/CodeGen`` directory) call ``analyzeBranch``
1144 to improve the control flow graph that represents the instructions.
1146 Several implementations of ``analyzeBranch`` (for ARM, Alpha, and X86) can be
1147 examined as models for your own ``analyzeBranch`` implementation. Since SPARC
1148 does not implement a useful ``analyzeBranch``, the ARM target implementation is
1151 ``analyzeBranch`` returns a Boolean value and takes four parameters:
1153 * ``MachineBasicBlock &MBB`` --- The incoming block to be examined.
1155 * ``MachineBasicBlock *&TBB`` --- A destination block that is returned. For a
1156 conditional branch that evaluates to true, ``TBB`` is the destination.
1158 * ``MachineBasicBlock *&FBB`` --- For a conditional branch that evaluates to
1159 false, ``FBB`` is returned as the destination.
1161 * ``std::vector<MachineOperand> &Cond`` --- List of operands to evaluate a
1162 condition for a conditional branch.
1164 In the simplest case, if a block ends without a branch, then it falls through
1165 to the successor block. No destination blocks are specified for either ``TBB``
1166 or ``FBB``, so both parameters return ``NULL``. The start of the
1167 ``analyzeBranch`` (see code below for the ARM target) shows the function
1168 parameters and the code for the simplest case.
1172 bool ARMInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
1173 MachineBasicBlock *&TBB,
1174 MachineBasicBlock *&FBB,
1175 std::vector<MachineOperand> &Cond) const
1177 MachineBasicBlock::iterator I = MBB.end();
1178 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
1181 If a block ends with a single unconditional branch instruction, then
1182 ``analyzeBranch`` (shown below) should return the destination of that branch in
1183 the ``TBB`` parameter.
1187 if (LastOpc == ARM::B || LastOpc == ARM::tB) {
1188 TBB = LastInst->getOperand(0).getMBB();
1192 If a block ends with two unconditional branches, then the second branch is
1193 never reached. In that situation, as shown below, remove the last branch
1194 instruction and return the penultimate branch in the ``TBB`` parameter.
1198 if ((SecondLastOpc == ARM::B || SecondLastOpc == ARM::tB) &&
1199 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
1200 TBB = SecondLastInst->getOperand(0).getMBB();
1202 I->eraseFromParent();
1206 A block may end with a single conditional branch instruction that falls through
1207 to successor block if the condition evaluates to false. In that case,
1208 ``analyzeBranch`` (shown below) should return the destination of that
1209 conditional branch in the ``TBB`` parameter and a list of operands in the
1210 ``Cond`` parameter to evaluate the condition.
1214 if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc) {
1215 // Block ends with fall-through condbranch.
1216 TBB = LastInst->getOperand(0).getMBB();
1217 Cond.push_back(LastInst->getOperand(1));
1218 Cond.push_back(LastInst->getOperand(2));
1222 If a block ends with both a conditional branch and an ensuing unconditional
1223 branch, then ``analyzeBranch`` (shown below) should return the conditional
1224 branch destination (assuming it corresponds to a conditional evaluation of
1225 "``true``") in the ``TBB`` parameter and the unconditional branch destination
1226 in the ``FBB`` (corresponding to a conditional evaluation of "``false``"). A
1227 list of operands to evaluate the condition should be returned in the ``Cond``
1232 unsigned SecondLastOpc = SecondLastInst->getOpcode();
1234 if ((SecondLastOpc == ARM::Bcc && LastOpc == ARM::B) ||
1235 (SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB)) {
1236 TBB = SecondLastInst->getOperand(0).getMBB();
1237 Cond.push_back(SecondLastInst->getOperand(1));
1238 Cond.push_back(SecondLastInst->getOperand(2));
1239 FBB = LastInst->getOperand(0).getMBB();
1243 For the last two cases (ending with a single conditional branch or ending with
1244 one conditional and one unconditional branch), the operands returned in the
1245 ``Cond`` parameter can be passed to methods of other instructions to create new
1246 branches or perform other operations. An implementation of ``analyzeBranch``
1247 requires the helper methods ``removeBranch`` and ``insertBranch`` to manage
1248 subsequent operations.
1250 ``analyzeBranch`` should return false indicating success in most circumstances.
1251 ``analyzeBranch`` should only return true when the method is stumped about what
1252 to do, for example, if a block has three terminating branches.
1253 ``analyzeBranch`` may return true if it encounters a terminator it cannot
1254 handle, such as an indirect branch.
1256 .. _instruction-selector:
1258 Instruction Selector
1259 ====================
1261 LLVM uses a ``SelectionDAG`` to represent LLVM IR instructions, and nodes of
1262 the ``SelectionDAG`` ideally represent native target instructions. During code
1263 generation, instruction selection passes are performed to convert non-native
1264 DAG instructions into native target-specific instructions. The pass described
1265 in ``XXXISelDAGToDAG.cpp`` is used to match patterns and perform DAG-to-DAG
1266 instruction selection. Optionally, a pass may be defined (in
1267 ``XXXBranchSelector.cpp``) to perform similar DAG-to-DAG operations for branch
1268 instructions. Later, the code in ``XXXISelLowering.cpp`` replaces or removes
1269 operations and data types not supported natively (legalizes) in a
1272 TableGen generates code for instruction selection using the following target
1273 description input files:
1275 * ``XXXInstrInfo.td`` --- Contains definitions of instructions in a
1276 target-specific instruction set, generates ``XXXGenDAGISel.inc``, which is
1277 included in ``XXXISelDAGToDAG.cpp``.
1279 * ``XXXCallingConv.td`` --- Contains the calling and return value conventions
1280 for the target architecture, and it generates ``XXXGenCallingConv.inc``,
1281 which is included in ``XXXISelLowering.cpp``.
1283 The implementation of an instruction selection pass must include a header that
1284 declares the ``FunctionPass`` class or a subclass of ``FunctionPass``. In
1285 ``XXXTargetMachine.cpp``, a Pass Manager (PM) should add each instruction
1286 selection pass into the queue of passes to run.
1288 The LLVM static compiler (``llc``) is an excellent tool for visualizing the
1289 contents of DAGs. To display the ``SelectionDAG`` before or after specific
1290 processing phases, use the command line options for ``llc``, described at
1291 :ref:`SelectionDAG-Process`.
1293 To describe instruction selector behavior, you should add patterns for lowering
1294 LLVM code into a ``SelectionDAG`` as the last parameter of the instruction
1295 definitions in ``XXXInstrInfo.td``. For example, in ``SparcInstrInfo.td``,
1296 this entry defines a register store operation, and the last parameter describes
1297 a pattern with the store DAG operator.
1299 .. code-block:: text
1301 def STrr : F3_1< 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src),
1302 "st $src, [$addr]", [(store i32:$src, ADDRrr:$addr)]>;
1304 ``ADDRrr`` is a memory mode that is also defined in ``SparcInstrInfo.td``:
1306 .. code-block:: text
1308 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
1310 The definition of ``ADDRrr`` refers to ``SelectADDRrr``, which is a function
1311 defined in an implementation of the Instructor Selector (such as
1312 ``SparcISelDAGToDAG.cpp``).
1314 In ``lib/Target/TargetSelectionDAG.td``, the DAG operator for store is defined
1317 .. code-block:: text
1319 def store : PatFrag<(ops node:$val, node:$ptr),
1320 (unindexedstore node:$val, node:$ptr)> {
1322 let IsTruncStore = false;
1325 ``XXXInstrInfo.td`` also generates (in ``XXXGenDAGISel.inc``) the
1326 ``SelectCode`` method that is used to call the appropriate processing method
1327 for an instruction. In this example, ``SelectCode`` calls ``Select_ISD_STORE``
1328 for the ``ISD::STORE`` opcode.
1332 SDNode *SelectCode(SDValue N) {
1334 MVT::ValueType NVT = N.getNode()->getValueType(0);
1335 switch (N.getOpcode()) {
1339 return Select_ISD_STORE(N);
1346 The pattern for ``STrr`` is matched, so elsewhere in ``XXXGenDAGISel.inc``,
1347 code for ``STrr`` is created for ``Select_ISD_STORE``. The ``Emit_22`` method
1348 is also generated in ``XXXGenDAGISel.inc`` to complete the processing of this
1353 SDNode *Select_ISD_STORE(const SDValue &N) {
1354 SDValue Chain = N.getOperand(0);
1355 if (Predicate_store(N.getNode())) {
1356 SDValue N1 = N.getOperand(1);
1357 SDValue N2 = N.getOperand(2);
1361 // Pattern: (st:void i32:i32:$src,
1362 // ADDRrr:i32:$addr)<<P:Predicate_store>>
1363 // Emits: (STrr:void ADDRrr:i32:$addr, IntRegs:i32:$src)
1364 // Pattern complexity = 13 cost = 1 size = 0
1365 if (SelectADDRrr(N, N2, CPTmp0, CPTmp1) &&
1366 N1.getNode()->getValueType(0) == MVT::i32 &&
1367 N2.getNode()->getValueType(0) == MVT::i32) {
1368 return Emit_22(N, SP::STrr, CPTmp0, CPTmp1);
1372 The SelectionDAG Legalize Phase
1373 -------------------------------
1375 The Legalize phase converts a DAG to use types and operations that are natively
1376 supported by the target. For natively unsupported types and operations, you
1377 need to add code to the target-specific ``XXXTargetLowering`` implementation to
1378 convert unsupported types and operations to supported ones.
1380 In the constructor for the ``XXXTargetLowering`` class, first use the
1381 ``addRegisterClass`` method to specify which types are supported and which
1382 register classes are associated with them. The code for the register classes
1383 are generated by TableGen from ``XXXRegisterInfo.td`` and placed in
1384 ``XXXGenRegisterInfo.h.inc``. For example, the implementation of the
1385 constructor for the SparcTargetLowering class (in ``SparcISelLowering.cpp``)
1386 starts with the following code:
1390 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
1391 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
1392 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
1394 You should examine the node types in the ``ISD`` namespace
1395 (``include/llvm/CodeGen/SelectionDAGNodes.h``) and determine which operations
1396 the target natively supports. For operations that do **not** have native
1397 support, add a callback to the constructor for the ``XXXTargetLowering`` class,
1398 so the instruction selection process knows what to do. The ``TargetLowering``
1399 class callback methods (declared in ``llvm/Target/TargetLowering.h``) are:
1401 * ``setOperationAction`` --- General operation.
1402 * ``setLoadExtAction`` --- Load with extension.
1403 * ``setTruncStoreAction`` --- Truncating store.
1404 * ``setIndexedLoadAction`` --- Indexed load.
1405 * ``setIndexedStoreAction`` --- Indexed store.
1406 * ``setConvertAction`` --- Type conversion.
1407 * ``setCondCodeAction`` --- Support for a given condition code.
1409 Note: on older releases, ``setLoadXAction`` is used instead of
1410 ``setLoadExtAction``. Also, on older releases, ``setCondCodeAction`` may not
1411 be supported. Examine your release to see what methods are specifically
1414 These callbacks are used to determine that an operation does or does not work
1415 with a specified type (or types). And in all cases, the third parameter is a
1416 ``LegalAction`` type enum value: ``Promote``, ``Expand``, ``Custom``, or
1417 ``Legal``. ``SparcISelLowering.cpp`` contains examples of all four
1418 ``LegalAction`` values.
1423 For an operation without native support for a given type, the specified type
1424 may be promoted to a larger type that is supported. For example, SPARC does
1425 not support a sign-extending load for Boolean values (``i1`` type), so in
1426 ``SparcISelLowering.cpp`` the third parameter below, ``Promote``, changes
1427 ``i1`` type values to a large type before loading.
1431 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
1436 For a type without native support, a value may need to be broken down further,
1437 rather than promoted. For an operation without native support, a combination
1438 of other operations may be used to similar effect. In SPARC, the
1439 floating-point sine and cosine trig operations are supported by expansion to
1440 other operations, as indicated by the third parameter, ``Expand``, to
1441 ``setOperationAction``:
1445 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1446 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1451 For some operations, simple type promotion or operation expansion may be
1452 insufficient. In some cases, a special intrinsic function must be implemented.
1454 For example, a constant value may require special treatment, or an operation
1455 may require spilling and restoring registers in the stack and working with
1456 register allocators.
1458 As seen in ``SparcISelLowering.cpp`` code below, to perform a type conversion
1459 from a floating point value to a signed integer, first the
1460 ``setOperationAction`` should be called with ``Custom`` as the third parameter:
1464 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1466 In the ``LowerOperation`` method, for each ``Custom`` operation, a case
1467 statement should be added to indicate what function to call. In the following
1468 code, an ``FP_TO_SINT`` opcode will call the ``LowerFP_TO_SINT`` method:
1472 SDValue SparcTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
1473 switch (Op.getOpcode()) {
1474 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
1479 Finally, the ``LowerFP_TO_SINT`` method is implemented, using an FP register to
1480 convert the floating-point value to an integer.
1484 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
1485 assert(Op.getValueType() == MVT::i32);
1486 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
1487 return DAG.getNode(ISD::BITCAST, MVT::i32, Op);
1493 The ``Legal`` ``LegalizeAction`` enum value simply indicates that an operation
1494 **is** natively supported. ``Legal`` represents the default condition, so it
1495 is rarely used. In ``SparcISelLowering.cpp``, the action for ``CTPOP`` (an
1496 operation to count the bits set in an integer) is natively supported only for
1497 SPARC v9. The following code enables the ``Expand`` conversion technique for
1498 non-v9 SPARC implementations.
1502 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1504 if (TM.getSubtarget<SparcSubtarget>().isV9())
1505 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
1510 To support target-specific calling conventions, ``XXXGenCallingConv.td`` uses
1511 interfaces (such as ``CCIfType`` and ``CCAssignToReg``) that are defined in
1512 ``lib/Target/TargetCallingConv.td``. TableGen can take the target descriptor
1513 file ``XXXGenCallingConv.td`` and generate the header file
1514 ``XXXGenCallingConv.inc``, which is typically included in
1515 ``XXXISelLowering.cpp``. You can use the interfaces in
1516 ``TargetCallingConv.td`` to specify:
1518 * The order of parameter allocation.
1520 * Where parameters and return values are placed (that is, on the stack or in
1523 * Which registers may be used.
1525 * Whether the caller or callee unwinds the stack.
1527 The following example demonstrates the use of the ``CCIfType`` and
1528 ``CCAssignToReg`` interfaces. If the ``CCIfType`` predicate is true (that is,
1529 if the current argument is of type ``f32`` or ``f64``), then the action is
1530 performed. In this case, the ``CCAssignToReg`` action assigns the argument
1531 value to the first available register: either ``R0`` or ``R1``.
1533 .. code-block:: text
1535 CCIfType<[f32,f64], CCAssignToReg<[R0, R1]>>
1537 ``SparcCallingConv.td`` contains definitions for a target-specific return-value
1538 calling convention (``RetCC_Sparc32``) and a basic 32-bit C calling convention
1539 (``CC_Sparc32``). The definition of ``RetCC_Sparc32`` (shown below) indicates
1540 which registers are used for specified scalar return types. A single-precision
1541 float is returned to register ``F0``, and a double-precision float goes to
1542 register ``D0``. A 32-bit integer is returned in register ``I0`` or ``I1``.
1544 .. code-block:: text
1546 def RetCC_Sparc32 : CallingConv<[
1547 CCIfType<[i32], CCAssignToReg<[I0, I1]>>,
1548 CCIfType<[f32], CCAssignToReg<[F0]>>,
1549 CCIfType<[f64], CCAssignToReg<[D0]>>
1552 The definition of ``CC_Sparc32`` in ``SparcCallingConv.td`` introduces
1553 ``CCAssignToStack``, which assigns the value to a stack slot with the specified
1554 size and alignment. In the example below, the first parameter, 4, indicates
1555 the size of the slot, and the second parameter, also 4, indicates the stack
1556 alignment along 4-byte units. (Special cases: if size is zero, then the ABI
1557 size is used; if alignment is zero, then the ABI alignment is used.)
1559 .. code-block:: text
1561 def CC_Sparc32 : CallingConv<[
1562 // All arguments get passed in integer registers if there is space.
1563 CCIfType<[i32, f32, f64], CCAssignToReg<[I0, I1, I2, I3, I4, I5]>>,
1564 CCAssignToStack<4, 4>
1567 ``CCDelegateTo`` is another commonly used interface, which tries to find a
1568 specified sub-calling convention, and, if a match is found, it is invoked. In
1569 the following example (in ``X86CallingConv.td``), the definition of
1570 ``RetCC_X86_32_C`` ends with ``CCDelegateTo``. After the current value is
1571 assigned to the register ``ST0`` or ``ST1``, the ``RetCC_X86Common`` is
1574 .. code-block:: text
1576 def RetCC_X86_32_C : CallingConv<[
1577 CCIfType<[f32], CCAssignToReg<[ST0, ST1]>>,
1578 CCIfType<[f64], CCAssignToReg<[ST0, ST1]>>,
1579 CCDelegateTo<RetCC_X86Common>
1582 ``CCIfCC`` is an interface that attempts to match the given name to the current
1583 calling convention. If the name identifies the current calling convention,
1584 then a specified action is invoked. In the following example (in
1585 ``X86CallingConv.td``), if the ``Fast`` calling convention is in use, then
1586 ``RetCC_X86_32_Fast`` is invoked. If the ``SSECall`` calling convention is in
1587 use, then ``RetCC_X86_32_SSE`` is invoked.
1589 .. code-block:: text
1591 def RetCC_X86_32 : CallingConv<[
1592 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
1593 CCIfCC<"CallingConv::X86_SSECall", CCDelegateTo<RetCC_X86_32_SSE>>,
1594 CCDelegateTo<RetCC_X86_32_C>
1597 ``CCAssignToRegAndStack`` is the same as ``CCAssignToReg``, but also allocates
1598 a stack slot, when some register is used. Basically, it works like:
1599 ``CCIf<CCAssignToReg<regList>, CCAssignToStack<size, align>>``.
1601 .. code-block:: text
1603 class CCAssignToRegAndStack<list<Register> regList, int size, int align>
1604 : CCAssignToReg<regList> {
1609 Other calling convention interfaces include:
1611 * ``CCIf <predicate, action>`` --- If the predicate matches, apply the action.
1613 * ``CCIfInReg <action>`` --- If the argument is marked with the "``inreg``"
1614 attribute, then apply the action.
1616 * ``CCIfNest <action>`` --- If the argument is marked with the "``nest``"
1617 attribute, then apply the action.
1619 * ``CCIfNotVarArg <action>`` --- If the current function does not take a
1620 variable number of arguments, apply the action.
1622 * ``CCAssignToRegWithShadow <registerList, shadowList>`` --- similar to
1623 ``CCAssignToReg``, but with a shadow list of registers.
1625 * ``CCPassByVal <size, align>`` --- Assign value to a stack slot with the
1626 minimum specified size and alignment.
1628 * ``CCPromoteToType <type>`` --- Promote the current value to the specified
1631 * ``CallingConv <[actions]>`` --- Define each calling convention that is
1637 During the code emission stage, the code generator may utilize an LLVM pass to
1638 produce assembly output. To do this, you want to implement the code for a
1639 printer that converts LLVM IR to a GAS-format assembly language for your target
1640 machine, using the following steps:
1642 * Define all the assembly strings for your target, adding them to the
1643 instructions defined in the ``XXXInstrInfo.td`` file. (See
1644 :ref:`instruction-set`.) TableGen will produce an output file
1645 (``XXXGenAsmWriter.inc``) with an implementation of the ``printInstruction``
1646 method for the ``XXXAsmPrinter`` class.
1648 * Write ``XXXTargetAsmInfo.h``, which contains the bare-bones declaration of
1649 the ``XXXTargetAsmInfo`` class (a subclass of ``TargetAsmInfo``).
1651 * Write ``XXXTargetAsmInfo.cpp``, which contains target-specific values for
1652 ``TargetAsmInfo`` properties and sometimes new implementations for methods.
1654 * Write ``XXXAsmPrinter.cpp``, which implements the ``AsmPrinter`` class that
1655 performs the LLVM-to-assembly conversion.
1657 The code in ``XXXTargetAsmInfo.h`` is usually a trivial declaration of the
1658 ``XXXTargetAsmInfo`` class for use in ``XXXTargetAsmInfo.cpp``. Similarly,
1659 ``XXXTargetAsmInfo.cpp`` usually has a few declarations of ``XXXTargetAsmInfo``
1660 replacement values that override the default values in ``TargetAsmInfo.cpp``.
1661 For example in ``SparcTargetAsmInfo.cpp``:
1665 SparcTargetAsmInfo::SparcTargetAsmInfo(const SparcTargetMachine &TM) {
1666 Data16bitsDirective = "\t.half\t";
1667 Data32bitsDirective = "\t.word\t";
1668 Data64bitsDirective = 0; // .xword is only supported by V9.
1669 ZeroDirective = "\t.skip\t";
1670 CommentString = "!";
1671 ConstantPoolSection = "\t.section \".rodata\",#alloc\n";
1674 The X86 assembly printer implementation (``X86TargetAsmInfo``) is an example
1675 where the target specific ``TargetAsmInfo`` class uses an overridden methods:
1676 ``ExpandInlineAsm``.
1678 A target-specific implementation of ``AsmPrinter`` is written in
1679 ``XXXAsmPrinter.cpp``, which implements the ``AsmPrinter`` class that converts
1680 the LLVM to printable assembly. The implementation must include the following
1681 headers that have declarations for the ``AsmPrinter`` and
1682 ``MachineFunctionPass`` classes. The ``MachineFunctionPass`` is a subclass of
1687 #include "llvm/CodeGen/AsmPrinter.h"
1688 #include "llvm/CodeGen/MachineFunctionPass.h"
1690 As a ``FunctionPass``, ``AsmPrinter`` first calls ``doInitialization`` to set
1691 up the ``AsmPrinter``. In ``SparcAsmPrinter``, a ``Mangler`` object is
1692 instantiated to process variable names.
1694 In ``XXXAsmPrinter.cpp``, the ``runOnMachineFunction`` method (declared in
1695 ``MachineFunctionPass``) must be implemented for ``XXXAsmPrinter``. In
1696 ``MachineFunctionPass``, the ``runOnFunction`` method invokes
1697 ``runOnMachineFunction``. Target-specific implementations of
1698 ``runOnMachineFunction`` differ, but generally do the following to process each
1701 * Call ``SetupMachineFunction`` to perform initialization.
1703 * Call ``EmitConstantPool`` to print out (to the output stream) constants which
1704 have been spilled to memory.
1706 * Call ``EmitJumpTableInfo`` to print out jump tables used by the current
1709 * Print out the label for the current function.
1711 * Print out the code for the function, including basic block labels and the
1712 assembly for the instruction (using ``printInstruction``)
1714 The ``XXXAsmPrinter`` implementation must also include the code generated by
1715 TableGen that is output in the ``XXXGenAsmWriter.inc`` file. The code in
1716 ``XXXGenAsmWriter.inc`` contains an implementation of the ``printInstruction``
1717 method that may call these methods:
1720 * ``printMemOperand``
1721 * ``printCCOperand`` (for conditional statements)
1722 * ``printDataDirective``
1724 * ``printImplicitDef``
1725 * ``printInlineAsm``
1727 The implementations of ``printDeclare``, ``printImplicitDef``,
1728 ``printInlineAsm``, and ``printLabel`` in ``AsmPrinter.cpp`` are generally
1729 adequate for printing assembly and do not need to be overridden.
1731 The ``printOperand`` method is implemented with a long ``switch``/``case``
1732 statement for the type of operand: register, immediate, basic block, external
1733 symbol, global address, constant pool index, or jump table index. For an
1734 instruction with a memory address operand, the ``printMemOperand`` method
1735 should be implemented to generate the proper output. Similarly,
1736 ``printCCOperand`` should be used to print a conditional operand.
1738 ``doFinalization`` should be overridden in ``XXXAsmPrinter``, and it should be
1739 called to shut down the assembly printer. During ``doFinalization``, global
1740 variables and constants are printed to output.
1745 Subtarget support is used to inform the code generation process of instruction
1746 set variations for a given chip set. For example, the LLVM SPARC
1747 implementation provided covers three major versions of the SPARC microprocessor
1748 architecture: Version 8 (V8, which is a 32-bit architecture), Version 9 (V9, a
1749 64-bit architecture), and the UltraSPARC architecture. V8 has 16
1750 double-precision floating-point registers that are also usable as either 32
1751 single-precision or 8 quad-precision registers. V8 is also purely big-endian.
1752 V9 has 32 double-precision floating-point registers that are also usable as 16
1753 quad-precision registers, but cannot be used as single-precision registers.
1754 The UltraSPARC architecture combines V9 with UltraSPARC Visual Instruction Set
1757 If subtarget support is needed, you should implement a target-specific
1758 ``XXXSubtarget`` class for your architecture. This class should process the
1759 command-line options ``-mcpu=`` and ``-mattr=``.
1761 TableGen uses definitions in the ``Target.td`` and ``Sparc.td`` files to
1762 generate code in ``SparcGenSubtarget.inc``. In ``Target.td``, shown below, the
1763 ``SubtargetFeature`` interface is defined. The first 4 string parameters of
1764 the ``SubtargetFeature`` interface are a feature name, an attribute set by the
1765 feature, the value of the attribute, and a description of the feature. (The
1766 fifth parameter is a list of features whose presence is implied, and its
1767 default value is an empty array.)
1769 .. code-block:: text
1771 class SubtargetFeature<string n, string a, string v, string d,
1772 list<SubtargetFeature> i = []> {
1774 string Attribute = a;
1777 list<SubtargetFeature> Implies = i;
1780 In the ``Sparc.td`` file, the ``SubtargetFeature`` is used to define the
1783 .. code-block:: text
1785 def FeatureV9 : SubtargetFeature<"v9", "IsV9", "true",
1786 "Enable SPARC-V9 instructions">;
1787 def FeatureV8Deprecated : SubtargetFeature<"deprecated-v8",
1788 "UseV8DeprecatedInsts", "true",
1789 "Enable deprecated V8 instructions in V9 mode">;
1790 def FeatureVIS : SubtargetFeature<"vis", "IsVIS", "true",
1791 "Enable UltraSPARC Visual Instruction Set extensions">;
1793 Elsewhere in ``Sparc.td``, the ``Proc`` class is defined and then is used to
1794 define particular SPARC processor subtypes that may have the previously
1797 .. code-block:: text
1799 class Proc<string Name, list<SubtargetFeature> Features>
1800 : Processor<Name, NoItineraries, Features>;
1802 def : Proc<"generic", []>;
1803 def : Proc<"v8", []>;
1804 def : Proc<"supersparc", []>;
1805 def : Proc<"sparclite", []>;
1806 def : Proc<"f934", []>;
1807 def : Proc<"hypersparc", []>;
1808 def : Proc<"sparclite86x", []>;
1809 def : Proc<"sparclet", []>;
1810 def : Proc<"tsc701", []>;
1811 def : Proc<"v9", [FeatureV9]>;
1812 def : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated]>;
1813 def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated]>;
1814 def : Proc<"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
1816 From ``Target.td`` and ``Sparc.td`` files, the resulting
1817 ``SparcGenSubtarget.inc`` specifies enum values to identify the features,
1818 arrays of constants to represent the CPU features and CPU subtypes, and the
1819 ``ParseSubtargetFeatures`` method that parses the features string that sets
1820 specified subtarget options. The generated ``SparcGenSubtarget.inc`` file
1821 should be included in the ``SparcSubtarget.cpp``. The target-specific
1822 implementation of the ``XXXSubtarget`` method should follow this pseudocode:
1826 XXXSubtarget::XXXSubtarget(const Module &M, const std::string &FS) {
1827 // Set the default features
1828 // Determine default and user specified characteristics of the CPU
1829 // Call ParseSubtargetFeatures(FS, CPU) to parse the features string
1830 // Perform any additional operations
1836 The implementation of a target machine optionally includes a Just-In-Time (JIT)
1837 code generator that emits machine code and auxiliary structures as binary
1838 output that can be written directly to memory. To do this, implement JIT code
1839 generation by performing the following steps:
1841 * Write an ``XXXCodeEmitter.cpp`` file that contains a machine function pass
1842 that transforms target-machine instructions into relocatable machine
1845 * Write an ``XXXJITInfo.cpp`` file that implements the JIT interfaces for
1846 target-specific code-generation activities, such as emitting machine code and
1849 * Modify ``XXXTargetMachine`` so that it provides a ``TargetJITInfo`` object
1850 through its ``getJITInfo`` method.
1852 There are several different approaches to writing the JIT support code. For
1853 instance, TableGen and target descriptor files may be used for creating a JIT
1854 code generator, but are not mandatory. For the Alpha and PowerPC target
1855 machines, TableGen is used to generate ``XXXGenCodeEmitter.inc``, which
1856 contains the binary coding of machine instructions and the
1857 ``getBinaryCodeForInstr`` method to access those codes. Other JIT
1858 implementations do not.
1860 Both ``XXXJITInfo.cpp`` and ``XXXCodeEmitter.cpp`` must include the
1861 ``llvm/CodeGen/MachineCodeEmitter.h`` header file that defines the
1862 ``MachineCodeEmitter`` class containing code for several callback functions
1863 that write data (in bytes, words, strings, etc.) to the output stream.
1865 Machine Code Emitter
1866 --------------------
1868 In ``XXXCodeEmitter.cpp``, a target-specific of the ``Emitter`` class is
1869 implemented as a function pass (subclass of ``MachineFunctionPass``). The
1870 target-specific implementation of ``runOnMachineFunction`` (invoked by
1871 ``runOnFunction`` in ``MachineFunctionPass``) iterates through the
1872 ``MachineBasicBlock`` calls ``emitInstruction`` to process each instruction and
1873 emit binary code. ``emitInstruction`` is largely implemented with case
1874 statements on the instruction types defined in ``XXXInstrInfo.h``. For
1875 example, in ``X86CodeEmitter.cpp``, the ``emitInstruction`` method is built
1876 around the following ``switch``/``case`` statements:
1880 switch (Desc->TSFlags & X86::FormMask) {
1881 case X86II::Pseudo: // for not yet implemented instructions
1882 ... // or pseudo-instructions
1884 case X86II::RawFrm: // for instructions with a fixed opcode value
1887 case X86II::AddRegFrm: // for instructions that have one register operand
1888 ... // added to their opcode
1890 case X86II::MRMDestReg:// for instructions that use the Mod/RM byte
1891 ... // to specify a destination (register)
1893 case X86II::MRMDestMem:// for instructions that use the Mod/RM byte
1894 ... // to specify a destination (memory)
1896 case X86II::MRMSrcReg: // for instructions that use the Mod/RM byte
1897 ... // to specify a source (register)
1899 case X86II::MRMSrcMem: // for instructions that use the Mod/RM byte
1900 ... // to specify a source (memory)
1902 case X86II::MRM0r: case X86II::MRM1r: // for instructions that operate on
1903 case X86II::MRM2r: case X86II::MRM3r: // a REGISTER r/m operand and
1904 case X86II::MRM4r: case X86II::MRM5r: // use the Mod/RM byte and a field
1905 case X86II::MRM6r: case X86II::MRM7r: // to hold extended opcode data
1908 case X86II::MRM0m: case X86II::MRM1m: // for instructions that operate on
1909 case X86II::MRM2m: case X86II::MRM3m: // a MEMORY r/m operand and
1910 case X86II::MRM4m: case X86II::MRM5m: // use the Mod/RM byte and a field
1911 case X86II::MRM6m: case X86II::MRM7m: // to hold extended opcode data
1914 case X86II::MRMInitReg: // for instructions whose source and
1915 ... // destination are the same register
1919 The implementations of these case statements often first emit the opcode and
1920 then get the operand(s). Then depending upon the operand, helper methods may
1921 be called to process the operand(s). For example, in ``X86CodeEmitter.cpp``,
1922 for the ``X86II::AddRegFrm`` case, the first data emitted (by ``emitByte``) is
1923 the opcode added to the register operand. Then an object representing the
1924 machine operand, ``MO1``, is extracted. The helper methods such as
1925 ``isImmediate``, ``isGlobalAddress``, ``isExternalSymbol``,
1926 ``isConstantPoolIndex``, and ``isJumpTableIndex`` determine the operand type.
1927 (``X86CodeEmitter.cpp`` also has private methods such as ``emitConstant``,
1928 ``emitGlobalAddress``, ``emitExternalSymbolAddress``, ``emitConstPoolAddress``,
1929 and ``emitJumpTableAddress`` that emit the data into the output stream.)
1933 case X86II::AddRegFrm:
1934 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
1936 if (CurOp != NumOps) {
1937 const MachineOperand &MO1 = MI.getOperand(CurOp++);
1938 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
1939 if (MO1.isImmediate())
1940 emitConstant(MO1.getImm(), Size);
1942 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
1943 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
1944 if (Opcode == X86::MOV64ri)
1945 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
1946 if (MO1.isGlobalAddress()) {
1947 bool NeedStub = isa<Function>(MO1.getGlobal());
1948 bool isLazy = gvNeedsLazyPtr(MO1.getGlobal());
1949 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
1951 } else if (MO1.isExternalSymbol())
1952 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
1953 else if (MO1.isConstantPoolIndex())
1954 emitConstPoolAddress(MO1.getIndex(), rt);
1955 else if (MO1.isJumpTableIndex())
1956 emitJumpTableAddress(MO1.getIndex(), rt);
1961 In the previous example, ``XXXCodeEmitter.cpp`` uses the variable ``rt``, which
1962 is a ``RelocationType`` enum that may be used to relocate addresses (for
1963 example, a global address with a PIC base offset). The ``RelocationType`` enum
1964 for that target is defined in the short target-specific ``XXXRelocations.h``
1965 file. The ``RelocationType`` is used by the ``relocate`` method defined in
1966 ``XXXJITInfo.cpp`` to rewrite addresses for referenced global symbols.
1968 For example, ``X86Relocations.h`` specifies the following relocation types for
1969 the X86 addresses. In all four cases, the relocated value is added to the
1970 value already in memory. For ``reloc_pcrel_word`` and ``reloc_picrel_word``,
1971 there is an additional initial adjustment.
1975 enum RelocationType {
1976 reloc_pcrel_word = 0, // add reloc value after adjusting for the PC loc
1977 reloc_picrel_word = 1, // add reloc value after adjusting for the PIC base
1978 reloc_absolute_word = 2, // absolute relocation; no additional adjustment
1979 reloc_absolute_dword = 3 // absolute relocation; no additional adjustment
1985 ``XXXJITInfo.cpp`` implements the JIT interfaces for target-specific
1986 code-generation activities, such as emitting machine code and stubs. At
1987 minimum, a target-specific version of ``XXXJITInfo`` implements the following:
1989 * ``getLazyResolverFunction`` --- Initializes the JIT, gives the target a
1990 function that is used for compilation.
1992 * ``emitFunctionStub`` --- Returns a native function with a specified address
1993 for a callback function.
1995 * ``relocate`` --- Changes the addresses of referenced globals, based on
1998 * Callback function that are wrappers to a function stub that is used when the
1999 real target is not initially known.
2001 ``getLazyResolverFunction`` is generally trivial to implement. It makes the
2002 incoming parameter as the global ``JITCompilerFunction`` and returns the
2003 callback function that will be used a function wrapper. For the Alpha target
2004 (in ``AlphaJITInfo.cpp``), the ``getLazyResolverFunction`` implementation is
2009 TargetJITInfo::LazyResolverFn AlphaJITInfo::getLazyResolverFunction(
2011 JITCompilerFunction = F;
2012 return AlphaCompilationCallback;
2015 For the X86 target, the ``getLazyResolverFunction`` implementation is a little
2016 more complicated, because it returns a different callback function for
2017 processors with SSE instructions and XMM registers.
2019 The callback function initially saves and later restores the callee register
2020 values, incoming arguments, and frame and return address. The callback
2021 function needs low-level access to the registers or stack, so it is typically
2022 implemented with assembler.