| blob | ca0d27b25b62c86fbf4ef4d1e173b7268eddffd0 |
1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2 ; RUN: opt -S -mtriple=amdgcn-- -mcpu=tahiti -amdgpu-codegenprepare %s | FileCheck -check-prefix=SI %s
3 ; RUN: opt -S -mtriple=amdgcn-- -mcpu=fiji -amdgpu-codegenprepare %s | FileCheck -check-prefix=VI %s
4 ; RUN: opt -S -mtriple=amdgcn-- -mcpu=fiji -amdgpu-codegenprepare-mul24=0 -amdgpu-codegenprepare %s | FileCheck -check-prefix=DISABLED %s
6 define i16 @mul_i16(i16 %lhs, i16 %rhs) {
7 ; SI-LABEL: @mul_i16(
8 ; SI-NEXT: [[TMP1:%.*]] = zext i16 [[LHS:%.*]] to i32
9 ; SI-NEXT: [[TMP2:%.*]] = zext i16 [[RHS:%.*]] to i32
10 ; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]])
11 ; SI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i16
12 ; SI-NEXT: ret i16 [[MUL]]
13 ;
14 ; VI-LABEL: @mul_i16(
15 ; VI-NEXT: [[MUL:%.*]] = mul i16 [[LHS:%.*]], [[RHS:%.*]]
16 ; VI-NEXT: ret i16 [[MUL]]
17 ;
18 ; DISABLED-LABEL: @mul_i16(
19 ; DISABLED-NEXT: [[MUL:%.*]] = mul i16 [[LHS:%.*]], [[RHS:%.*]]
20 ; DISABLED-NEXT: ret i16 [[MUL]]
21 ;
22 %mul = mul i16 %lhs, %rhs
23 ret i16 %mul
24 }
26 define i32 @smul24_i32(i32 %lhs, i32 %rhs) {
27 ; SI-LABEL: @smul24_i32(
28 ; SI-NEXT: [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 8
29 ; SI-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 8
30 ; SI-NEXT: [[SHL_RHS:%.*]] = shl i32 [[RHS:%.*]], 8
31 ; SI-NEXT: [[RHS24:%.*]] = ashr i32 [[SHL_RHS]], 8
32 ; SI-NEXT: [[MUL:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[LHS24]], i32 [[RHS24]])
33 ; SI-NEXT: ret i32 [[MUL]]
34 ;
35 ; VI-LABEL: @smul24_i32(
36 ; VI-NEXT: [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 8
37 ; VI-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 8
38 ; VI-NEXT: [[SHL_RHS:%.*]] = shl i32 [[RHS:%.*]], 8
39 ; VI-NEXT: [[RHS24:%.*]] = ashr i32 [[SHL_RHS]], 8
40 ; VI-NEXT: [[MUL:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[LHS24]], i32 [[RHS24]])
41 ; VI-NEXT: ret i32 [[MUL]]
42 ;
43 ; DISABLED-LABEL: @smul24_i32(
44 ; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 8
45 ; DISABLED-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 8
46 ; DISABLED-NEXT: [[SHL_RHS:%.*]] = shl i32 [[RHS:%.*]], 8
47 ; DISABLED-NEXT: [[RHS24:%.*]] = ashr i32 [[SHL_RHS]], 8
48 ; DISABLED-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
49 ; DISABLED-NEXT: ret i32 [[MUL]]
50 ;
51 %shl.lhs = shl i32 %lhs, 8
52 %lhs24 = ashr i32 %shl.lhs, 8
53 %shl.rhs = shl i32 %rhs, 8
54 %rhs24 = ashr i32 %shl.rhs, 8
55 %mul = mul i32 %lhs24, %rhs24
56 ret i32 %mul
57 }
59 define <2 x i32> @smul24_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
60 ; SI-LABEL: @smul24_v2i32(
61 ; SI-NEXT: [[SHL_LHS:%.*]] = shl <2 x i32> [[LHS:%.*]], <i32 8, i32 8>
62 ; SI-NEXT: [[LHS24:%.*]] = ashr <2 x i32> [[SHL_LHS]], <i32 8, i32 8>
63 ; SI-NEXT: [[SHL_RHS:%.*]] = shl <2 x i32> [[RHS:%.*]], <i32 8, i32 8>
64 ; SI-NEXT: [[RHS24:%.*]] = ashr <2 x i32> [[SHL_RHS]], <i32 8, i32 8>
65 ; SI-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[LHS24]], i64 0
66 ; SI-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[LHS24]], i64 1
67 ; SI-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[RHS24]], i64 0
68 ; SI-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[RHS24]], i64 1
69 ; SI-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP3]])
70 ; SI-NEXT: [[TMP6:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP2]], i32 [[TMP4]])
71 ; SI-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> undef, i32 [[TMP5]], i64 0
72 ; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1
73 ; SI-NEXT: ret <2 x i32> [[MUL]]
74 ;
75 ; VI-LABEL: @smul24_v2i32(
76 ; VI-NEXT: [[SHL_LHS:%.*]] = shl <2 x i32> [[LHS:%.*]], <i32 8, i32 8>
77 ; VI-NEXT: [[LHS24:%.*]] = ashr <2 x i32> [[SHL_LHS]], <i32 8, i32 8>
78 ; VI-NEXT: [[SHL_RHS:%.*]] = shl <2 x i32> [[RHS:%.*]], <i32 8, i32 8>
79 ; VI-NEXT: [[RHS24:%.*]] = ashr <2 x i32> [[SHL_RHS]], <i32 8, i32 8>
80 ; VI-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[LHS24]], i64 0
81 ; VI-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[LHS24]], i64 1
82 ; VI-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[RHS24]], i64 0
83 ; VI-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[RHS24]], i64 1
84 ; VI-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP3]])
85 ; VI-NEXT: [[TMP6:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP2]], i32 [[TMP4]])
86 ; VI-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> undef, i32 [[TMP5]], i64 0
87 ; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1
88 ; VI-NEXT: ret <2 x i32> [[MUL]]
89 ;
90 ; DISABLED-LABEL: @smul24_v2i32(
91 ; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl <2 x i32> [[LHS:%.*]], <i32 8, i32 8>
92 ; DISABLED-NEXT: [[LHS24:%.*]] = ashr <2 x i32> [[SHL_LHS]], <i32 8, i32 8>
93 ; DISABLED-NEXT: [[SHL_RHS:%.*]] = shl <2 x i32> [[RHS:%.*]], <i32 8, i32 8>
94 ; DISABLED-NEXT: [[RHS24:%.*]] = ashr <2 x i32> [[SHL_RHS]], <i32 8, i32 8>
95 ; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i32> [[LHS24]], [[RHS24]]
96 ; DISABLED-NEXT: ret <2 x i32> [[MUL]]
97 ;
98 %shl.lhs = shl <2 x i32> %lhs, <i32 8, i32 8>
99 %lhs24 = ashr <2 x i32> %shl.lhs, <i32 8, i32 8>
100 %shl.rhs = shl <2 x i32> %rhs, <i32 8, i32 8>
101 %rhs24 = ashr <2 x i32> %shl.rhs, <i32 8, i32 8>
102 %mul = mul <2 x i32> %lhs24, %rhs24
103 ret <2 x i32> %mul
104 }
106 define i32 @umul24_i32(i32 %lhs, i32 %rhs) {
107 ; SI-LABEL: @umul24_i32(
108 ; SI-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 16777215
109 ; SI-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 16777215
110 ; SI-NEXT: [[MUL:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[LHS24]], i32 [[RHS24]])
111 ; SI-NEXT: ret i32 [[MUL]]
112 ;
113 ; VI-LABEL: @umul24_i32(
114 ; VI-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 16777215
115 ; VI-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 16777215
116 ; VI-NEXT: [[MUL:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[LHS24]], i32 [[RHS24]])
117 ; VI-NEXT: ret i32 [[MUL]]
118 ;
119 ; DISABLED-LABEL: @umul24_i32(
120 ; DISABLED-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 16777215
121 ; DISABLED-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 16777215
122 ; DISABLED-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
123 ; DISABLED-NEXT: ret i32 [[MUL]]
124 ;
125 %lhs24 = and i32 %lhs, 16777215
126 %rhs24 = and i32 %rhs, 16777215
127 %mul = mul i32 %lhs24, %rhs24
128 ret i32 %mul
129 }
131 define <2 x i32> @umul24_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
132 ; SI-LABEL: @umul24_v2i32(
133 ; SI-NEXT: [[LHS24:%.*]] = and <2 x i32> [[LHS:%.*]], <i32 16777215, i32 16777215>
134 ; SI-NEXT: [[RHS24:%.*]] = and <2 x i32> [[RHS:%.*]], <i32 16777215, i32 16777215>
135 ; SI-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[LHS24]], i64 0
136 ; SI-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[LHS24]], i64 1
137 ; SI-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[RHS24]], i64 0
138 ; SI-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[RHS24]], i64 1
139 ; SI-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP3]])
140 ; SI-NEXT: [[TMP6:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP2]], i32 [[TMP4]])
141 ; SI-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> undef, i32 [[TMP5]], i64 0
142 ; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1
143 ; SI-NEXT: ret <2 x i32> [[MUL]]
144 ;
145 ; VI-LABEL: @umul24_v2i32(
146 ; VI-NEXT: [[LHS24:%.*]] = and <2 x i32> [[LHS:%.*]], <i32 16777215, i32 16777215>
147 ; VI-NEXT: [[RHS24:%.*]] = and <2 x i32> [[RHS:%.*]], <i32 16777215, i32 16777215>
148 ; VI-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[LHS24]], i64 0
149 ; VI-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[LHS24]], i64 1
150 ; VI-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[RHS24]], i64 0
151 ; VI-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[RHS24]], i64 1
152 ; VI-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP3]])
153 ; VI-NEXT: [[TMP6:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP2]], i32 [[TMP4]])
154 ; VI-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> undef, i32 [[TMP5]], i64 0
155 ; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1
156 ; VI-NEXT: ret <2 x i32> [[MUL]]
157 ;
158 ; DISABLED-LABEL: @umul24_v2i32(
159 ; DISABLED-NEXT: [[LHS24:%.*]] = and <2 x i32> [[LHS:%.*]], <i32 16777215, i32 16777215>
160 ; DISABLED-NEXT: [[RHS24:%.*]] = and <2 x i32> [[RHS:%.*]], <i32 16777215, i32 16777215>
161 ; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i32> [[LHS24]], [[RHS24]]
162 ; DISABLED-NEXT: ret <2 x i32> [[MUL]]
163 ;
164 %lhs24 = and <2 x i32> %lhs, <i32 16777215, i32 16777215>
165 %rhs24 = and <2 x i32> %rhs, <i32 16777215, i32 16777215>
166 %mul = mul <2 x i32> %lhs24, %rhs24
167 ret <2 x i32> %mul
168 }
170 define i64 @smul24_i64(i64 %lhs, i64 %rhs) {
171 ; SI-LABEL: @smul24_i64(
172 ; SI-NEXT: [[SHL_LHS:%.*]] = shl i64 [[LHS:%.*]], 40
173 ; SI-NEXT: [[LHS24:%.*]] = ashr i64 [[SHL_LHS]], 40
174 ; SI-NEXT: [[SHL_RHS:%.*]] = shl i64 [[RHS:%.*]], 40
175 ; SI-NEXT: [[RHS24:%.*]] = ashr i64 [[SHL_RHS]], 40
176 ; SI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32
177 ; SI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32
178 ; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP2]])
179 ; SI-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mulhi.i24(i32 [[TMP1]], i32 [[TMP2]])
180 ; SI-NEXT: [[TMP5:%.*]] = zext i32 [[TMP3]] to i64
181 ; SI-NEXT: [[TMP6:%.*]] = zext i32 [[TMP4]] to i64
182 ; SI-NEXT: [[TMP7:%.*]] = shl i64 [[TMP6]], 32
183 ; SI-NEXT: [[MUL:%.*]] = or i64 [[TMP5]], [[TMP7]]
184 ; SI-NEXT: ret i64 [[MUL]]
185 ;
186 ; VI-LABEL: @smul24_i64(
187 ; VI-NEXT: [[SHL_LHS:%.*]] = shl i64 [[LHS:%.*]], 40
188 ; VI-NEXT: [[LHS24:%.*]] = ashr i64 [[SHL_LHS]], 40
189 ; VI-NEXT: [[SHL_RHS:%.*]] = shl i64 [[RHS:%.*]], 40
190 ; VI-NEXT: [[RHS24:%.*]] = ashr i64 [[SHL_RHS]], 40
191 ; VI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32
192 ; VI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32
193 ; VI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP2]])
194 ; VI-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mulhi.i24(i32 [[TMP1]], i32 [[TMP2]])
195 ; VI-NEXT: [[TMP5:%.*]] = zext i32 [[TMP3]] to i64
196 ; VI-NEXT: [[TMP6:%.*]] = zext i32 [[TMP4]] to i64
197 ; VI-NEXT: [[TMP7:%.*]] = shl i64 [[TMP6]], 32
198 ; VI-NEXT: [[MUL:%.*]] = or i64 [[TMP5]], [[TMP7]]
199 ; VI-NEXT: ret i64 [[MUL]]
200 ;
201 ; DISABLED-LABEL: @smul24_i64(
202 ; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i64 [[LHS:%.*]], 40
203 ; DISABLED-NEXT: [[LHS24:%.*]] = ashr i64 [[SHL_LHS]], 40
204 ; DISABLED-NEXT: [[SHL_RHS:%.*]] = shl i64 [[RHS:%.*]], 40
205 ; DISABLED-NEXT: [[RHS24:%.*]] = ashr i64 [[SHL_RHS]], 40
206 ; DISABLED-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]]
207 ; DISABLED-NEXT: ret i64 [[MUL]]
208 ;
209 %shl.lhs = shl i64 %lhs, 40
210 %lhs24 = ashr i64 %shl.lhs, 40
211 %shl.rhs = shl i64 %rhs, 40
212 %rhs24 = ashr i64 %shl.rhs, 40
213 %mul = mul i64 %lhs24, %rhs24
214 ret i64 %mul
215 }
217 define i64 @smul24_i64_2(i64 %lhs, i64 %rhs) {
218 ; SI-LABEL: @smul24_i64_2(
219 ; SI-NEXT: [[SHL_LHS:%.*]] = shl i64 [[LHS:%.*]], 49
220 ; SI-NEXT: [[LHS24:%.*]] = ashr i64 [[SHL_LHS]], 49
221 ; SI-NEXT: [[SHL_RHS:%.*]] = shl i64 [[RHS:%.*]], 49
222 ; SI-NEXT: [[RHS24:%.*]] = ashr i64 [[SHL_RHS]], 49
223 ; SI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32
224 ; SI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32
225 ; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP2]])
226 ; SI-NEXT: [[MUL:%.*]] = sext i32 [[TMP3]] to i64
227 ; SI-NEXT: ret i64 [[MUL]]
228 ;
229 ; VI-LABEL: @smul24_i64_2(
230 ; VI-NEXT: [[SHL_LHS:%.*]] = shl i64 [[LHS:%.*]], 49
231 ; VI-NEXT: [[LHS24:%.*]] = ashr i64 [[SHL_LHS]], 49
232 ; VI-NEXT: [[SHL_RHS:%.*]] = shl i64 [[RHS:%.*]], 49
233 ; VI-NEXT: [[RHS24:%.*]] = ashr i64 [[SHL_RHS]], 49
234 ; VI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32
235 ; VI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32
236 ; VI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP2]])
237 ; VI-NEXT: [[MUL:%.*]] = sext i32 [[TMP3]] to i64
238 ; VI-NEXT: ret i64 [[MUL]]
239 ;
240 ; DISABLED-LABEL: @smul24_i64_2(
241 ; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i64 [[LHS:%.*]], 49
242 ; DISABLED-NEXT: [[LHS24:%.*]] = ashr i64 [[SHL_LHS]], 49
243 ; DISABLED-NEXT: [[SHL_RHS:%.*]] = shl i64 [[RHS:%.*]], 49
244 ; DISABLED-NEXT: [[RHS24:%.*]] = ashr i64 [[SHL_RHS]], 49
245 ; DISABLED-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]]
246 ; DISABLED-NEXT: ret i64 [[MUL]]
247 ;
248 %shl.lhs = shl i64 %lhs, 49
249 %lhs24 = ashr i64 %shl.lhs, 49
250 %shl.rhs = shl i64 %rhs, 49
251 %rhs24 = ashr i64 %shl.rhs, 49
252 %mul = mul i64 %lhs24, %rhs24
253 ret i64 %mul
254 }
256 define i64 @smul24_i64_3(i64 %lhs, i64 %rhs) {
257 ; SI-LABEL: @smul24_i64_3(
258 ; SI-NEXT: [[LHS_TRUNC:%.*]] = trunc i64 [[LHS:%.*]] to i16
259 ; SI-NEXT: [[LHS24:%.*]] = sext i16 [[LHS_TRUNC]] to i64
260 ; SI-NEXT: [[RHS_TRUNC:%.*]] = trunc i64 [[RHS:%.*]] to i17
261 ; SI-NEXT: [[RHS24:%.*]] = sext i17 [[RHS_TRUNC]] to i64
262 ; SI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32
263 ; SI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32
264 ; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP2]])
265 ; SI-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mulhi.i24(i32 [[TMP1]], i32 [[TMP2]])
266 ; SI-NEXT: [[TMP5:%.*]] = zext i32 [[TMP3]] to i64
267 ; SI-NEXT: [[TMP6:%.*]] = zext i32 [[TMP4]] to i64
268 ; SI-NEXT: [[TMP7:%.*]] = shl i64 [[TMP6]], 32
269 ; SI-NEXT: [[MUL:%.*]] = or i64 [[TMP5]], [[TMP7]]
270 ; SI-NEXT: ret i64 [[MUL]]
271 ;
272 ; VI-LABEL: @smul24_i64_3(
273 ; VI-NEXT: [[LHS_TRUNC:%.*]] = trunc i64 [[LHS:%.*]] to i16
274 ; VI-NEXT: [[LHS24:%.*]] = sext i16 [[LHS_TRUNC]] to i64
275 ; VI-NEXT: [[RHS_TRUNC:%.*]] = trunc i64 [[RHS:%.*]] to i17
276 ; VI-NEXT: [[RHS24:%.*]] = sext i17 [[RHS_TRUNC]] to i64
277 ; VI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32
278 ; VI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32
279 ; VI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP2]])
280 ; VI-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mulhi.i24(i32 [[TMP1]], i32 [[TMP2]])
281 ; VI-NEXT: [[TMP5:%.*]] = zext i32 [[TMP3]] to i64
282 ; VI-NEXT: [[TMP6:%.*]] = zext i32 [[TMP4]] to i64
283 ; VI-NEXT: [[TMP7:%.*]] = shl i64 [[TMP6]], 32
284 ; VI-NEXT: [[MUL:%.*]] = or i64 [[TMP5]], [[TMP7]]
285 ; VI-NEXT: ret i64 [[MUL]]
286 ;
287 ; DISABLED-LABEL: @smul24_i64_3(
288 ; DISABLED-NEXT: [[LHS_TRUNC:%.*]] = trunc i64 [[LHS:%.*]] to i16
289 ; DISABLED-NEXT: [[LHS24:%.*]] = sext i16 [[LHS_TRUNC]] to i64
290 ; DISABLED-NEXT: [[RHS_TRUNC:%.*]] = trunc i64 [[RHS:%.*]] to i17
291 ; DISABLED-NEXT: [[RHS24:%.*]] = sext i17 [[RHS_TRUNC]] to i64
292 ; DISABLED-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]]
293 ; DISABLED-NEXT: ret i64 [[MUL]]
294 ;
295 %lhs.trunc = trunc i64 %lhs to i16
296 %lhs24 = sext i16 %lhs.trunc to i64
297 %rhs.trunc = trunc i64 %rhs to i17
298 %rhs24 = sext i17 %rhs.trunc to i64
299 %mul = mul i64 %lhs24, %rhs24
300 ret i64 %mul
301 }
303 define i64 @smul24_i64_4(i64 %lhs, i64 %rhs) {
304 ; SI-LABEL: @smul24_i64_4(
305 ; SI-NEXT: [[LHS_TRUNC:%.*]] = trunc i64 [[LHS:%.*]] to i24
306 ; SI-NEXT: [[LHS24:%.*]] = sext i24 [[LHS_TRUNC]] to i64
307 ; SI-NEXT: [[RHS_TRUNC:%.*]] = trunc i64 [[RHS:%.*]] to i25
308 ; SI-NEXT: [[RHS24:%.*]] = sext i25 [[RHS_TRUNC]] to i64
309 ; SI-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]]
310 ; SI-NEXT: ret i64 [[MUL]]
311 ;
312 ; VI-LABEL: @smul24_i64_4(
313 ; VI-NEXT: [[LHS_TRUNC:%.*]] = trunc i64 [[LHS:%.*]] to i24
314 ; VI-NEXT: [[LHS24:%.*]] = sext i24 [[LHS_TRUNC]] to i64
315 ; VI-NEXT: [[RHS_TRUNC:%.*]] = trunc i64 [[RHS:%.*]] to i25
316 ; VI-NEXT: [[RHS24:%.*]] = sext i25 [[RHS_TRUNC]] to i64
317 ; VI-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]]
318 ; VI-NEXT: ret i64 [[MUL]]
319 ;
320 ; DISABLED-LABEL: @smul24_i64_4(
321 ; DISABLED-NEXT: [[LHS_TRUNC:%.*]] = trunc i64 [[LHS:%.*]] to i24
322 ; DISABLED-NEXT: [[LHS24:%.*]] = sext i24 [[LHS_TRUNC]] to i64
323 ; DISABLED-NEXT: [[RHS_TRUNC:%.*]] = trunc i64 [[RHS:%.*]] to i25
324 ; DISABLED-NEXT: [[RHS24:%.*]] = sext i25 [[RHS_TRUNC]] to i64
325 ; DISABLED-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]]
326 ; DISABLED-NEXT: ret i64 [[MUL]]
327 ;
328 %lhs.trunc = trunc i64 %lhs to i24
329 %lhs24 = sext i24 %lhs.trunc to i64
330 %rhs.trunc = trunc i64 %rhs to i25
331 %rhs24 = sext i25 %rhs.trunc to i64
332 %mul = mul i64 %lhs24, %rhs24
333 ret i64 %mul
334 }
336 define i64 @umul24_i64(i64 %lhs, i64 %rhs) {
337 ; SI-LABEL: @umul24_i64(
338 ; SI-NEXT: [[LHS24:%.*]] = and i64 [[LHS:%.*]], 16777215
339 ; SI-NEXT: [[RHS24:%.*]] = and i64 [[RHS:%.*]], 16777215
340 ; SI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32
341 ; SI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32
342 ; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]])
343 ; SI-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mulhi.u24(i32 [[TMP1]], i32 [[TMP2]])
344 ; SI-NEXT: [[TMP5:%.*]] = zext i32 [[TMP3]] to i64
345 ; SI-NEXT: [[TMP6:%.*]] = zext i32 [[TMP4]] to i64
346 ; SI-NEXT: [[TMP7:%.*]] = shl i64 [[TMP6]], 32
347 ; SI-NEXT: [[MUL:%.*]] = or i64 [[TMP5]], [[TMP7]]
348 ; SI-NEXT: ret i64 [[MUL]]
349 ;
350 ; VI-LABEL: @umul24_i64(
351 ; VI-NEXT: [[LHS24:%.*]] = and i64 [[LHS:%.*]], 16777215
352 ; VI-NEXT: [[RHS24:%.*]] = and i64 [[RHS:%.*]], 16777215
353 ; VI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32
354 ; VI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32
355 ; VI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]])
356 ; VI-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mulhi.u24(i32 [[TMP1]], i32 [[TMP2]])
357 ; VI-NEXT: [[TMP5:%.*]] = zext i32 [[TMP3]] to i64
358 ; VI-NEXT: [[TMP6:%.*]] = zext i32 [[TMP4]] to i64
359 ; VI-NEXT: [[TMP7:%.*]] = shl i64 [[TMP6]], 32
360 ; VI-NEXT: [[MUL:%.*]] = or i64 [[TMP5]], [[TMP7]]
361 ; VI-NEXT: ret i64 [[MUL]]
362 ;
363 ; DISABLED-LABEL: @umul24_i64(
364 ; DISABLED-NEXT: [[LHS24:%.*]] = and i64 [[LHS:%.*]], 16777215
365 ; DISABLED-NEXT: [[RHS24:%.*]] = and i64 [[RHS:%.*]], 16777215
366 ; DISABLED-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]]
367 ; DISABLED-NEXT: ret i64 [[MUL]]
368 ;
369 %lhs24 = and i64 %lhs, 16777215
370 %rhs24 = and i64 %rhs, 16777215
371 %mul = mul i64 %lhs24, %rhs24
372 ret i64 %mul
373 }
375 define i64 @umul24_i64_2(i64 %lhs, i64 %rhs) {
376 ; SI-LABEL: @umul24_i64_2(
377 ; SI-NEXT: [[LHS24:%.*]] = and i64 [[LHS:%.*]], 65535
378 ; SI-NEXT: [[RHS24:%.*]] = and i64 [[RHS:%.*]], 65535
379 ; SI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32
380 ; SI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32
381 ; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]])
382 ; SI-NEXT: [[MUL:%.*]] = zext i32 [[TMP3]] to i64
383 ; SI-NEXT: ret i64 [[MUL]]
384 ;
385 ; VI-LABEL: @umul24_i64_2(
386 ; VI-NEXT: [[LHS24:%.*]] = and i64 [[LHS:%.*]], 65535
387 ; VI-NEXT: [[RHS24:%.*]] = and i64 [[RHS:%.*]], 65535
388 ; VI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32
389 ; VI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32
390 ; VI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]])
391 ; VI-NEXT: [[MUL:%.*]] = zext i32 [[TMP3]] to i64
392 ; VI-NEXT: ret i64 [[MUL]]
393 ;
394 ; DISABLED-LABEL: @umul24_i64_2(
395 ; DISABLED-NEXT: [[LHS24:%.*]] = and i64 [[LHS:%.*]], 65535
396 ; DISABLED-NEXT: [[RHS24:%.*]] = and i64 [[RHS:%.*]], 65535
397 ; DISABLED-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]]
398 ; DISABLED-NEXT: ret i64 [[MUL]]
399 ;
400 %lhs24 = and i64 %lhs, 65535
401 %rhs24 = and i64 %rhs, 65535
402 %mul = mul i64 %lhs24, %rhs24
403 ret i64 %mul
404 }
406 define i31 @smul24_i31(i31 %lhs, i31 %rhs) {
407 ; SI-LABEL: @smul24_i31(
408 ; SI-NEXT: [[SHL_LHS:%.*]] = shl i31 [[LHS:%.*]], 7
409 ; SI-NEXT: [[LHS24:%.*]] = ashr i31 [[SHL_LHS]], 7
410 ; SI-NEXT: [[SHL_RHS:%.*]] = shl i31 [[RHS:%.*]], 7
411 ; SI-NEXT: [[RHS24:%.*]] = ashr i31 [[SHL_RHS]], 7
412 ; SI-NEXT: [[TMP1:%.*]] = sext i31 [[LHS24]] to i32
413 ; SI-NEXT: [[TMP2:%.*]] = sext i31 [[RHS24]] to i32
414 ; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP2]])
415 ; SI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i31
416 ; SI-NEXT: ret i31 [[MUL]]
417 ;
418 ; VI-LABEL: @smul24_i31(
419 ; VI-NEXT: [[SHL_LHS:%.*]] = shl i31 [[LHS:%.*]], 7
420 ; VI-NEXT: [[LHS24:%.*]] = ashr i31 [[SHL_LHS]], 7
421 ; VI-NEXT: [[SHL_RHS:%.*]] = shl i31 [[RHS:%.*]], 7
422 ; VI-NEXT: [[RHS24:%.*]] = ashr i31 [[SHL_RHS]], 7
423 ; VI-NEXT: [[TMP1:%.*]] = sext i31 [[LHS24]] to i32
424 ; VI-NEXT: [[TMP2:%.*]] = sext i31 [[RHS24]] to i32
425 ; VI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP2]])
426 ; VI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i31
427 ; VI-NEXT: ret i31 [[MUL]]
428 ;
429 ; DISABLED-LABEL: @smul24_i31(
430 ; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i31 [[LHS:%.*]], 7
431 ; DISABLED-NEXT: [[LHS24:%.*]] = ashr i31 [[SHL_LHS]], 7
432 ; DISABLED-NEXT: [[SHL_RHS:%.*]] = shl i31 [[RHS:%.*]], 7
433 ; DISABLED-NEXT: [[RHS24:%.*]] = ashr i31 [[SHL_RHS]], 7
434 ; DISABLED-NEXT: [[MUL:%.*]] = mul i31 [[LHS24]], [[RHS24]]
435 ; DISABLED-NEXT: ret i31 [[MUL]]
436 ;
437 %shl.lhs = shl i31 %lhs, 7
438 %lhs24 = ashr i31 %shl.lhs, 7
439 %shl.rhs = shl i31 %rhs, 7
440 %rhs24 = ashr i31 %shl.rhs, 7
441 %mul = mul i31 %lhs24, %rhs24
442 ret i31 %mul
443 }
445 define i31 @umul24_i31(i31 %lhs, i31 %rhs) {
446 ; SI-LABEL: @umul24_i31(
447 ; SI-NEXT: [[LHS24:%.*]] = and i31 [[LHS:%.*]], 16777215
448 ; SI-NEXT: [[RHS24:%.*]] = and i31 [[RHS:%.*]], 16777215
449 ; SI-NEXT: [[TMP1:%.*]] = zext i31 [[LHS24]] to i32
450 ; SI-NEXT: [[TMP2:%.*]] = zext i31 [[RHS24]] to i32
451 ; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]])
452 ; SI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i31
453 ; SI-NEXT: ret i31 [[MUL]]
454 ;
455 ; VI-LABEL: @umul24_i31(
456 ; VI-NEXT: [[LHS24:%.*]] = and i31 [[LHS:%.*]], 16777215
457 ; VI-NEXT: [[RHS24:%.*]] = and i31 [[RHS:%.*]], 16777215
458 ; VI-NEXT: [[TMP1:%.*]] = zext i31 [[LHS24]] to i32
459 ; VI-NEXT: [[TMP2:%.*]] = zext i31 [[RHS24]] to i32
460 ; VI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]])
461 ; VI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i31
462 ; VI-NEXT: ret i31 [[MUL]]
463 ;
464 ; DISABLED-LABEL: @umul24_i31(
465 ; DISABLED-NEXT: [[LHS24:%.*]] = and i31 [[LHS:%.*]], 16777215
466 ; DISABLED-NEXT: [[RHS24:%.*]] = and i31 [[RHS:%.*]], 16777215
467 ; DISABLED-NEXT: [[MUL:%.*]] = mul i31 [[LHS24]], [[RHS24]]
468 ; DISABLED-NEXT: ret i31 [[MUL]]
469 ;
470 %lhs24 = and i31 %lhs, 16777215
471 %rhs24 = and i31 %rhs, 16777215
472 %mul = mul i31 %lhs24, %rhs24
473 ret i31 %mul
474 }
476 define <2 x i31> @umul24_v2i31(<2 x i31> %lhs, <2 x i31> %rhs) {
477 ; SI-LABEL: @umul24_v2i31(
478 ; SI-NEXT: [[LHS24:%.*]] = and <2 x i31> [[LHS:%.*]], <i31 16777215, i31 16777215>
479 ; SI-NEXT: [[RHS24:%.*]] = and <2 x i31> [[RHS:%.*]], <i31 16777215, i31 16777215>
480 ; SI-NEXT: [[TMP1:%.*]] = extractelement <2 x i31> [[LHS24]], i64 0
481 ; SI-NEXT: [[TMP2:%.*]] = extractelement <2 x i31> [[LHS24]], i64 1
482 ; SI-NEXT: [[TMP3:%.*]] = extractelement <2 x i31> [[RHS24]], i64 0
483 ; SI-NEXT: [[TMP4:%.*]] = extractelement <2 x i31> [[RHS24]], i64 1
484 ; SI-NEXT: [[TMP5:%.*]] = zext i31 [[TMP1]] to i32
485 ; SI-NEXT: [[TMP6:%.*]] = zext i31 [[TMP3]] to i32
486 ; SI-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP5]], i32 [[TMP6]])
487 ; SI-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP7]] to i31
488 ; SI-NEXT: [[TMP9:%.*]] = zext i31 [[TMP2]] to i32
489 ; SI-NEXT: [[TMP10:%.*]] = zext i31 [[TMP4]] to i32
490 ; SI-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP9]], i32 [[TMP10]])
491 ; SI-NEXT: [[TMP12:%.*]] = trunc i32 [[TMP11]] to i31
492 ; SI-NEXT: [[TMP13:%.*]] = insertelement <2 x i31> undef, i31 [[TMP8]], i64 0
493 ; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1
494 ; SI-NEXT: ret <2 x i31> [[MUL]]
495 ;
496 ; VI-LABEL: @umul24_v2i31(
497 ; VI-NEXT: [[LHS24:%.*]] = and <2 x i31> [[LHS:%.*]], <i31 16777215, i31 16777215>
498 ; VI-NEXT: [[RHS24:%.*]] = and <2 x i31> [[RHS:%.*]], <i31 16777215, i31 16777215>
499 ; VI-NEXT: [[TMP1:%.*]] = extractelement <2 x i31> [[LHS24]], i64 0
500 ; VI-NEXT: [[TMP2:%.*]] = extractelement <2 x i31> [[LHS24]], i64 1
501 ; VI-NEXT: [[TMP3:%.*]] = extractelement <2 x i31> [[RHS24]], i64 0
502 ; VI-NEXT: [[TMP4:%.*]] = extractelement <2 x i31> [[RHS24]], i64 1
503 ; VI-NEXT: [[TMP5:%.*]] = zext i31 [[TMP1]] to i32
504 ; VI-NEXT: [[TMP6:%.*]] = zext i31 [[TMP3]] to i32
505 ; VI-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP5]], i32 [[TMP6]])
506 ; VI-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP7]] to i31
507 ; VI-NEXT: [[TMP9:%.*]] = zext i31 [[TMP2]] to i32
508 ; VI-NEXT: [[TMP10:%.*]] = zext i31 [[TMP4]] to i32
509 ; VI-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP9]], i32 [[TMP10]])
510 ; VI-NEXT: [[TMP12:%.*]] = trunc i32 [[TMP11]] to i31
511 ; VI-NEXT: [[TMP13:%.*]] = insertelement <2 x i31> undef, i31 [[TMP8]], i64 0
512 ; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1
513 ; VI-NEXT: ret <2 x i31> [[MUL]]
514 ;
515 ; DISABLED-LABEL: @umul24_v2i31(
516 ; DISABLED-NEXT: [[LHS24:%.*]] = and <2 x i31> [[LHS:%.*]], <i31 16777215, i31 16777215>
517 ; DISABLED-NEXT: [[RHS24:%.*]] = and <2 x i31> [[RHS:%.*]], <i31 16777215, i31 16777215>
518 ; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i31> [[LHS24]], [[RHS24]]
519 ; DISABLED-NEXT: ret <2 x i31> [[MUL]]
520 ;
521 %lhs24 = and <2 x i31> %lhs, <i31 16777215, i31 16777215>
522 %rhs24 = and <2 x i31> %rhs, <i31 16777215, i31 16777215>
523 %mul = mul <2 x i31> %lhs24, %rhs24
524 ret <2 x i31> %mul
525 }
527 define <2 x i31> @smul24_v2i31(<2 x i31> %lhs, <2 x i31> %rhs) {
528 ; SI-LABEL: @smul24_v2i31(
529 ; SI-NEXT: [[SHL_LHS:%.*]] = shl <2 x i31> [[LHS:%.*]], <i31 8, i31 8>
530 ; SI-NEXT: [[LHS24:%.*]] = ashr <2 x i31> [[SHL_LHS]], <i31 8, i31 8>
531 ; SI-NEXT: [[SHL_RHS:%.*]] = shl <2 x i31> [[RHS:%.*]], <i31 8, i31 8>
532 ; SI-NEXT: [[RHS24:%.*]] = ashr <2 x i31> [[SHL_RHS]], <i31 8, i31 8>
533 ; SI-NEXT: [[TMP1:%.*]] = extractelement <2 x i31> [[LHS24]], i64 0
534 ; SI-NEXT: [[TMP2:%.*]] = extractelement <2 x i31> [[LHS24]], i64 1
535 ; SI-NEXT: [[TMP3:%.*]] = extractelement <2 x i31> [[RHS24]], i64 0
536 ; SI-NEXT: [[TMP4:%.*]] = extractelement <2 x i31> [[RHS24]], i64 1
537 ; SI-NEXT: [[TMP5:%.*]] = sext i31 [[TMP1]] to i32
538 ; SI-NEXT: [[TMP6:%.*]] = sext i31 [[TMP3]] to i32
539 ; SI-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP5]], i32 [[TMP6]])
540 ; SI-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP7]] to i31
541 ; SI-NEXT: [[TMP9:%.*]] = sext i31 [[TMP2]] to i32
542 ; SI-NEXT: [[TMP10:%.*]] = sext i31 [[TMP4]] to i32
543 ; SI-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP9]], i32 [[TMP10]])
544 ; SI-NEXT: [[TMP12:%.*]] = trunc i32 [[TMP11]] to i31
545 ; SI-NEXT: [[TMP13:%.*]] = insertelement <2 x i31> undef, i31 [[TMP8]], i64 0
546 ; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1
547 ; SI-NEXT: ret <2 x i31> [[MUL]]
548 ;
549 ; VI-LABEL: @smul24_v2i31(
550 ; VI-NEXT: [[SHL_LHS:%.*]] = shl <2 x i31> [[LHS:%.*]], <i31 8, i31 8>
551 ; VI-NEXT: [[LHS24:%.*]] = ashr <2 x i31> [[SHL_LHS]], <i31 8, i31 8>
552 ; VI-NEXT: [[SHL_RHS:%.*]] = shl <2 x i31> [[RHS:%.*]], <i31 8, i31 8>
553 ; VI-NEXT: [[RHS24:%.*]] = ashr <2 x i31> [[SHL_RHS]], <i31 8, i31 8>
554 ; VI-NEXT: [[TMP1:%.*]] = extractelement <2 x i31> [[LHS24]], i64 0
555 ; VI-NEXT: [[TMP2:%.*]] = extractelement <2 x i31> [[LHS24]], i64 1
556 ; VI-NEXT: [[TMP3:%.*]] = extractelement <2 x i31> [[RHS24]], i64 0
557 ; VI-NEXT: [[TMP4:%.*]] = extractelement <2 x i31> [[RHS24]], i64 1
558 ; VI-NEXT: [[TMP5:%.*]] = sext i31 [[TMP1]] to i32
559 ; VI-NEXT: [[TMP6:%.*]] = sext i31 [[TMP3]] to i32
560 ; VI-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP5]], i32 [[TMP6]])
561 ; VI-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP7]] to i31
562 ; VI-NEXT: [[TMP9:%.*]] = sext i31 [[TMP2]] to i32
563 ; VI-NEXT: [[TMP10:%.*]] = sext i31 [[TMP4]] to i32
564 ; VI-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP9]], i32 [[TMP10]])
565 ; VI-NEXT: [[TMP12:%.*]] = trunc i32 [[TMP11]] to i31
566 ; VI-NEXT: [[TMP13:%.*]] = insertelement <2 x i31> undef, i31 [[TMP8]], i64 0
567 ; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1
568 ; VI-NEXT: ret <2 x i31> [[MUL]]
569 ;
570 ; DISABLED-LABEL: @smul24_v2i31(
571 ; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl <2 x i31> [[LHS:%.*]], <i31 8, i31 8>
572 ; DISABLED-NEXT: [[LHS24:%.*]] = ashr <2 x i31> [[SHL_LHS]], <i31 8, i31 8>
573 ; DISABLED-NEXT: [[SHL_RHS:%.*]] = shl <2 x i31> [[RHS:%.*]], <i31 8, i31 8>
574 ; DISABLED-NEXT: [[RHS24:%.*]] = ashr <2 x i31> [[SHL_RHS]], <i31 8, i31 8>
575 ; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i31> [[LHS24]], [[RHS24]]
576 ; DISABLED-NEXT: ret <2 x i31> [[MUL]]
577 ;
578 %shl.lhs = shl <2 x i31> %lhs, <i31 8, i31 8>
579 %lhs24 = ashr <2 x i31> %shl.lhs, <i31 8, i31 8>
580 %shl.rhs = shl <2 x i31> %rhs, <i31 8, i31 8>
581 %rhs24 = ashr <2 x i31> %shl.rhs, <i31 8, i31 8>
582 %mul = mul <2 x i31> %lhs24, %rhs24
583 ret <2 x i31> %mul
584 }
586 define i33 @smul24_i33(i33 %lhs, i33 %rhs) {
587 ; SI-LABEL: @smul24_i33(
588 ; SI-NEXT: [[SHL_LHS:%.*]] = shl i33 [[LHS:%.*]], 9
589 ; SI-NEXT: [[LHS24:%.*]] = ashr i33 [[SHL_LHS]], 9
590 ; SI-NEXT: [[SHL_RHS:%.*]] = shl i33 [[RHS:%.*]], 9
591 ; SI-NEXT: [[RHS24:%.*]] = ashr i33 [[SHL_RHS]], 9
592 ; SI-NEXT: [[TMP1:%.*]] = trunc i33 [[LHS24]] to i32
593 ; SI-NEXT: [[TMP2:%.*]] = trunc i33 [[RHS24]] to i32
594 ; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP2]])
595 ; SI-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mulhi.i24(i32 [[TMP1]], i32 [[TMP2]])
596 ; SI-NEXT: [[TMP5:%.*]] = zext i32 [[TMP3]] to i64
597 ; SI-NEXT: [[TMP6:%.*]] = zext i32 [[TMP4]] to i64
598 ; SI-NEXT: [[TMP7:%.*]] = shl i64 [[TMP6]], 32
599 ; SI-NEXT: [[TMP8:%.*]] = or i64 [[TMP5]], [[TMP7]]
600 ; SI-NEXT: [[MUL:%.*]] = trunc i64 [[TMP8]] to i33
601 ; SI-NEXT: ret i33 [[MUL]]
602 ;
603 ; VI-LABEL: @smul24_i33(
604 ; VI-NEXT: [[SHL_LHS:%.*]] = shl i33 [[LHS:%.*]], 9
605 ; VI-NEXT: [[LHS24:%.*]] = ashr i33 [[SHL_LHS]], 9
606 ; VI-NEXT: [[SHL_RHS:%.*]] = shl i33 [[RHS:%.*]], 9
607 ; VI-NEXT: [[RHS24:%.*]] = ashr i33 [[SHL_RHS]], 9
608 ; VI-NEXT: [[TMP1:%.*]] = trunc i33 [[LHS24]] to i32
609 ; VI-NEXT: [[TMP2:%.*]] = trunc i33 [[RHS24]] to i32
610 ; VI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP2]])
611 ; VI-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mulhi.i24(i32 [[TMP1]], i32 [[TMP2]])
612 ; VI-NEXT: [[TMP5:%.*]] = zext i32 [[TMP3]] to i64
613 ; VI-NEXT: [[TMP6:%.*]] = zext i32 [[TMP4]] to i64
614 ; VI-NEXT: [[TMP7:%.*]] = shl i64 [[TMP6]], 32
615 ; VI-NEXT: [[TMP8:%.*]] = or i64 [[TMP5]], [[TMP7]]
616 ; VI-NEXT: [[MUL:%.*]] = trunc i64 [[TMP8]] to i33
617 ; VI-NEXT: ret i33 [[MUL]]
618 ;
619 ; DISABLED-LABEL: @smul24_i33(
620 ; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i33 [[LHS:%.*]], 9
621 ; DISABLED-NEXT: [[LHS24:%.*]] = ashr i33 [[SHL_LHS]], 9
622 ; DISABLED-NEXT: [[SHL_RHS:%.*]] = shl i33 [[RHS:%.*]], 9
623 ; DISABLED-NEXT: [[RHS24:%.*]] = ashr i33 [[SHL_RHS]], 9
624 ; DISABLED-NEXT: [[MUL:%.*]] = mul i33 [[LHS24]], [[RHS24]]
625 ; DISABLED-NEXT: ret i33 [[MUL]]
626 ;
627 %shl.lhs = shl i33 %lhs, 9
628 %lhs24 = ashr i33 %shl.lhs, 9
629 %shl.rhs = shl i33 %rhs, 9
630 %rhs24 = ashr i33 %shl.rhs, 9
631 %mul = mul i33 %lhs24, %rhs24
632 ret i33 %mul
633 }
635 define i33 @umul24_i33(i33 %lhs, i33 %rhs) {
636 ; SI-LABEL: @umul24_i33(
637 ; SI-NEXT: [[LHS24:%.*]] = and i33 [[LHS:%.*]], 16777215
638 ; SI-NEXT: [[RHS24:%.*]] = and i33 [[RHS:%.*]], 16777215
639 ; SI-NEXT: [[TMP1:%.*]] = trunc i33 [[LHS24]] to i32
640 ; SI-NEXT: [[TMP2:%.*]] = trunc i33 [[RHS24]] to i32
641 ; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]])
642 ; SI-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mulhi.u24(i32 [[TMP1]], i32 [[TMP2]])
643 ; SI-NEXT: [[TMP5:%.*]] = zext i32 [[TMP3]] to i64
644 ; SI-NEXT: [[TMP6:%.*]] = zext i32 [[TMP4]] to i64
645 ; SI-NEXT: [[TMP7:%.*]] = shl i64 [[TMP6]], 32
646 ; SI-NEXT: [[TMP8:%.*]] = or i64 [[TMP5]], [[TMP7]]
647 ; SI-NEXT: [[MUL:%.*]] = trunc i64 [[TMP8]] to i33
648 ; SI-NEXT: ret i33 [[MUL]]
649 ;
650 ; VI-LABEL: @umul24_i33(
651 ; VI-NEXT: [[LHS24:%.*]] = and i33 [[LHS:%.*]], 16777215
652 ; VI-NEXT: [[RHS24:%.*]] = and i33 [[RHS:%.*]], 16777215
653 ; VI-NEXT: [[TMP1:%.*]] = trunc i33 [[LHS24]] to i32
654 ; VI-NEXT: [[TMP2:%.*]] = trunc i33 [[RHS24]] to i32
655 ; VI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]])
656 ; VI-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mulhi.u24(i32 [[TMP1]], i32 [[TMP2]])
657 ; VI-NEXT: [[TMP5:%.*]] = zext i32 [[TMP3]] to i64
658 ; VI-NEXT: [[TMP6:%.*]] = zext i32 [[TMP4]] to i64
659 ; VI-NEXT: [[TMP7:%.*]] = shl i64 [[TMP6]], 32
660 ; VI-NEXT: [[TMP8:%.*]] = or i64 [[TMP5]], [[TMP7]]
661 ; VI-NEXT: [[MUL:%.*]] = trunc i64 [[TMP8]] to i33
662 ; VI-NEXT: ret i33 [[MUL]]
663 ;
664 ; DISABLED-LABEL: @umul24_i33(
665 ; DISABLED-NEXT: [[LHS24:%.*]] = and i33 [[LHS:%.*]], 16777215
666 ; DISABLED-NEXT: [[RHS24:%.*]] = and i33 [[RHS:%.*]], 16777215
667 ; DISABLED-NEXT: [[MUL:%.*]] = mul i33 [[LHS24]], [[RHS24]]
668 ; DISABLED-NEXT: ret i33 [[MUL]]
669 ;
670 %lhs24 = and i33 %lhs, 16777215
671 %rhs24 = and i33 %rhs, 16777215
672 %mul = mul i33 %lhs24, %rhs24
673 ret i33 %mul
674 }
676 define i32 @smul25_i32(i32 %lhs, i32 %rhs) {
677 ; SI-LABEL: @smul25_i32(
678 ; SI-NEXT: [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 7
679 ; SI-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 7
680 ; SI-NEXT: [[SHL_RHS:%.*]] = shl i32 [[RHS:%.*]], 7
681 ; SI-NEXT: [[RHS24:%.*]] = ashr i32 [[SHL_RHS]], 7
682 ; SI-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
683 ; SI-NEXT: ret i32 [[MUL]]
684 ;
685 ; VI-LABEL: @smul25_i32(
686 ; VI-NEXT: [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 7
687 ; VI-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 7
688 ; VI-NEXT: [[SHL_RHS:%.*]] = shl i32 [[RHS:%.*]], 7
689 ; VI-NEXT: [[RHS24:%.*]] = ashr i32 [[SHL_RHS]], 7
690 ; VI-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
691 ; VI-NEXT: ret i32 [[MUL]]
692 ;
693 ; DISABLED-LABEL: @smul25_i32(
694 ; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 7
695 ; DISABLED-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 7
696 ; DISABLED-NEXT: [[SHL_RHS:%.*]] = shl i32 [[RHS:%.*]], 7
697 ; DISABLED-NEXT: [[RHS24:%.*]] = ashr i32 [[SHL_RHS]], 7
698 ; DISABLED-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
699 ; DISABLED-NEXT: ret i32 [[MUL]]
700 ;
701 %shl.lhs = shl i32 %lhs, 7
702 %lhs24 = ashr i32 %shl.lhs, 7
703 %shl.rhs = shl i32 %rhs, 7
704 %rhs24 = ashr i32 %shl.rhs, 7
705 %mul = mul i32 %lhs24, %rhs24
706 ret i32 %mul
707 }
709 define i32 @umul25_i32(i32 %lhs, i32 %rhs) {
710 ; SI-LABEL: @umul25_i32(
711 ; SI-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 33554431
712 ; SI-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 33554431
713 ; SI-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
714 ; SI-NEXT: ret i32 [[MUL]]
715 ;
716 ; VI-LABEL: @umul25_i32(
717 ; VI-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 33554431
718 ; VI-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 33554431
719 ; VI-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
720 ; VI-NEXT: ret i32 [[MUL]]
721 ;
722 ; DISABLED-LABEL: @umul25_i32(
723 ; DISABLED-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 33554431
724 ; DISABLED-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 33554431
725 ; DISABLED-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
726 ; DISABLED-NEXT: ret i32 [[MUL]]
727 ;
728 %lhs24 = and i32 %lhs, 33554431
729 %rhs24 = and i32 %rhs, 33554431
730 %mul = mul i32 %lhs24, %rhs24
731 ret i32 %mul
732 }
734 define <2 x i33> @smul24_v2i33(<2 x i33> %lhs, <2 x i33> %rhs) {
735 ; SI-LABEL: @smul24_v2i33(
736 ; SI-NEXT: [[SHL_LHS:%.*]] = shl <2 x i33> [[LHS:%.*]], <i33 9, i33 9>
737 ; SI-NEXT: [[LHS24:%.*]] = ashr <2 x i33> [[SHL_LHS]], <i33 9, i33 9>
738 ; SI-NEXT: [[SHL_RHS:%.*]] = shl <2 x i33> [[RHS:%.*]], <i33 9, i33 9>
739 ; SI-NEXT: [[RHS24:%.*]] = ashr <2 x i33> [[SHL_RHS]], <i33 9, i33 9>
740 ; SI-NEXT: [[TMP1:%.*]] = extractelement <2 x i33> [[LHS24]], i64 0
741 ; SI-NEXT: [[TMP2:%.*]] = extractelement <2 x i33> [[LHS24]], i64 1
742 ; SI-NEXT: [[TMP3:%.*]] = extractelement <2 x i33> [[RHS24]], i64 0
743 ; SI-NEXT: [[TMP4:%.*]] = extractelement <2 x i33> [[RHS24]], i64 1
744 ; SI-NEXT: [[TMP5:%.*]] = trunc i33 [[TMP1]] to i32
745 ; SI-NEXT: [[TMP6:%.*]] = trunc i33 [[TMP3]] to i32
746 ; SI-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP5]], i32 [[TMP6]])
747 ; SI-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.mulhi.i24(i32 [[TMP5]], i32 [[TMP6]])
748 ; SI-NEXT: [[TMP9:%.*]] = zext i32 [[TMP7]] to i64
749 ; SI-NEXT: [[TMP10:%.*]] = zext i32 [[TMP8]] to i64
750 ; SI-NEXT: [[TMP11:%.*]] = shl i64 [[TMP10]], 32
751 ; SI-NEXT: [[TMP12:%.*]] = or i64 [[TMP9]], [[TMP11]]
752 ; SI-NEXT: [[TMP13:%.*]] = trunc i64 [[TMP12]] to i33
753 ; SI-NEXT: [[TMP14:%.*]] = trunc i33 [[TMP2]] to i32
754 ; SI-NEXT: [[TMP15:%.*]] = trunc i33 [[TMP4]] to i32
755 ; SI-NEXT: [[TMP16:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP14]], i32 [[TMP15]])
756 ; SI-NEXT: [[TMP17:%.*]] = call i32 @llvm.amdgcn.mulhi.i24(i32 [[TMP14]], i32 [[TMP15]])
757 ; SI-NEXT: [[TMP18:%.*]] = zext i32 [[TMP16]] to i64
758 ; SI-NEXT: [[TMP19:%.*]] = zext i32 [[TMP17]] to i64
759 ; SI-NEXT: [[TMP20:%.*]] = shl i64 [[TMP19]], 32
760 ; SI-NEXT: [[TMP21:%.*]] = or i64 [[TMP18]], [[TMP20]]
761 ; SI-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i33
762 ; SI-NEXT: [[TMP23:%.*]] = insertelement <2 x i33> undef, i33 [[TMP13]], i64 0
763 ; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i33> [[TMP23]], i33 [[TMP22]], i64 1
764 ; SI-NEXT: ret <2 x i33> [[MUL]]
765 ;
766 ; VI-LABEL: @smul24_v2i33(
767 ; VI-NEXT: [[SHL_LHS:%.*]] = shl <2 x i33> [[LHS:%.*]], <i33 9, i33 9>
768 ; VI-NEXT: [[LHS24:%.*]] = ashr <2 x i33> [[SHL_LHS]], <i33 9, i33 9>
769 ; VI-NEXT: [[SHL_RHS:%.*]] = shl <2 x i33> [[RHS:%.*]], <i33 9, i33 9>
770 ; VI-NEXT: [[RHS24:%.*]] = ashr <2 x i33> [[SHL_RHS]], <i33 9, i33 9>
771 ; VI-NEXT: [[TMP1:%.*]] = extractelement <2 x i33> [[LHS24]], i64 0
772 ; VI-NEXT: [[TMP2:%.*]] = extractelement <2 x i33> [[LHS24]], i64 1
773 ; VI-NEXT: [[TMP3:%.*]] = extractelement <2 x i33> [[RHS24]], i64 0
774 ; VI-NEXT: [[TMP4:%.*]] = extractelement <2 x i33> [[RHS24]], i64 1
775 ; VI-NEXT: [[TMP5:%.*]] = trunc i33 [[TMP1]] to i32
776 ; VI-NEXT: [[TMP6:%.*]] = trunc i33 [[TMP3]] to i32
777 ; VI-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP5]], i32 [[TMP6]])
778 ; VI-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.mulhi.i24(i32 [[TMP5]], i32 [[TMP6]])
779 ; VI-NEXT: [[TMP9:%.*]] = zext i32 [[TMP7]] to i64
780 ; VI-NEXT: [[TMP10:%.*]] = zext i32 [[TMP8]] to i64
781 ; VI-NEXT: [[TMP11:%.*]] = shl i64 [[TMP10]], 32
782 ; VI-NEXT: [[TMP12:%.*]] = or i64 [[TMP9]], [[TMP11]]
783 ; VI-NEXT: [[TMP13:%.*]] = trunc i64 [[TMP12]] to i33
784 ; VI-NEXT: [[TMP14:%.*]] = trunc i33 [[TMP2]] to i32
785 ; VI-NEXT: [[TMP15:%.*]] = trunc i33 [[TMP4]] to i32
786 ; VI-NEXT: [[TMP16:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP14]], i32 [[TMP15]])
787 ; VI-NEXT: [[TMP17:%.*]] = call i32 @llvm.amdgcn.mulhi.i24(i32 [[TMP14]], i32 [[TMP15]])
788 ; VI-NEXT: [[TMP18:%.*]] = zext i32 [[TMP16]] to i64
789 ; VI-NEXT: [[TMP19:%.*]] = zext i32 [[TMP17]] to i64
790 ; VI-NEXT: [[TMP20:%.*]] = shl i64 [[TMP19]], 32
791 ; VI-NEXT: [[TMP21:%.*]] = or i64 [[TMP18]], [[TMP20]]
792 ; VI-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i33
793 ; VI-NEXT: [[TMP23:%.*]] = insertelement <2 x i33> undef, i33 [[TMP13]], i64 0
794 ; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i33> [[TMP23]], i33 [[TMP22]], i64 1
795 ; VI-NEXT: ret <2 x i33> [[MUL]]
796 ;
797 ; DISABLED-LABEL: @smul24_v2i33(
798 ; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl <2 x i33> [[LHS:%.*]], <i33 9, i33 9>
799 ; DISABLED-NEXT: [[LHS24:%.*]] = ashr <2 x i33> [[SHL_LHS]], <i33 9, i33 9>
800 ; DISABLED-NEXT: [[SHL_RHS:%.*]] = shl <2 x i33> [[RHS:%.*]], <i33 9, i33 9>
801 ; DISABLED-NEXT: [[RHS24:%.*]] = ashr <2 x i33> [[SHL_RHS]], <i33 9, i33 9>
802 ; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i33> [[LHS24]], [[RHS24]]
803 ; DISABLED-NEXT: ret <2 x i33> [[MUL]]
804 ;
805 %shl.lhs = shl <2 x i33> %lhs, <i33 9, i33 9>
806 %lhs24 = ashr <2 x i33> %shl.lhs, <i33 9, i33 9>
807 %shl.rhs = shl <2 x i33> %rhs, <i33 9, i33 9>
808 %rhs24 = ashr <2 x i33> %shl.rhs, <i33 9, i33 9>
809 %mul = mul <2 x i33> %lhs24, %rhs24
810 ret <2 x i33> %mul
811 }