llvm/test/CodeGen/AMDGPU/lower-term-opcodes.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=si-optimize-exec-masking -verify-machineinstrs  %s -o - | FileCheck %s
   3 # RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass=si-optimize-exec-masking -verify-machineinstrs  %s -o - | FileCheck %s
   4
   5 ---
   6 name: lower_term_opcodes
   7 tracksRegLiveness: false
   8 body: |
   9   ; CHECK-LABEL: name: lower_term_opcodes
  10   ; CHECK: bb.0:
  11   ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  12   ; CHECK-NEXT: {{  $}}
  13   ; CHECK-NEXT:   $sgpr0 = COPY $sgpr1
  14   ; CHECK-NEXT: {{  $}}
  15   ; CHECK-NEXT: bb.1:
  16   ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  17   ; CHECK-NEXT: {{  $}}
  18   ; CHECK-NEXT:   $sgpr0 = S_MOV_B32 0
  19   ; CHECK-NEXT: {{  $}}
  20   ; CHECK-NEXT: bb.2:
  21   ; CHECK-NEXT:   successors: %bb.3(0x80000000)
  22   ; CHECK-NEXT: {{  $}}
  23   ; CHECK-NEXT:   $sgpr0 = S_MOV_B32 &SYMBOL
  24   ; CHECK-NEXT: {{  $}}
  25   ; CHECK-NEXT: bb.3:
  26   ; CHECK-NEXT:   successors: %bb.4(0x80000000)
  27   ; CHECK-NEXT: {{  $}}
  28   ; CHECK-NEXT:   $sgpr0_sgpr1 = COPY $sgpr2_sgpr3
  29   ; CHECK-NEXT: {{  $}}
  30   ; CHECK-NEXT: bb.4:
  31   ; CHECK-NEXT:   successors: %bb.5(0x80000000)
  32   ; CHECK-NEXT: {{  $}}
  33   ; CHECK-NEXT:   $sgpr0_sgpr1 = S_MOV_B64 0
  34   ; CHECK-NEXT: {{  $}}
  35   ; CHECK-NEXT: bb.5:
  36   ; CHECK-NEXT:   successors: %bb.6(0x80000000)
  37   ; CHECK-NEXT: {{  $}}
  38   ; CHECK-NEXT:   $sgpr0_sgpr1 = S_MOV_B64 &SYMBOL
  39   ; CHECK-NEXT: {{  $}}
  40   ; CHECK-NEXT: bb.6:
  41   ; CHECK-NEXT:   successors: %bb.7(0x80000000)
  42   ; CHECK-NEXT: {{  $}}
  43   ; CHECK-NEXT:   $sgpr0 = S_XOR_B32 $sgpr1, $sgpr2, implicit-def $scc
  44   ; CHECK-NEXT: {{  $}}
  45   ; CHECK-NEXT: bb.7:
  46   ; CHECK-NEXT:   successors: %bb.8(0x80000000)
  47   ; CHECK-NEXT: {{  $}}
  48   ; CHECK-NEXT:   $sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc
  49   ; CHECK-NEXT: {{  $}}
  50   ; CHECK-NEXT: bb.8:
  51   ; CHECK-NEXT:   successors: %bb.9(0x80000000)
  52   ; CHECK-NEXT: {{  $}}
  53   ; CHECK-NEXT:   $sgpr0 = S_OR_B32 $sgpr1, $sgpr2, implicit-def $scc
  54   ; CHECK-NEXT: {{  $}}
  55   ; CHECK-NEXT: bb.9:
  56   ; CHECK-NEXT:   successors: %bb.10(0x80000000)
  57   ; CHECK-NEXT: {{  $}}
  58   ; CHECK-NEXT:   $sgpr0_sgpr1 = S_OR_B64 $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc
  59   ; CHECK-NEXT: {{  $}}
  60   ; CHECK-NEXT: bb.10:
  61   ; CHECK-NEXT:   successors: %bb.11(0x80000000)
  62   ; CHECK-NEXT: {{  $}}
  63   ; CHECK-NEXT:   $sgpr0 = S_ANDN2_B32 $sgpr1, $sgpr2, implicit-def $scc
  64   ; CHECK-NEXT: {{  $}}
  65   ; CHECK-NEXT: bb.11:
  66   ; CHECK-NEXT:   $sgpr0_sgpr1 = S_ANDN2_B64 $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc
  67   bb.0:
  68     $sgpr0 = S_MOV_B32_term $sgpr1
  69
  70   bb.1:
  71     $sgpr0 = S_MOV_B32_term 0
  72
  73   bb.3:
  74     $sgpr0 = S_MOV_B32_term &SYMBOL
  75
  76   bb.4:
  77     $sgpr0_sgpr1 = S_MOV_B64_term $sgpr2_sgpr3
  78
  79   bb.5:
  80     $sgpr0_sgpr1 = S_MOV_B64_term 0
  81
  82   bb.6:
  83     $sgpr0_sgpr1 = S_MOV_B64_term &SYMBOL
  84
  85   bb.7:
  86     $sgpr0 = S_XOR_B32_term $sgpr1, $sgpr2, implicit-def $scc
  87
  88   bb.8:
  89     $sgpr0_sgpr1 = S_XOR_B64_term $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc
  90
  91   bb.9:
  92     $sgpr0 = S_OR_B32_term $sgpr1, $sgpr2, implicit-def $scc
  93
  94   bb.10:
  95     $sgpr0_sgpr1 = S_OR_B64_term $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc
  96
  97   bb.11:
  98     $sgpr0 = S_ANDN2_B32_term $sgpr1, $sgpr2, implicit-def $scc
  99
 100   bb.12:
 101     $sgpr0_sgpr1 = S_ANDN2_B64_term $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc
 102 ...