| blob | 0c9bf2ac2f76874e7d875d977632989e6425a070 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s -check-prefixes=SI
3 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -denormal-fp-math-f32=preserve-sign < %s | FileCheck %s -check-prefixes=VI
4 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=fiji -denormal-fp-math-f32=ieee < %s | FileCheck %s -check-prefixes=GCN
5 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=gfx1030 -denormal-fp-math-f32=ieee < %s | FileCheck %s -check-prefixes=GFX1030
6 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefixes=EG
8 define amdgpu_kernel void @udiv_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
9 ; SI-LABEL: udiv_i32:
10 ; SI: ; %bb.0:
11 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
12 ; SI-NEXT: s_mov_b32 s7, 0xf000
13 ; SI-NEXT: s_mov_b32 s6, -1
14 ; SI-NEXT: s_mov_b32 s10, s6
15 ; SI-NEXT: s_mov_b32 s11, s7
16 ; SI-NEXT: s_waitcnt lgkmcnt(0)
17 ; SI-NEXT: s_mov_b32 s8, s2
18 ; SI-NEXT: s_mov_b32 s9, s3
19 ; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
20 ; SI-NEXT: s_mov_b32 s4, s0
21 ; SI-NEXT: s_mov_b32 s5, s1
22 ; SI-NEXT: s_waitcnt vmcnt(0)
23 ; SI-NEXT: v_cvt_f32_u32_e32 v2, v1
24 ; SI-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
25 ; SI-NEXT: v_rcp_iflag_f32_e32 v2, v2
26 ; SI-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
27 ; SI-NEXT: v_cvt_u32_f32_e32 v2, v2
28 ; SI-NEXT: v_mul_lo_u32 v3, v3, v2
29 ; SI-NEXT: v_mul_hi_u32 v3, v2, v3
30 ; SI-NEXT: v_add_i32_e32 v2, vcc, v2, v3
31 ; SI-NEXT: v_mul_hi_u32 v2, v0, v2
32 ; SI-NEXT: v_mul_lo_u32 v3, v2, v1
33 ; SI-NEXT: v_add_i32_e32 v4, vcc, 1, v2
34 ; SI-NEXT: v_subrev_i32_e32 v0, vcc, v3, v0
35 ; SI-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v1
36 ; SI-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1]
37 ; SI-NEXT: v_subrev_i32_e32 v3, vcc, v1, v0
38 ; SI-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1]
39 ; SI-NEXT: v_add_i32_e32 v3, vcc, 1, v2
40 ; SI-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
41 ; SI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
42 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
43 ; SI-NEXT: s_endpgm
44 ;
45 ; VI-LABEL: udiv_i32:
46 ; VI: ; %bb.0:
47 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
48 ; VI-NEXT: s_mov_b32 s7, 0xf000
49 ; VI-NEXT: s_mov_b32 s6, -1
50 ; VI-NEXT: s_mov_b32 s10, s6
51 ; VI-NEXT: s_mov_b32 s11, s7
52 ; VI-NEXT: s_waitcnt lgkmcnt(0)
53 ; VI-NEXT: s_mov_b32 s8, s2
54 ; VI-NEXT: s_mov_b32 s9, s3
55 ; VI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
56 ; VI-NEXT: s_mov_b32 s4, s0
57 ; VI-NEXT: s_mov_b32 s5, s1
58 ; VI-NEXT: s_waitcnt vmcnt(0)
59 ; VI-NEXT: v_cvt_f32_u32_e32 v2, v1
60 ; VI-NEXT: v_sub_u32_e32 v3, vcc, 0, v1
61 ; VI-NEXT: v_rcp_iflag_f32_e32 v2, v2
62 ; VI-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
63 ; VI-NEXT: v_cvt_u32_f32_e32 v2, v2
64 ; VI-NEXT: v_mul_lo_u32 v3, v3, v2
65 ; VI-NEXT: v_mul_hi_u32 v3, v2, v3
66 ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v3
67 ; VI-NEXT: v_mul_hi_u32 v2, v0, v2
68 ; VI-NEXT: v_mul_lo_u32 v3, v2, v1
69 ; VI-NEXT: v_add_u32_e32 v4, vcc, 1, v2
70 ; VI-NEXT: v_subrev_u32_e32 v0, vcc, v3, v0
71 ; VI-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v1
72 ; VI-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1]
73 ; VI-NEXT: v_subrev_u32_e32 v3, vcc, v1, v0
74 ; VI-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1]
75 ; VI-NEXT: v_add_u32_e32 v3, vcc, 1, v2
76 ; VI-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
77 ; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
78 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
79 ; VI-NEXT: s_endpgm
80 ;
81 ; GCN-LABEL: udiv_i32:
82 ; GCN: ; %bb.0:
83 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
84 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
85 ; GCN-NEXT: v_mov_b32_e32 v0, s2
86 ; GCN-NEXT: v_mov_b32_e32 v1, s3
87 ; GCN-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
88 ; GCN-NEXT: s_waitcnt vmcnt(0)
89 ; GCN-NEXT: v_cvt_f32_u32_e32 v2, v1
90 ; GCN-NEXT: v_sub_u32_e32 v3, vcc, 0, v1
91 ; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2
92 ; GCN-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
93 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
94 ; GCN-NEXT: v_mul_lo_u32 v3, v3, v2
95 ; GCN-NEXT: v_mul_hi_u32 v3, v2, v3
96 ; GCN-NEXT: v_add_u32_e32 v2, vcc, v2, v3
97 ; GCN-NEXT: v_mul_hi_u32 v4, v0, v2
98 ; GCN-NEXT: v_mov_b32_e32 v2, s0
99 ; GCN-NEXT: v_mov_b32_e32 v3, s1
100 ; GCN-NEXT: v_mul_lo_u32 v5, v4, v1
101 ; GCN-NEXT: v_add_u32_e32 v6, vcc, 1, v4
102 ; GCN-NEXT: v_subrev_u32_e32 v0, vcc, v5, v0
103 ; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v1
104 ; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v6, s[0:1]
105 ; GCN-NEXT: v_subrev_u32_e32 v5, vcc, v1, v0
106 ; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v5, s[0:1]
107 ; GCN-NEXT: v_add_u32_e32 v5, vcc, 1, v4
108 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
109 ; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
110 ; GCN-NEXT: flat_store_dword v[2:3], v0
111 ; GCN-NEXT: s_endpgm
112 ;
113 ; GFX1030-LABEL: udiv_i32:
114 ; GFX1030: ; %bb.0:
115 ; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
116 ; GFX1030-NEXT: v_mov_b32_e32 v2, 0
117 ; GFX1030-NEXT: s_waitcnt lgkmcnt(0)
118 ; GFX1030-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3]
119 ; GFX1030-NEXT: s_waitcnt vmcnt(0)
120 ; GFX1030-NEXT: v_cvt_f32_u32_e32 v3, v1
121 ; GFX1030-NEXT: v_sub_nc_u32_e32 v4, 0, v1
122 ; GFX1030-NEXT: v_rcp_iflag_f32_e32 v3, v3
123 ; GFX1030-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
124 ; GFX1030-NEXT: v_cvt_u32_f32_e32 v3, v3
125 ; GFX1030-NEXT: v_mul_lo_u32 v4, v4, v3
126 ; GFX1030-NEXT: v_mul_hi_u32 v4, v3, v4
127 ; GFX1030-NEXT: v_add_nc_u32_e32 v3, v3, v4
128 ; GFX1030-NEXT: v_mul_hi_u32 v3, v0, v3
129 ; GFX1030-NEXT: v_mul_lo_u32 v4, v3, v1
130 ; GFX1030-NEXT: v_sub_nc_u32_e32 v0, v0, v4
131 ; GFX1030-NEXT: v_add_nc_u32_e32 v4, 1, v3
132 ; GFX1030-NEXT: v_sub_nc_u32_e32 v5, v0, v1
133 ; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v1
134 ; GFX1030-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
135 ; GFX1030-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
136 ; GFX1030-NEXT: v_add_nc_u32_e32 v4, 1, v3
137 ; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v1
138 ; GFX1030-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc_lo
139 ; GFX1030-NEXT: global_store_dword v2, v0, s[0:1]
140 ; GFX1030-NEXT: s_endpgm
141 ;
142 ; EG-LABEL: udiv_i32:
143 ; EG: ; %bb.0:
144 ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
145 ; EG-NEXT: TEX 0 @6
146 ; EG-NEXT: ALU 17, @9, KC0[CB0:0-32], KC1[]
147 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
148 ; EG-NEXT: CF_END
149 ; EG-NEXT: PAD
150 ; EG-NEXT: Fetch clause starting at 6:
151 ; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1
152 ; EG-NEXT: ALU clause starting at 8:
153 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
154 ; EG-NEXT: ALU clause starting at 9:
155 ; EG-NEXT: SUB_INT T0.W, 0.0, T0.Y,
156 ; EG-NEXT: RECIP_UINT * T0.Z, T0.Y,
157 ; EG-NEXT: MULLO_INT * T0.W, PV.W, PS,
158 ; EG-NEXT: MULHI * T0.W, T0.Z, PS,
159 ; EG-NEXT: ADD_INT * T0.W, T0.Z, PS,
160 ; EG-NEXT: MULHI * T0.Z, T0.X, PV.W,
161 ; EG-NEXT: MULLO_INT * T0.W, PS, T0.Y,
162 ; EG-NEXT: SUB_INT * T0.W, T0.X, PS,
163 ; EG-NEXT: ADD_INT T1.Z, T0.Z, 1,
164 ; EG-NEXT: SETGE_UINT T1.W, PV.W, T0.Y,
165 ; EG-NEXT: SUB_INT * T2.W, PV.W, T0.Y,
166 ; EG-NEXT: CNDE_INT T0.W, PV.W, T0.W, PS,
167 ; EG-NEXT: CNDE_INT * T1.W, PV.W, T0.Z, PV.Z,
168 ; EG-NEXT: ADD_INT T2.W, PS, 1,
169 ; EG-NEXT: SETGE_UINT * T0.W, PV.W, T0.Y,
170 ; EG-NEXT: CNDE_INT T0.X, PS, T1.W, PV.W,
171 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
172 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
173 %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
174 %a = load i32, i32 addrspace(1)* %in
175 %b = load i32, i32 addrspace(1)* %b_ptr
176 %result = udiv i32 %a, %b
177 store i32 %result, i32 addrspace(1)* %out
178 ret void
179 }
181 define amdgpu_kernel void @s_udiv_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
182 ; SI-LABEL: s_udiv_i32:
183 ; SI: ; %bb.0:
184 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
185 ; SI-NEXT: s_mov_b32 s7, 0xf000
186 ; SI-NEXT: s_mov_b32 s6, -1
187 ; SI-NEXT: s_waitcnt lgkmcnt(0)
188 ; SI-NEXT: v_cvt_f32_u32_e32 v0, s3
189 ; SI-NEXT: s_sub_i32 s4, 0, s3
190 ; SI-NEXT: s_mov_b32 s5, s1
191 ; SI-NEXT: v_rcp_iflag_f32_e32 v0, v0
192 ; SI-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
193 ; SI-NEXT: v_cvt_u32_f32_e32 v0, v0
194 ; SI-NEXT: v_mul_lo_u32 v1, s4, v0
195 ; SI-NEXT: s_mov_b32 s4, s0
196 ; SI-NEXT: v_mul_hi_u32 v1, v0, v1
197 ; SI-NEXT: v_add_i32_e32 v0, vcc, v0, v1
198 ; SI-NEXT: v_mul_hi_u32 v0, s2, v0
199 ; SI-NEXT: v_mul_lo_u32 v1, v0, s3
200 ; SI-NEXT: v_add_i32_e32 v2, vcc, 1, v0
201 ; SI-NEXT: v_sub_i32_e32 v1, vcc, s2, v1
202 ; SI-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v1
203 ; SI-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
204 ; SI-NEXT: v_subrev_i32_e32 v2, vcc, s3, v1
205 ; SI-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[0:1]
206 ; SI-NEXT: v_add_i32_e32 v2, vcc, 1, v0
207 ; SI-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
208 ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
209 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
210 ; SI-NEXT: s_endpgm
211 ;
212 ; VI-LABEL: s_udiv_i32:
213 ; VI: ; %bb.0:
214 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
215 ; VI-NEXT: s_mov_b32 s7, 0xf000
216 ; VI-NEXT: s_mov_b32 s6, -1
217 ; VI-NEXT: s_waitcnt lgkmcnt(0)
218 ; VI-NEXT: v_cvt_f32_u32_e32 v0, s3
219 ; VI-NEXT: s_sub_i32 s4, 0, s3
220 ; VI-NEXT: s_mov_b32 s5, s1
221 ; VI-NEXT: v_rcp_iflag_f32_e32 v0, v0
222 ; VI-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
223 ; VI-NEXT: v_cvt_u32_f32_e32 v0, v0
224 ; VI-NEXT: v_mul_lo_u32 v1, s4, v0
225 ; VI-NEXT: s_mov_b32 s4, s0
226 ; VI-NEXT: v_mul_hi_u32 v1, v0, v1
227 ; VI-NEXT: v_add_u32_e32 v0, vcc, v1, v0
228 ; VI-NEXT: v_mul_hi_u32 v0, s2, v0
229 ; VI-NEXT: v_mul_lo_u32 v1, v0, s3
230 ; VI-NEXT: v_add_u32_e32 v2, vcc, 1, v0
231 ; VI-NEXT: v_sub_u32_e32 v1, vcc, s2, v1
232 ; VI-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v1
233 ; VI-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
234 ; VI-NEXT: v_subrev_u32_e32 v2, vcc, s3, v1
235 ; VI-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[0:1]
236 ; VI-NEXT: v_add_u32_e32 v2, vcc, 1, v0
237 ; VI-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
238 ; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
239 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
240 ; VI-NEXT: s_endpgm
241 ;
242 ; GCN-LABEL: s_udiv_i32:
243 ; GCN: ; %bb.0:
244 ; GCN-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
245 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
246 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s7
247 ; GCN-NEXT: s_sub_i32 s0, 0, s7
248 ; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
249 ; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
250 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
251 ; GCN-NEXT: v_mul_lo_u32 v1, s0, v0
252 ; GCN-NEXT: v_mul_hi_u32 v1, v0, v1
253 ; GCN-NEXT: v_add_u32_e32 v0, vcc, v1, v0
254 ; GCN-NEXT: v_mul_hi_u32 v0, s6, v0
255 ; GCN-NEXT: v_mul_lo_u32 v1, v0, s7
256 ; GCN-NEXT: v_add_u32_e32 v2, vcc, 1, v0
257 ; GCN-NEXT: v_sub_u32_e32 v1, vcc, s6, v1
258 ; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s7, v1
259 ; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
260 ; GCN-NEXT: v_subrev_u32_e32 v2, vcc, s7, v1
261 ; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[0:1]
262 ; GCN-NEXT: v_add_u32_e32 v2, vcc, 1, v0
263 ; GCN-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
264 ; GCN-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
265 ; GCN-NEXT: v_mov_b32_e32 v0, s4
266 ; GCN-NEXT: v_mov_b32_e32 v1, s5
267 ; GCN-NEXT: flat_store_dword v[0:1], v2
268 ; GCN-NEXT: s_endpgm
269 ;
270 ; GFX1030-LABEL: s_udiv_i32:
271 ; GFX1030: ; %bb.0:
272 ; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
273 ; GFX1030-NEXT: v_mov_b32_e32 v3, 0
274 ; GFX1030-NEXT: s_waitcnt lgkmcnt(0)
275 ; GFX1030-NEXT: v_cvt_f32_u32_e32 v0, s3
276 ; GFX1030-NEXT: s_sub_i32 s5, 0, s3
277 ; GFX1030-NEXT: v_rcp_iflag_f32_e32 v0, v0
278 ; GFX1030-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
279 ; GFX1030-NEXT: v_cvt_u32_f32_e32 v0, v0
280 ; GFX1030-NEXT: v_readfirstlane_b32 s4, v0
281 ; GFX1030-NEXT: s_mul_i32 s5, s5, s4
282 ; GFX1030-NEXT: s_mul_hi_u32 s5, s4, s5
283 ; GFX1030-NEXT: s_add_i32 s4, s4, s5
284 ; GFX1030-NEXT: s_mul_hi_u32 s4, s2, s4
285 ; GFX1030-NEXT: s_mul_i32 s5, s4, s3
286 ; GFX1030-NEXT: s_sub_i32 s2, s2, s5
287 ; GFX1030-NEXT: s_cmp_ge_u32 s2, s3
288 ; GFX1030-NEXT: s_cselect_b32 vcc_lo, -1, 0
289 ; GFX1030-NEXT: s_add_i32 s5, s4, 1
290 ; GFX1030-NEXT: v_mov_b32_e32 v0, s5
291 ; GFX1030-NEXT: s_sub_i32 s5, s2, s3
292 ; GFX1030-NEXT: v_mov_b32_e32 v1, s5
293 ; GFX1030-NEXT: v_cndmask_b32_e32 v0, s4, v0, vcc_lo
294 ; GFX1030-NEXT: v_cndmask_b32_e32 v1, s2, v1, vcc_lo
295 ; GFX1030-NEXT: v_add_nc_u32_e32 v2, 1, v0
296 ; GFX1030-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v1
297 ; GFX1030-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
298 ; GFX1030-NEXT: global_store_dword v3, v0, s[0:1]
299 ; GFX1030-NEXT: s_endpgm
300 ;
301 ; EG-LABEL: s_udiv_i32:
302 ; EG: ; %bb.0:
303 ; EG-NEXT: ALU 17, @4, KC0[CB0:0-32], KC1[]
304 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
305 ; EG-NEXT: CF_END
306 ; EG-NEXT: PAD
307 ; EG-NEXT: ALU clause starting at 4:
308 ; EG-NEXT: SUB_INT T0.W, 0.0, KC0[2].W,
309 ; EG-NEXT: RECIP_UINT * T0.X, KC0[2].W,
310 ; EG-NEXT: MULLO_INT * T0.Y, PV.W, PS,
311 ; EG-NEXT: MULHI * T0.Y, T0.X, PS,
312 ; EG-NEXT: ADD_INT * T0.W, T0.X, PS,
313 ; EG-NEXT: MULHI * T0.X, KC0[2].Z, PV.W,
314 ; EG-NEXT: MULLO_INT * T0.Y, PS, KC0[2].W,
315 ; EG-NEXT: SUB_INT * T0.W, KC0[2].Z, PS,
316 ; EG-NEXT: SUB_INT T0.Z, PV.W, KC0[2].W,
317 ; EG-NEXT: SETGE_UINT T1.W, PV.W, KC0[2].W,
318 ; EG-NEXT: ADD_INT * T2.W, T0.X, 1,
319 ; EG-NEXT: CNDE_INT T2.W, PV.W, T0.X, PS,
320 ; EG-NEXT: CNDE_INT * T0.W, PV.W, T0.W, PV.Z,
321 ; EG-NEXT: SETGE_UINT T0.W, PS, KC0[2].W,
322 ; EG-NEXT: ADD_INT * T1.W, PV.W, 1,
323 ; EG-NEXT: CNDE_INT T0.X, PV.W, T2.W, PS,
324 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
325 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
326 %result = udiv i32 %a, %b
327 store i32 %result, i32 addrspace(1)* %out
328 ret void
329 }
332 ; The code generated by udiv is long and complex and may frequently
333 ; change. The goal of this test is to make sure the ISel doesn't fail
334 ; when it gets a v4i32 udiv
335 define amdgpu_kernel void @udiv_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
336 ; SI-LABEL: udiv_v2i32:
337 ; SI: ; %bb.0:
338 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
339 ; SI-NEXT: s_mov_b32 s7, 0xf000
340 ; SI-NEXT: s_mov_b32 s6, -1
341 ; SI-NEXT: s_mov_b32 s10, s6
342 ; SI-NEXT: s_mov_b32 s11, s7
343 ; SI-NEXT: s_waitcnt lgkmcnt(0)
344 ; SI-NEXT: s_mov_b32 s8, s2
345 ; SI-NEXT: s_mov_b32 s9, s3
346 ; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
347 ; SI-NEXT: s_mov_b32 s4, s0
348 ; SI-NEXT: s_mov_b32 s5, s1
349 ; SI-NEXT: s_waitcnt vmcnt(0)
350 ; SI-NEXT: v_cvt_f32_u32_e32 v4, v2
351 ; SI-NEXT: v_cvt_f32_u32_e32 v5, v3
352 ; SI-NEXT: v_sub_i32_e32 v6, vcc, 0, v2
353 ; SI-NEXT: v_rcp_iflag_f32_e32 v4, v4
354 ; SI-NEXT: v_rcp_iflag_f32_e32 v5, v5
355 ; SI-NEXT: v_sub_i32_e32 v7, vcc, 0, v3
356 ; SI-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
357 ; SI-NEXT: v_mul_f32_e32 v5, 0x4f7ffffe, v5
358 ; SI-NEXT: v_cvt_u32_f32_e32 v4, v4
359 ; SI-NEXT: v_cvt_u32_f32_e32 v5, v5
360 ; SI-NEXT: v_mul_lo_u32 v6, v6, v4
361 ; SI-NEXT: v_mul_lo_u32 v7, v7, v5
362 ; SI-NEXT: v_mul_hi_u32 v6, v4, v6
363 ; SI-NEXT: v_mul_hi_u32 v7, v5, v7
364 ; SI-NEXT: v_add_i32_e32 v4, vcc, v6, v4
365 ; SI-NEXT: v_add_i32_e32 v5, vcc, v7, v5
366 ; SI-NEXT: v_mul_hi_u32 v4, v0, v4
367 ; SI-NEXT: v_mul_hi_u32 v5, v1, v5
368 ; SI-NEXT: v_mul_lo_u32 v6, v4, v2
369 ; SI-NEXT: v_mul_lo_u32 v8, v5, v3
370 ; SI-NEXT: v_add_i32_e32 v7, vcc, 1, v4
371 ; SI-NEXT: v_subrev_i32_e32 v0, vcc, v6, v0
372 ; SI-NEXT: v_sub_i32_e32 v1, vcc, v1, v8
373 ; SI-NEXT: v_add_i32_e32 v9, vcc, 1, v5
374 ; SI-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v2
375 ; SI-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v3
376 ; SI-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[0:1]
377 ; SI-NEXT: v_subrev_i32_e32 v6, vcc, v2, v0
378 ; SI-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[2:3]
379 ; SI-NEXT: v_subrev_i32_e32 v7, vcc, v3, v1
380 ; SI-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[0:1]
381 ; SI-NEXT: v_add_i32_e32 v6, vcc, 1, v4
382 ; SI-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[2:3]
383 ; SI-NEXT: v_add_i32_e32 v7, vcc, 1, v5
384 ; SI-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
385 ; SI-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc
386 ; SI-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
387 ; SI-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc
388 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
389 ; SI-NEXT: s_endpgm
390 ;
391 ; VI-LABEL: udiv_v2i32:
392 ; VI: ; %bb.0:
393 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
394 ; VI-NEXT: s_mov_b32 s7, 0xf000
395 ; VI-NEXT: s_mov_b32 s6, -1
396 ; VI-NEXT: s_mov_b32 s10, s6
397 ; VI-NEXT: s_mov_b32 s11, s7
398 ; VI-NEXT: s_waitcnt lgkmcnt(0)
399 ; VI-NEXT: s_mov_b32 s8, s2
400 ; VI-NEXT: s_mov_b32 s9, s3
401 ; VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
402 ; VI-NEXT: s_mov_b32 s4, s0
403 ; VI-NEXT: s_mov_b32 s5, s1
404 ; VI-NEXT: s_waitcnt vmcnt(0)
405 ; VI-NEXT: v_cvt_f32_u32_e32 v4, v2
406 ; VI-NEXT: v_cvt_f32_u32_e32 v5, v3
407 ; VI-NEXT: v_sub_u32_e32 v6, vcc, 0, v2
408 ; VI-NEXT: v_rcp_iflag_f32_e32 v4, v4
409 ; VI-NEXT: v_rcp_iflag_f32_e32 v5, v5
410 ; VI-NEXT: v_sub_u32_e32 v7, vcc, 0, v3
411 ; VI-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
412 ; VI-NEXT: v_mul_f32_e32 v5, 0x4f7ffffe, v5
413 ; VI-NEXT: v_cvt_u32_f32_e32 v4, v4
414 ; VI-NEXT: v_cvt_u32_f32_e32 v5, v5
415 ; VI-NEXT: v_mul_lo_u32 v6, v6, v4
416 ; VI-NEXT: v_mul_lo_u32 v7, v7, v5
417 ; VI-NEXT: v_mul_hi_u32 v6, v4, v6
418 ; VI-NEXT: v_mul_hi_u32 v7, v5, v7
419 ; VI-NEXT: v_add_u32_e32 v4, vcc, v6, v4
420 ; VI-NEXT: v_add_u32_e32 v5, vcc, v7, v5
421 ; VI-NEXT: v_mul_hi_u32 v4, v0, v4
422 ; VI-NEXT: v_mul_hi_u32 v5, v1, v5
423 ; VI-NEXT: v_mul_lo_u32 v6, v4, v2
424 ; VI-NEXT: v_mul_lo_u32 v8, v5, v3
425 ; VI-NEXT: v_add_u32_e32 v7, vcc, 1, v4
426 ; VI-NEXT: v_sub_u32_e32 v0, vcc, v0, v6
427 ; VI-NEXT: v_subrev_u32_e32 v1, vcc, v8, v1
428 ; VI-NEXT: v_add_u32_e32 v9, vcc, 1, v5
429 ; VI-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v2
430 ; VI-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v3
431 ; VI-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[0:1]
432 ; VI-NEXT: v_sub_u32_e32 v6, vcc, v0, v2
433 ; VI-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[2:3]
434 ; VI-NEXT: v_subrev_u32_e32 v7, vcc, v3, v1
435 ; VI-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[0:1]
436 ; VI-NEXT: v_add_u32_e32 v6, vcc, 1, v4
437 ; VI-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[2:3]
438 ; VI-NEXT: v_add_u32_e32 v7, vcc, 1, v5
439 ; VI-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
440 ; VI-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc
441 ; VI-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
442 ; VI-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc
443 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
444 ; VI-NEXT: s_endpgm
445 ;
446 ; GCN-LABEL: udiv_v2i32:
447 ; GCN: ; %bb.0:
448 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
449 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
450 ; GCN-NEXT: v_mov_b32_e32 v0, s2
451 ; GCN-NEXT: v_mov_b32_e32 v1, s3
452 ; GCN-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
453 ; GCN-NEXT: s_waitcnt vmcnt(0)
454 ; GCN-NEXT: v_cvt_f32_u32_e32 v4, v2
455 ; GCN-NEXT: v_cvt_f32_u32_e32 v5, v3
456 ; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v4
457 ; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v5
458 ; GCN-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
459 ; GCN-NEXT: v_cvt_u32_f32_e32 v6, v4
460 ; GCN-NEXT: v_mul_f32_e32 v5, 0x4f7ffffe, v5
461 ; GCN-NEXT: v_cvt_u32_f32_e32 v7, v5
462 ; GCN-NEXT: v_sub_u32_e32 v4, vcc, 0, v2
463 ; GCN-NEXT: v_mul_lo_u32 v5, v4, v6
464 ; GCN-NEXT: v_sub_u32_e32 v4, vcc, 0, v3
465 ; GCN-NEXT: v_mul_lo_u32 v8, v4, v7
466 ; GCN-NEXT: v_mul_hi_u32 v9, v6, v5
467 ; GCN-NEXT: v_mov_b32_e32 v4, s0
468 ; GCN-NEXT: v_mov_b32_e32 v5, s1
469 ; GCN-NEXT: v_mul_hi_u32 v8, v7, v8
470 ; GCN-NEXT: v_add_u32_e32 v6, vcc, v9, v6
471 ; GCN-NEXT: v_mul_hi_u32 v6, v0, v6
472 ; GCN-NEXT: v_add_u32_e32 v7, vcc, v8, v7
473 ; GCN-NEXT: v_mul_hi_u32 v7, v1, v7
474 ; GCN-NEXT: v_mul_lo_u32 v8, v6, v2
475 ; GCN-NEXT: v_add_u32_e32 v9, vcc, 1, v6
476 ; GCN-NEXT: v_mul_lo_u32 v10, v7, v3
477 ; GCN-NEXT: v_sub_u32_e32 v0, vcc, v0, v8
478 ; GCN-NEXT: v_add_u32_e32 v11, vcc, 1, v7
479 ; GCN-NEXT: v_subrev_u32_e32 v1, vcc, v10, v1
480 ; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v2
481 ; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v3
482 ; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v9, s[0:1]
483 ; GCN-NEXT: v_sub_u32_e32 v8, vcc, v0, v2
484 ; GCN-NEXT: v_cndmask_b32_e64 v7, v7, v11, s[2:3]
485 ; GCN-NEXT: v_subrev_u32_e32 v9, vcc, v3, v1
486 ; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v8, s[0:1]
487 ; GCN-NEXT: v_add_u32_e32 v8, vcc, 1, v6
488 ; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v9, s[2:3]
489 ; GCN-NEXT: v_add_u32_e32 v9, vcc, 1, v7
490 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
491 ; GCN-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc
492 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
493 ; GCN-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc
494 ; GCN-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
495 ; GCN-NEXT: s_endpgm
496 ;
497 ; GFX1030-LABEL: udiv_v2i32:
498 ; GFX1030: ; %bb.0:
499 ; GFX1030-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
500 ; GFX1030-NEXT: v_mov_b32_e32 v4, 0
501 ; GFX1030-NEXT: s_waitcnt lgkmcnt(0)
502 ; GFX1030-NEXT: global_load_dwordx4 v[0:3], v4, s[6:7]
503 ; GFX1030-NEXT: s_waitcnt vmcnt(0)
504 ; GFX1030-NEXT: v_cvt_f32_u32_e32 v5, v2
505 ; GFX1030-NEXT: v_cvt_f32_u32_e32 v6, v3
506 ; GFX1030-NEXT: v_sub_nc_u32_e32 v7, 0, v2
507 ; GFX1030-NEXT: v_sub_nc_u32_e32 v8, 0, v3
508 ; GFX1030-NEXT: v_rcp_iflag_f32_e32 v5, v5
509 ; GFX1030-NEXT: v_rcp_iflag_f32_e32 v6, v6
510 ; GFX1030-NEXT: v_mul_f32_e32 v5, 0x4f7ffffe, v5
511 ; GFX1030-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
512 ; GFX1030-NEXT: v_cvt_u32_f32_e32 v5, v5
513 ; GFX1030-NEXT: v_cvt_u32_f32_e32 v6, v6
514 ; GFX1030-NEXT: v_mul_lo_u32 v7, v7, v5
515 ; GFX1030-NEXT: v_mul_lo_u32 v8, v8, v6
516 ; GFX1030-NEXT: v_mul_hi_u32 v7, v5, v7
517 ; GFX1030-NEXT: v_mul_hi_u32 v8, v6, v8
518 ; GFX1030-NEXT: v_add_nc_u32_e32 v5, v5, v7
519 ; GFX1030-NEXT: v_add_nc_u32_e32 v6, v6, v8
520 ; GFX1030-NEXT: v_mul_hi_u32 v5, v0, v5
521 ; GFX1030-NEXT: v_mul_hi_u32 v6, v1, v6
522 ; GFX1030-NEXT: v_mul_lo_u32 v7, v5, v2
523 ; GFX1030-NEXT: v_mul_lo_u32 v8, v6, v3
524 ; GFX1030-NEXT: v_sub_nc_u32_e32 v0, v0, v7
525 ; GFX1030-NEXT: v_add_nc_u32_e32 v7, 1, v5
526 ; GFX1030-NEXT: v_sub_nc_u32_e32 v1, v1, v8
527 ; GFX1030-NEXT: v_add_nc_u32_e32 v8, 1, v6
528 ; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v2
529 ; GFX1030-NEXT: v_sub_nc_u32_e32 v9, v1, v3
530 ; GFX1030-NEXT: v_cmp_ge_u32_e64 s0, v1, v3
531 ; GFX1030-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
532 ; GFX1030-NEXT: v_sub_nc_u32_e32 v7, v0, v2
533 ; GFX1030-NEXT: v_cndmask_b32_e64 v6, v6, v8, s0
534 ; GFX1030-NEXT: v_cndmask_b32_e64 v1, v1, v9, s0
535 ; GFX1030-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc_lo
536 ; GFX1030-NEXT: v_add_nc_u32_e32 v7, 1, v5
537 ; GFX1030-NEXT: v_add_nc_u32_e32 v8, 1, v6
538 ; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v2
539 ; GFX1030-NEXT: v_cndmask_b32_e32 v0, v5, v7, vcc_lo
540 ; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v1, v3
541 ; GFX1030-NEXT: v_cndmask_b32_e32 v1, v6, v8, vcc_lo
542 ; GFX1030-NEXT: global_store_dwordx2 v4, v[0:1], s[4:5]
543 ; GFX1030-NEXT: s_endpgm
544 ;
545 ; EG-LABEL: udiv_v2i32:
546 ; EG: ; %bb.0:
547 ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
548 ; EG-NEXT: TEX 0 @6
549 ; EG-NEXT: ALU 33, @9, KC0[CB0:0-32], KC1[]
550 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XY, T0.X, 1
551 ; EG-NEXT: CF_END
552 ; EG-NEXT: PAD
553 ; EG-NEXT: Fetch clause starting at 6:
554 ; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
555 ; EG-NEXT: ALU clause starting at 8:
556 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
557 ; EG-NEXT: ALU clause starting at 9:
558 ; EG-NEXT: SUB_INT T1.W, 0.0, T0.W,
559 ; EG-NEXT: RECIP_UINT * T1.X, T0.W,
560 ; EG-NEXT: MULLO_INT * T1.Y, PV.W, PS,
561 ; EG-NEXT: SUB_INT T1.W, 0.0, T0.Z,
562 ; EG-NEXT: RECIP_UINT * T1.Z, T0.Z,
563 ; EG-NEXT: MULLO_INT * T1.W, PV.W, PS,
564 ; EG-NEXT: MULHI * T1.W, T1.Z, PS,
565 ; EG-NEXT: ADD_INT T1.W, T1.Z, PS,
566 ; EG-NEXT: MULHI * T1.Y, T1.X, T1.Y,
567 ; EG-NEXT: ADD_INT T2.W, T1.X, PS,
568 ; EG-NEXT: MULHI * T1.X, T0.X, PV.W,
569 ; EG-NEXT: MULHI * T1.Y, T0.Y, PV.W,
570 ; EG-NEXT: MULLO_INT * T1.Z, PS, T0.W,
571 ; EG-NEXT: SUB_INT T1.W, T0.Y, PS,
572 ; EG-NEXT: MULLO_INT * T0.Y, T1.X, T0.Z,
573 ; EG-NEXT: SUB_INT T0.Y, T0.X, PS,
574 ; EG-NEXT: ADD_INT T1.Z, T1.Y, 1,
575 ; EG-NEXT: SETGE_UINT T2.W, PV.W, T0.W,
576 ; EG-NEXT: SUB_INT * T3.W, PV.W, T0.W,
577 ; EG-NEXT: CNDE_INT T0.X, PV.W, T1.W, PS,
578 ; EG-NEXT: CNDE_INT T1.Y, PV.W, T1.Y, PV.Z,
579 ; EG-NEXT: ADD_INT T1.Z, T1.X, 1,
580 ; EG-NEXT: SETGE_UINT T1.W, PV.Y, T0.Z,
581 ; EG-NEXT: SUB_INT * T2.W, PV.Y, T0.Z,
582 ; EG-NEXT: CNDE_INT T0.Y, PV.W, T0.Y, PS,
583 ; EG-NEXT: CNDE_INT T1.Z, PV.W, T1.X, PV.Z,
584 ; EG-NEXT: ADD_INT T1.W, PV.Y, 1,
585 ; EG-NEXT: SETGE_UINT * T0.W, PV.X, T0.W,
586 ; EG-NEXT: CNDE_INT T1.Y, PS, T1.Y, PV.W,
587 ; EG-NEXT: ADD_INT T0.W, PV.Z, 1,
588 ; EG-NEXT: SETGE_UINT * T1.W, PV.Y, T0.Z,
589 ; EG-NEXT: CNDE_INT T1.X, PS, T1.Z, PV.W,
590 ; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
591 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
592 %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
593 %a = load <2 x i32>, <2 x i32> addrspace(1) * %in
594 %b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr
595 %result = udiv <2 x i32> %a, %b
596 store <2 x i32> %result, <2 x i32> addrspace(1)* %out
597 ret void
598 }
600 define amdgpu_kernel void @udiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
601 ; SI-LABEL: udiv_v4i32:
602 ; SI: ; %bb.0:
603 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
604 ; SI-NEXT: s_mov_b32 s11, 0xf000
605 ; SI-NEXT: s_mov_b32 s10, -1
606 ; SI-NEXT: s_mov_b32 s6, s10
607 ; SI-NEXT: s_mov_b32 s7, s11
608 ; SI-NEXT: s_waitcnt lgkmcnt(0)
609 ; SI-NEXT: s_mov_b32 s4, s2
610 ; SI-NEXT: s_mov_b32 s5, s3
611 ; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 0 offset:16
612 ; SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[4:7], 0
613 ; SI-NEXT: s_mov_b32 s8, s0
614 ; SI-NEXT: s_mov_b32 s9, s1
615 ; SI-NEXT: s_waitcnt vmcnt(1)
616 ; SI-NEXT: v_cvt_f32_u32_e32 v8, v0
617 ; SI-NEXT: v_cvt_f32_u32_e32 v10, v1
618 ; SI-NEXT: v_cvt_f32_u32_e32 v12, v2
619 ; SI-NEXT: v_cvt_f32_u32_e32 v14, v3
620 ; SI-NEXT: v_rcp_iflag_f32_e32 v8, v8
621 ; SI-NEXT: v_rcp_iflag_f32_e32 v10, v10
622 ; SI-NEXT: v_rcp_iflag_f32_e32 v12, v12
623 ; SI-NEXT: v_rcp_iflag_f32_e32 v14, v14
624 ; SI-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8
625 ; SI-NEXT: v_mul_f32_e32 v10, 0x4f7ffffe, v10
626 ; SI-NEXT: v_mul_f32_e32 v12, 0x4f7ffffe, v12
627 ; SI-NEXT: v_mul_f32_e32 v14, 0x4f7ffffe, v14
628 ; SI-NEXT: v_cvt_u32_f32_e32 v8, v8
629 ; SI-NEXT: v_cvt_u32_f32_e32 v10, v10
630 ; SI-NEXT: v_cvt_u32_f32_e32 v12, v12
631 ; SI-NEXT: v_cvt_u32_f32_e32 v14, v14
632 ; SI-NEXT: v_sub_i32_e32 v9, vcc, 0, v0
633 ; SI-NEXT: v_sub_i32_e32 v11, vcc, 0, v1
634 ; SI-NEXT: v_sub_i32_e32 v13, vcc, 0, v2
635 ; SI-NEXT: v_sub_i32_e32 v15, vcc, 0, v3
636 ; SI-NEXT: v_mul_lo_u32 v9, v9, v8
637 ; SI-NEXT: v_mul_lo_u32 v11, v11, v10
638 ; SI-NEXT: v_mul_lo_u32 v13, v13, v12
639 ; SI-NEXT: v_mul_lo_u32 v15, v15, v14
640 ; SI-NEXT: v_mul_hi_u32 v9, v8, v9
641 ; SI-NEXT: v_mul_hi_u32 v11, v10, v11
642 ; SI-NEXT: v_mul_hi_u32 v13, v12, v13
643 ; SI-NEXT: v_mul_hi_u32 v15, v14, v15
644 ; SI-NEXT: v_add_i32_e32 v8, vcc, v9, v8
645 ; SI-NEXT: v_add_i32_e32 v9, vcc, v11, v10
646 ; SI-NEXT: v_add_i32_e32 v10, vcc, v13, v12
647 ; SI-NEXT: v_add_i32_e32 v11, vcc, v15, v14
648 ; SI-NEXT: s_waitcnt vmcnt(0)
649 ; SI-NEXT: v_mul_hi_u32 v8, v4, v8
650 ; SI-NEXT: v_mul_hi_u32 v9, v5, v9
651 ; SI-NEXT: v_mul_hi_u32 v10, v6, v10
652 ; SI-NEXT: v_mul_hi_u32 v11, v7, v11
653 ; SI-NEXT: v_mul_lo_u32 v12, v8, v0
654 ; SI-NEXT: v_mul_lo_u32 v14, v9, v1
655 ; SI-NEXT: v_mul_lo_u32 v16, v10, v2
656 ; SI-NEXT: v_mul_lo_u32 v18, v11, v3
657 ; SI-NEXT: v_subrev_i32_e32 v4, vcc, v12, v4
658 ; SI-NEXT: v_sub_i32_e32 v5, vcc, v5, v14
659 ; SI-NEXT: v_sub_i32_e32 v6, vcc, v6, v16
660 ; SI-NEXT: v_sub_i32_e32 v7, vcc, v7, v18
661 ; SI-NEXT: v_add_i32_e32 v13, vcc, 1, v8
662 ; SI-NEXT: v_add_i32_e32 v15, vcc, 1, v9
663 ; SI-NEXT: v_add_i32_e32 v17, vcc, 1, v10
664 ; SI-NEXT: v_add_i32_e32 v19, vcc, 1, v11
665 ; SI-NEXT: v_cmp_ge_u32_e64 s[0:1], v4, v0
666 ; SI-NEXT: v_cmp_ge_u32_e64 s[2:3], v5, v1
667 ; SI-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v2
668 ; SI-NEXT: v_cmp_ge_u32_e64 s[6:7], v7, v3
669 ; SI-NEXT: v_cndmask_b32_e64 v8, v8, v13, s[0:1]
670 ; SI-NEXT: v_subrev_i32_e32 v12, vcc, v0, v4
671 ; SI-NEXT: v_cndmask_b32_e64 v9, v9, v15, s[2:3]
672 ; SI-NEXT: v_subrev_i32_e32 v13, vcc, v1, v5
673 ; SI-NEXT: v_cndmask_b32_e64 v10, v10, v17, s[4:5]
674 ; SI-NEXT: v_subrev_i32_e32 v14, vcc, v2, v6
675 ; SI-NEXT: v_cndmask_b32_e64 v11, v11, v19, s[6:7]
676 ; SI-NEXT: v_sub_i32_e32 v15, vcc, v7, v3
677 ; SI-NEXT: v_cndmask_b32_e64 v4, v4, v12, s[0:1]
678 ; SI-NEXT: v_add_i32_e32 v12, vcc, 1, v8
679 ; SI-NEXT: v_cndmask_b32_e64 v5, v5, v13, s[2:3]
680 ; SI-NEXT: v_add_i32_e32 v13, vcc, 1, v9
681 ; SI-NEXT: v_cndmask_b32_e64 v6, v6, v14, s[4:5]
682 ; SI-NEXT: v_add_i32_e32 v14, vcc, 1, v10
683 ; SI-NEXT: v_cndmask_b32_e64 v7, v7, v15, s[6:7]
684 ; SI-NEXT: v_add_i32_e32 v15, vcc, 1, v11
685 ; SI-NEXT: v_cmp_ge_u32_e32 vcc, v4, v0
686 ; SI-NEXT: v_cndmask_b32_e32 v0, v8, v12, vcc
687 ; SI-NEXT: v_cmp_ge_u32_e32 vcc, v5, v1
688 ; SI-NEXT: v_cndmask_b32_e32 v1, v9, v13, vcc
689 ; SI-NEXT: v_cmp_ge_u32_e32 vcc, v6, v2
690 ; SI-NEXT: v_cndmask_b32_e32 v2, v10, v14, vcc
691 ; SI-NEXT: v_cmp_ge_u32_e32 vcc, v7, v3
692 ; SI-NEXT: v_cndmask_b32_e32 v3, v11, v15, vcc
693 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
694 ; SI-NEXT: s_endpgm
695 ;
696 ; VI-LABEL: udiv_v4i32:
697 ; VI: ; %bb.0:
698 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
699 ; VI-NEXT: s_mov_b32 s11, 0xf000
700 ; VI-NEXT: s_mov_b32 s10, -1
701 ; VI-NEXT: s_mov_b32 s6, s10
702 ; VI-NEXT: s_mov_b32 s7, s11
703 ; VI-NEXT: s_waitcnt lgkmcnt(0)
704 ; VI-NEXT: s_mov_b32 s4, s2
705 ; VI-NEXT: s_mov_b32 s5, s3
706 ; VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 0 offset:16
707 ; VI-NEXT: buffer_load_dwordx4 v[4:7], off, s[4:7], 0
708 ; VI-NEXT: s_mov_b32 s8, s0
709 ; VI-NEXT: s_mov_b32 s9, s1
710 ; VI-NEXT: s_waitcnt vmcnt(1)
711 ; VI-NEXT: v_cvt_f32_u32_e32 v8, v0
712 ; VI-NEXT: v_cvt_f32_u32_e32 v10, v1
713 ; VI-NEXT: v_cvt_f32_u32_e32 v12, v2
714 ; VI-NEXT: v_cvt_f32_u32_e32 v14, v3
715 ; VI-NEXT: v_rcp_iflag_f32_e32 v8, v8
716 ; VI-NEXT: v_rcp_iflag_f32_e32 v10, v10
717 ; VI-NEXT: v_rcp_iflag_f32_e32 v12, v12
718 ; VI-NEXT: v_rcp_iflag_f32_e32 v14, v14
719 ; VI-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8
720 ; VI-NEXT: v_mul_f32_e32 v10, 0x4f7ffffe, v10
721 ; VI-NEXT: v_mul_f32_e32 v12, 0x4f7ffffe, v12
722 ; VI-NEXT: v_mul_f32_e32 v14, 0x4f7ffffe, v14
723 ; VI-NEXT: v_cvt_u32_f32_e32 v8, v8
724 ; VI-NEXT: v_cvt_u32_f32_e32 v10, v10
725 ; VI-NEXT: v_cvt_u32_f32_e32 v12, v12
726 ; VI-NEXT: v_cvt_u32_f32_e32 v14, v14
727 ; VI-NEXT: v_sub_u32_e32 v9, vcc, 0, v0
728 ; VI-NEXT: v_sub_u32_e32 v11, vcc, 0, v1
729 ; VI-NEXT: v_sub_u32_e32 v13, vcc, 0, v2
730 ; VI-NEXT: v_sub_u32_e32 v15, vcc, 0, v3
731 ; VI-NEXT: v_mul_lo_u32 v9, v9, v8
732 ; VI-NEXT: v_mul_lo_u32 v11, v11, v10
733 ; VI-NEXT: v_mul_lo_u32 v13, v13, v12
734 ; VI-NEXT: v_mul_lo_u32 v15, v15, v14
735 ; VI-NEXT: v_mul_hi_u32 v9, v8, v9
736 ; VI-NEXT: v_mul_hi_u32 v11, v10, v11
737 ; VI-NEXT: v_mul_hi_u32 v13, v12, v13
738 ; VI-NEXT: v_mul_hi_u32 v15, v14, v15
739 ; VI-NEXT: v_add_u32_e32 v8, vcc, v9, v8
740 ; VI-NEXT: v_add_u32_e32 v9, vcc, v10, v11
741 ; VI-NEXT: v_add_u32_e32 v10, vcc, v12, v13
742 ; VI-NEXT: v_add_u32_e32 v11, vcc, v15, v14
743 ; VI-NEXT: s_waitcnt vmcnt(0)
744 ; VI-NEXT: v_mul_hi_u32 v8, v4, v8
745 ; VI-NEXT: v_mul_hi_u32 v9, v5, v9
746 ; VI-NEXT: v_mul_hi_u32 v10, v6, v10
747 ; VI-NEXT: v_mul_hi_u32 v11, v7, v11
748 ; VI-NEXT: v_mul_lo_u32 v12, v8, v0
749 ; VI-NEXT: v_mul_lo_u32 v14, v9, v1
750 ; VI-NEXT: v_mul_lo_u32 v16, v10, v2
751 ; VI-NEXT: v_mul_lo_u32 v18, v11, v3
752 ; VI-NEXT: v_sub_u32_e32 v4, vcc, v4, v12
753 ; VI-NEXT: v_subrev_u32_e32 v5, vcc, v14, v5
754 ; VI-NEXT: v_subrev_u32_e32 v6, vcc, v16, v6
755 ; VI-NEXT: v_sub_u32_e32 v7, vcc, v7, v18
756 ; VI-NEXT: v_add_u32_e32 v13, vcc, 1, v8
757 ; VI-NEXT: v_add_u32_e32 v15, vcc, 1, v9
758 ; VI-NEXT: v_add_u32_e32 v17, vcc, 1, v10
759 ; VI-NEXT: v_add_u32_e32 v19, vcc, 1, v11
760 ; VI-NEXT: v_cmp_ge_u32_e64 s[0:1], v4, v0
761 ; VI-NEXT: v_cmp_ge_u32_e64 s[2:3], v5, v1
762 ; VI-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v2
763 ; VI-NEXT: v_cmp_ge_u32_e64 s[6:7], v7, v3
764 ; VI-NEXT: v_cndmask_b32_e64 v8, v8, v13, s[0:1]
765 ; VI-NEXT: v_subrev_u32_e32 v12, vcc, v0, v4
766 ; VI-NEXT: v_cndmask_b32_e64 v9, v9, v15, s[2:3]
767 ; VI-NEXT: v_subrev_u32_e32 v13, vcc, v1, v5
768 ; VI-NEXT: v_cndmask_b32_e64 v10, v10, v17, s[4:5]
769 ; VI-NEXT: v_subrev_u32_e32 v14, vcc, v2, v6
770 ; VI-NEXT: v_cndmask_b32_e64 v11, v11, v19, s[6:7]
771 ; VI-NEXT: v_subrev_u32_e32 v15, vcc, v3, v7
772 ; VI-NEXT: v_cndmask_b32_e64 v4, v4, v12, s[0:1]
773 ; VI-NEXT: v_add_u32_e32 v12, vcc, 1, v8
774 ; VI-NEXT: v_cndmask_b32_e64 v5, v5, v13, s[2:3]
775 ; VI-NEXT: v_add_u32_e32 v13, vcc, 1, v9
776 ; VI-NEXT: v_cndmask_b32_e64 v6, v6, v14, s[4:5]
777 ; VI-NEXT: v_add_u32_e32 v14, vcc, 1, v10
778 ; VI-NEXT: v_cndmask_b32_e64 v7, v7, v15, s[6:7]
779 ; VI-NEXT: v_add_u32_e32 v15, vcc, 1, v11
780 ; VI-NEXT: v_cmp_ge_u32_e32 vcc, v4, v0
781 ; VI-NEXT: v_cndmask_b32_e32 v0, v8, v12, vcc
782 ; VI-NEXT: v_cmp_ge_u32_e32 vcc, v5, v1
783 ; VI-NEXT: v_cndmask_b32_e32 v1, v9, v13, vcc
784 ; VI-NEXT: v_cmp_ge_u32_e32 vcc, v6, v2
785 ; VI-NEXT: v_cndmask_b32_e32 v2, v10, v14, vcc
786 ; VI-NEXT: v_cmp_ge_u32_e32 vcc, v7, v3
787 ; VI-NEXT: v_cndmask_b32_e32 v3, v11, v15, vcc
788 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
789 ; VI-NEXT: s_endpgm
790 ;
791 ; GCN-LABEL: udiv_v4i32:
792 ; GCN: ; %bb.0:
793 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
794 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
795 ; GCN-NEXT: s_add_u32 s4, s2, 16
796 ; GCN-NEXT: s_addc_u32 s5, s3, 0
797 ; GCN-NEXT: v_mov_b32_e32 v0, s4
798 ; GCN-NEXT: v_mov_b32_e32 v1, s5
799 ; GCN-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
800 ; GCN-NEXT: v_mov_b32_e32 v5, s3
801 ; GCN-NEXT: v_mov_b32_e32 v4, s2
802 ; GCN-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
803 ; GCN-NEXT: v_mov_b32_e32 v8, s0
804 ; GCN-NEXT: v_mov_b32_e32 v9, s1
805 ; GCN-NEXT: s_waitcnt vmcnt(1)
806 ; GCN-NEXT: v_cvt_f32_u32_e32 v10, v0
807 ; GCN-NEXT: v_cvt_f32_u32_e32 v12, v1
808 ; GCN-NEXT: v_cvt_f32_u32_e32 v14, v2
809 ; GCN-NEXT: v_cvt_f32_u32_e32 v16, v3
810 ; GCN-NEXT: v_rcp_iflag_f32_e32 v10, v10
811 ; GCN-NEXT: v_rcp_iflag_f32_e32 v12, v12
812 ; GCN-NEXT: v_rcp_iflag_f32_e32 v14, v14
813 ; GCN-NEXT: v_rcp_iflag_f32_e32 v16, v16
814 ; GCN-NEXT: v_mul_f32_e32 v10, 0x4f7ffffe, v10
815 ; GCN-NEXT: v_mul_f32_e32 v12, 0x4f7ffffe, v12
816 ; GCN-NEXT: v_mul_f32_e32 v14, 0x4f7ffffe, v14
817 ; GCN-NEXT: v_mul_f32_e32 v16, 0x4f7ffffe, v16
818 ; GCN-NEXT: v_cvt_u32_f32_e32 v10, v10
819 ; GCN-NEXT: v_cvt_u32_f32_e32 v12, v12
820 ; GCN-NEXT: v_cvt_u32_f32_e32 v14, v14
821 ; GCN-NEXT: v_cvt_u32_f32_e32 v16, v16
822 ; GCN-NEXT: v_sub_u32_e32 v11, vcc, 0, v0
823 ; GCN-NEXT: v_sub_u32_e32 v13, vcc, 0, v1
824 ; GCN-NEXT: v_sub_u32_e32 v15, vcc, 0, v2
825 ; GCN-NEXT: v_sub_u32_e32 v17, vcc, 0, v3
826 ; GCN-NEXT: v_mul_lo_u32 v11, v11, v10
827 ; GCN-NEXT: v_mul_lo_u32 v13, v13, v12
828 ; GCN-NEXT: v_mul_lo_u32 v15, v15, v14
829 ; GCN-NEXT: v_mul_lo_u32 v17, v17, v16
830 ; GCN-NEXT: v_mul_hi_u32 v11, v10, v11
831 ; GCN-NEXT: v_mul_hi_u32 v13, v12, v13
832 ; GCN-NEXT: v_mul_hi_u32 v15, v14, v15
833 ; GCN-NEXT: v_mul_hi_u32 v17, v16, v17
834 ; GCN-NEXT: v_add_u32_e32 v10, vcc, v11, v10
835 ; GCN-NEXT: v_add_u32_e32 v11, vcc, v12, v13
836 ; GCN-NEXT: v_add_u32_e32 v12, vcc, v14, v15
837 ; GCN-NEXT: v_add_u32_e32 v13, vcc, v17, v16
838 ; GCN-NEXT: s_waitcnt vmcnt(0)
839 ; GCN-NEXT: v_mul_hi_u32 v10, v4, v10
840 ; GCN-NEXT: v_mul_hi_u32 v11, v5, v11
841 ; GCN-NEXT: v_mul_hi_u32 v12, v6, v12
842 ; GCN-NEXT: v_mul_hi_u32 v13, v7, v13
843 ; GCN-NEXT: v_mul_lo_u32 v14, v10, v0
844 ; GCN-NEXT: v_mul_lo_u32 v16, v11, v1
845 ; GCN-NEXT: v_mul_lo_u32 v18, v12, v2
846 ; GCN-NEXT: v_mul_lo_u32 v19, v13, v3
847 ; GCN-NEXT: v_sub_u32_e32 v4, vcc, v4, v14
848 ; GCN-NEXT: v_subrev_u32_e32 v5, vcc, v16, v5
849 ; GCN-NEXT: v_subrev_u32_e32 v6, vcc, v18, v6
850 ; GCN-NEXT: v_sub_u32_e32 v7, vcc, v7, v19
851 ; GCN-NEXT: v_add_u32_e32 v15, vcc, 1, v10
852 ; GCN-NEXT: v_add_u32_e32 v17, vcc, 1, v11
853 ; GCN-NEXT: v_add_u32_e32 v14, vcc, 1, v12
854 ; GCN-NEXT: v_add_u32_e32 v16, vcc, 1, v13
855 ; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v4, v0
856 ; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v5, v1
857 ; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v2
858 ; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v7, v3
859 ; GCN-NEXT: v_cndmask_b32_e64 v10, v10, v15, s[0:1]
860 ; GCN-NEXT: v_subrev_u32_e32 v15, vcc, v0, v4
861 ; GCN-NEXT: v_cndmask_b32_e64 v11, v11, v17, s[2:3]
862 ; GCN-NEXT: v_subrev_u32_e32 v17, vcc, v1, v5
863 ; GCN-NEXT: v_cndmask_b32_e64 v12, v12, v14, s[4:5]
864 ; GCN-NEXT: v_subrev_u32_e32 v14, vcc, v2, v6
865 ; GCN-NEXT: v_cndmask_b32_e64 v13, v13, v16, s[6:7]
866 ; GCN-NEXT: v_subrev_u32_e32 v16, vcc, v3, v7
867 ; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v15, s[0:1]
868 ; GCN-NEXT: v_add_u32_e32 v15, vcc, 1, v10
869 ; GCN-NEXT: v_cndmask_b32_e64 v5, v5, v17, s[2:3]
870 ; GCN-NEXT: v_add_u32_e32 v17, vcc, 1, v11
871 ; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v14, s[4:5]
872 ; GCN-NEXT: v_add_u32_e32 v14, vcc, 1, v12
873 ; GCN-NEXT: v_cndmask_b32_e64 v7, v7, v16, s[6:7]
874 ; GCN-NEXT: v_add_u32_e32 v16, vcc, 1, v13
875 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v4, v0
876 ; GCN-NEXT: v_cndmask_b32_e32 v0, v10, v15, vcc
877 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v1
878 ; GCN-NEXT: v_cndmask_b32_e32 v1, v11, v17, vcc
879 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v2
880 ; GCN-NEXT: v_cndmask_b32_e32 v2, v12, v14, vcc
881 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v7, v3
882 ; GCN-NEXT: v_cndmask_b32_e32 v3, v13, v16, vcc
883 ; GCN-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
884 ; GCN-NEXT: s_endpgm
885 ;
886 ; GFX1030-LABEL: udiv_v4i32:
887 ; GFX1030: ; %bb.0:
888 ; GFX1030-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
889 ; GFX1030-NEXT: v_mov_b32_e32 v8, 0
890 ; GFX1030-NEXT: s_waitcnt lgkmcnt(0)
891 ; GFX1030-NEXT: s_clause 0x1
892 ; GFX1030-NEXT: global_load_dwordx4 v[0:3], v8, s[6:7] offset:16
893 ; GFX1030-NEXT: global_load_dwordx4 v[4:7], v8, s[6:7]
894 ; GFX1030-NEXT: s_waitcnt vmcnt(1)
895 ; GFX1030-NEXT: v_cvt_f32_u32_e32 v9, v0
896 ; GFX1030-NEXT: v_cvt_f32_u32_e32 v10, v1
897 ; GFX1030-NEXT: v_cvt_f32_u32_e32 v11, v2
898 ; GFX1030-NEXT: v_cvt_f32_u32_e32 v12, v3
899 ; GFX1030-NEXT: v_sub_nc_u32_e32 v13, 0, v0
900 ; GFX1030-NEXT: v_rcp_iflag_f32_e32 v9, v9
901 ; GFX1030-NEXT: v_rcp_iflag_f32_e32 v10, v10
902 ; GFX1030-NEXT: v_rcp_iflag_f32_e32 v11, v11
903 ; GFX1030-NEXT: v_rcp_iflag_f32_e32 v12, v12
904 ; GFX1030-NEXT: v_sub_nc_u32_e32 v14, 0, v1
905 ; GFX1030-NEXT: v_sub_nc_u32_e32 v15, 0, v2
906 ; GFX1030-NEXT: v_sub_nc_u32_e32 v16, 0, v3
907 ; GFX1030-NEXT: v_mul_f32_e32 v9, 0x4f7ffffe, v9
908 ; GFX1030-NEXT: v_mul_f32_e32 v10, 0x4f7ffffe, v10
909 ; GFX1030-NEXT: v_mul_f32_e32 v11, 0x4f7ffffe, v11
910 ; GFX1030-NEXT: v_mul_f32_e32 v12, 0x4f7ffffe, v12
911 ; GFX1030-NEXT: v_cvt_u32_f32_e32 v9, v9
912 ; GFX1030-NEXT: v_cvt_u32_f32_e32 v10, v10
913 ; GFX1030-NEXT: v_cvt_u32_f32_e32 v11, v11
914 ; GFX1030-NEXT: v_cvt_u32_f32_e32 v12, v12
915 ; GFX1030-NEXT: v_mul_lo_u32 v13, v13, v9
916 ; GFX1030-NEXT: v_mul_lo_u32 v14, v14, v10
917 ; GFX1030-NEXT: v_mul_lo_u32 v15, v15, v11
918 ; GFX1030-NEXT: v_mul_lo_u32 v16, v16, v12
919 ; GFX1030-NEXT: v_mul_hi_u32 v13, v9, v13
920 ; GFX1030-NEXT: v_mul_hi_u32 v14, v10, v14
921 ; GFX1030-NEXT: v_mul_hi_u32 v15, v11, v15
922 ; GFX1030-NEXT: v_mul_hi_u32 v16, v12, v16
923 ; GFX1030-NEXT: v_add_nc_u32_e32 v9, v9, v13
924 ; GFX1030-NEXT: v_add_nc_u32_e32 v10, v10, v14
925 ; GFX1030-NEXT: v_add_nc_u32_e32 v11, v11, v15
926 ; GFX1030-NEXT: v_add_nc_u32_e32 v12, v12, v16
927 ; GFX1030-NEXT: s_waitcnt vmcnt(0)
928 ; GFX1030-NEXT: v_mul_hi_u32 v9, v4, v9
929 ; GFX1030-NEXT: v_mul_hi_u32 v10, v5, v10
930 ; GFX1030-NEXT: v_mul_hi_u32 v11, v6, v11
931 ; GFX1030-NEXT: v_mul_hi_u32 v12, v7, v12
932 ; GFX1030-NEXT: v_mul_lo_u32 v13, v9, v0
933 ; GFX1030-NEXT: v_mul_lo_u32 v14, v10, v1
934 ; GFX1030-NEXT: v_mul_lo_u32 v15, v11, v2
935 ; GFX1030-NEXT: v_mul_lo_u32 v16, v12, v3
936 ; GFX1030-NEXT: v_add_nc_u32_e32 v17, 1, v9
937 ; GFX1030-NEXT: v_add_nc_u32_e32 v18, 1, v10
938 ; GFX1030-NEXT: v_add_nc_u32_e32 v19, 1, v11
939 ; GFX1030-NEXT: v_sub_nc_u32_e32 v4, v4, v13
940 ; GFX1030-NEXT: v_sub_nc_u32_e32 v5, v5, v14
941 ; GFX1030-NEXT: v_sub_nc_u32_e32 v6, v6, v15
942 ; GFX1030-NEXT: v_sub_nc_u32_e32 v7, v7, v16
943 ; GFX1030-NEXT: v_add_nc_u32_e32 v13, 1, v12
944 ; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v4, v0
945 ; GFX1030-NEXT: v_sub_nc_u32_e32 v14, v4, v0
946 ; GFX1030-NEXT: v_cmp_ge_u32_e64 s0, v5, v1
947 ; GFX1030-NEXT: v_sub_nc_u32_e32 v15, v5, v1
948 ; GFX1030-NEXT: v_cmp_ge_u32_e64 s1, v6, v2
949 ; GFX1030-NEXT: v_cndmask_b32_e32 v9, v9, v17, vcc_lo
950 ; GFX1030-NEXT: v_cndmask_b32_e32 v4, v4, v14, vcc_lo
951 ; GFX1030-NEXT: v_cndmask_b32_e64 v10, v10, v18, s0
952 ; GFX1030-NEXT: v_sub_nc_u32_e32 v16, v6, v2
953 ; GFX1030-NEXT: v_cmp_ge_u32_e64 s2, v7, v3
954 ; GFX1030-NEXT: v_add_nc_u32_e32 v14, 1, v9
955 ; GFX1030-NEXT: v_cndmask_b32_e64 v5, v5, v15, s0
956 ; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v4, v0
957 ; GFX1030-NEXT: v_cndmask_b32_e64 v11, v11, v19, s1
958 ; GFX1030-NEXT: v_cndmask_b32_e64 v12, v12, v13, s2
959 ; GFX1030-NEXT: v_sub_nc_u32_e32 v13, v7, v3
960 ; GFX1030-NEXT: v_add_nc_u32_e32 v15, 1, v10
961 ; GFX1030-NEXT: v_cndmask_b32_e64 v6, v6, v16, s1
962 ; GFX1030-NEXT: v_cndmask_b32_e32 v0, v9, v14, vcc_lo
963 ; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v5, v1
964 ; GFX1030-NEXT: v_add_nc_u32_e32 v16, 1, v11
965 ; GFX1030-NEXT: v_cndmask_b32_e64 v7, v7, v13, s2
966 ; GFX1030-NEXT: v_add_nc_u32_e32 v13, 1, v12
967 ; GFX1030-NEXT: v_cndmask_b32_e32 v1, v10, v15, vcc_lo
968 ; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v6, v2
969 ; GFX1030-NEXT: v_cndmask_b32_e32 v2, v11, v16, vcc_lo
970 ; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v7, v3
971 ; GFX1030-NEXT: v_cndmask_b32_e32 v3, v12, v13, vcc_lo
972 ; GFX1030-NEXT: global_store_dwordx4 v8, v[0:3], s[4:5]
973 ; GFX1030-NEXT: s_endpgm
974 ;
975 ; EG-LABEL: udiv_v4i32:
976 ; EG: ; %bb.0:
977 ; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
978 ; EG-NEXT: TEX 1 @6
979 ; EG-NEXT: ALU 65, @11, KC0[CB0:0-32], KC1[]
980 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T0.X, 1
981 ; EG-NEXT: CF_END
982 ; EG-NEXT: PAD
983 ; EG-NEXT: Fetch clause starting at 6:
984 ; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1
985 ; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
986 ; EG-NEXT: ALU clause starting at 10:
987 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
988 ; EG-NEXT: ALU clause starting at 11:
989 ; EG-NEXT: SUB_INT T2.W, 0.0, T1.W,
990 ; EG-NEXT: RECIP_UINT * T2.X, T1.W,
991 ; EG-NEXT: MULLO_INT * T2.Y, PV.W, PS,
992 ; EG-NEXT: MULHI * T2.Y, T2.X, PS,
993 ; EG-NEXT: ADD_INT * T2.W, T2.X, PS,
994 ; EG-NEXT: MULHI * T2.X, T0.W, PV.W,
995 ; EG-NEXT: MULLO_INT * T2.Y, PS, T1.W,
996 ; EG-NEXT: SUB_INT T2.W, 0.0, T1.X,
997 ; EG-NEXT: RECIP_UINT * T2.Z, T1.X,
998 ; EG-NEXT: MULLO_INT * T2.W, PV.W, PS,
999 ; EG-NEXT: SUB_INT T3.W, 0.0, T1.Y,
1000 ; EG-NEXT: RECIP_UINT * T3.X, T1.Y,
1001 ; EG-NEXT: MULLO_INT * T3.Y, PV.W, PS,
1002 ; EG-NEXT: SUB_INT T3.W, 0.0, T1.Z,
1003 ; EG-NEXT: RECIP_UINT * T3.Z, T1.Z,
1004 ; EG-NEXT: MULLO_INT * T3.W, PV.W, PS,
1005 ; EG-NEXT: MULHI * T3.W, T3.Z, PS,
1006 ; EG-NEXT: ADD_INT T3.W, T3.Z, PS,
1007 ; EG-NEXT: MULHI * T3.Y, T3.X, T3.Y,
1008 ; EG-NEXT: ADD_INT T4.W, T3.X, PS,
1009 ; EG-NEXT: MULHI * T3.X, T0.Z, PV.W,
1010 ; EG-NEXT: MULHI * T3.Y, T0.Y, PV.W,
1011 ; EG-NEXT: MULLO_INT * T3.Z, PS, T1.Y,
1012 ; EG-NEXT: SUB_INT T3.W, T0.Y, PS,
1013 ; EG-NEXT: MULLO_INT * T0.Y, T3.X, T1.Z,
1014 ; EG-NEXT: SUB_INT T4.X, T0.Z, PS,
1015 ; EG-NEXT: ADD_INT T0.Y, T3.Y, 1,
1016 ; EG-NEXT: SETGE_UINT T0.Z, PV.W, T1.Y,
1017 ; EG-NEXT: SUB_INT T4.W, PV.W, T1.Y,
1018 ; EG-NEXT: MULHI * T2.W, T2.Z, T2.W,
1019 ; EG-NEXT: CNDE_INT T5.X, PV.Z, T3.W, PV.W,
1020 ; EG-NEXT: CNDE_INT T0.Y, PV.Z, T3.Y, PV.Y, BS:VEC_021/SCL_122
1021 ; EG-NEXT: SETGE_UINT T0.Z, PV.X, T1.Z,
1022 ; EG-NEXT: ADD_INT T2.W, T2.Z, PS,
1023 ; EG-NEXT: SUB_INT * T0.W, T0.W, T2.Y,
1024 ; EG-NEXT: ADD_INT T6.X, T3.X, 1,
1025 ; EG-NEXT: ADD_INT T2.Y, T2.X, 1, BS:VEC_120/SCL_212
1026 ; EG-NEXT: SETGE_UINT T2.Z, PS, T1.W,
1027 ; EG-NEXT: SUB_INT T3.W, PS, T1.W,
1028 ; EG-NEXT: MULHI * T2.W, T0.X, PV.W,
1029 ; EG-NEXT: SUB_INT T7.X, T4.X, T1.Z,
1030 ; EG-NEXT: CNDE_INT T3.Y, PV.Z, T0.W, PV.W,
1031 ; EG-NEXT: CNDE_INT T2.Z, PV.Z, T2.X, PV.Y,
1032 ; EG-NEXT: CNDE_INT * T0.W, T0.Z, T3.X, PV.X, BS:VEC_021/SCL_122
1033 ; EG-NEXT: MULLO_INT * T2.X, T2.W, T1.X,
1034 ; EG-NEXT: ADD_INT T3.X, T0.W, 1,
1035 ; EG-NEXT: ADD_INT T2.Y, T2.Z, 1,
1036 ; EG-NEXT: SETGE_UINT T3.Z, T3.Y, T1.W,
1037 ; EG-NEXT: SUB_INT T1.W, T0.X, PS, BS:VEC_201
1038 ; EG-NEXT: CNDE_INT * T3.W, T0.Z, T4.X, T7.X,
1039 ; EG-NEXT: SETGE_UINT T0.X, PS, T1.Z, BS:VEC_021/SCL_122
1040 ; EG-NEXT: ADD_INT T3.Y, T2.W, 1,
1041 ; EG-NEXT: SETGE_UINT T0.Z, PV.W, T1.X,
1042 ; EG-NEXT: SUB_INT T3.W, PV.W, T1.X,
1043 ; EG-NEXT: CNDE_INT * T4.W, PV.Z, T2.Z, PV.Y,
1044 ; EG-NEXT: CNDE_INT T2.X, PV.Z, T1.W, PV.W,
1045 ; EG-NEXT: CNDE_INT T2.Y, PV.Z, T2.W, PV.Y, BS:VEC_021/SCL_122
1046 ; EG-NEXT: CNDE_INT T4.Z, PV.X, T0.W, T3.X, BS:VEC_201
1047 ; EG-NEXT: ADD_INT T0.W, T0.Y, 1,
1048 ; EG-NEXT: SETGE_UINT * T1.W, T5.X, T1.Y,
1049 ; EG-NEXT: CNDE_INT T4.Y, PS, T0.Y, PV.W,
1050 ; EG-NEXT: ADD_INT T0.W, PV.Y, 1,
1051 ; EG-NEXT: SETGE_UINT * T1.W, PV.X, T1.X,
1052 ; EG-NEXT: CNDE_INT T4.X, PS, T2.Y, PV.W,
1053 ; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
1054 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
1055 %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
1056 %a = load <4 x i32>, <4 x i32> addrspace(1) * %in
1057 %b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr
1058 %result = udiv <4 x i32> %a, %b
1059 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
1060 ret void
1061 }
1063 define amdgpu_kernel void @udiv_i32_div_pow2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
1064 ; SI-LABEL: udiv_i32_div_pow2:
1065 ; SI: ; %bb.0:
1066 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
1067 ; SI-NEXT: s_mov_b32 s7, 0xf000
1068 ; SI-NEXT: s_mov_b32 s6, -1
1069 ; SI-NEXT: s_mov_b32 s10, s6
1070 ; SI-NEXT: s_mov_b32 s11, s7
1071 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1072 ; SI-NEXT: s_mov_b32 s8, s2
1073 ; SI-NEXT: s_mov_b32 s9, s3
1074 ; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0
1075 ; SI-NEXT: s_mov_b32 s4, s0
1076 ; SI-NEXT: s_mov_b32 s5, s1
1077 ; SI-NEXT: s_waitcnt vmcnt(0)
1078 ; SI-NEXT: v_lshrrev_b32_e32 v0, 4, v0
1079 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
1080 ; SI-NEXT: s_endpgm
1081 ;
1082 ; VI-LABEL: udiv_i32_div_pow2:
1083 ; VI: ; %bb.0:
1084 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1085 ; VI-NEXT: s_mov_b32 s7, 0xf000
1086 ; VI-NEXT: s_mov_b32 s6, -1
1087 ; VI-NEXT: s_mov_b32 s10, s6
1088 ; VI-NEXT: s_mov_b32 s11, s7
1089 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1090 ; VI-NEXT: s_mov_b32 s8, s2
1091 ; VI-NEXT: s_mov_b32 s9, s3
1092 ; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0
1093 ; VI-NEXT: s_mov_b32 s4, s0
1094 ; VI-NEXT: s_mov_b32 s5, s1
1095 ; VI-NEXT: s_waitcnt vmcnt(0)
1096 ; VI-NEXT: v_lshrrev_b32_e32 v0, 4, v0
1097 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
1098 ; VI-NEXT: s_endpgm
1099 ;
1100 ; GCN-LABEL: udiv_i32_div_pow2:
1101 ; GCN: ; %bb.0:
1102 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
1103 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
1104 ; GCN-NEXT: v_mov_b32_e32 v0, s2
1105 ; GCN-NEXT: v_mov_b32_e32 v1, s3
1106 ; GCN-NEXT: flat_load_dword v2, v[0:1]
1107 ; GCN-NEXT: v_mov_b32_e32 v0, s0
1108 ; GCN-NEXT: v_mov_b32_e32 v1, s1
1109 ; GCN-NEXT: s_waitcnt vmcnt(0)
1110 ; GCN-NEXT: v_lshrrev_b32_e32 v2, 4, v2
1111 ; GCN-NEXT: flat_store_dword v[0:1], v2
1112 ; GCN-NEXT: s_endpgm
1113 ;
1114 ; GFX1030-LABEL: udiv_i32_div_pow2:
1115 ; GFX1030: ; %bb.0:
1116 ; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
1117 ; GFX1030-NEXT: v_mov_b32_e32 v0, 0
1118 ; GFX1030-NEXT: s_waitcnt lgkmcnt(0)
1119 ; GFX1030-NEXT: global_load_dword v1, v0, s[2:3]
1120 ; GFX1030-NEXT: s_waitcnt vmcnt(0)
1121 ; GFX1030-NEXT: v_lshrrev_b32_e32 v1, 4, v1
1122 ; GFX1030-NEXT: global_store_dword v0, v1, s[0:1]
1123 ; GFX1030-NEXT: s_endpgm
1124 ;
1125 ; EG-LABEL: udiv_i32_div_pow2:
1126 ; EG: ; %bb.0:
1127 ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
1128 ; EG-NEXT: TEX 0 @6
1129 ; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]
1130 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
1131 ; EG-NEXT: CF_END
1132 ; EG-NEXT: PAD
1133 ; EG-NEXT: Fetch clause starting at 6:
1134 ; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
1135 ; EG-NEXT: ALU clause starting at 8:
1136 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
1137 ; EG-NEXT: ALU clause starting at 9:
1138 ; EG-NEXT: LSHR T0.X, T0.X, literal.x,
1139 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
1140 ; EG-NEXT: 4(5.605194e-45), 2(2.802597e-45)
1141 %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
1142 %a = load i32, i32 addrspace(1)* %in
1143 %result = udiv i32 %a, 16
1144 store i32 %result, i32 addrspace(1)* %out
1145 ret void
1146 }
1148 define amdgpu_kernel void @udiv_i32_div_k_even(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
1149 ; SI-LABEL: udiv_i32_div_k_even:
1150 ; SI: ; %bb.0:
1151 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
1152 ; SI-NEXT: s_mov_b32 s7, 0xf000
1153 ; SI-NEXT: s_mov_b32 s6, -1
1154 ; SI-NEXT: s_mov_b32 s10, s6
1155 ; SI-NEXT: s_mov_b32 s11, s7
1156 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1157 ; SI-NEXT: s_mov_b32 s8, s2
1158 ; SI-NEXT: s_mov_b32 s9, s3
1159 ; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0
1160 ; SI-NEXT: s_mov_b32 s2, 0xfabbd9c1
1161 ; SI-NEXT: s_mov_b32 s4, s0
1162 ; SI-NEXT: s_mov_b32 s5, s1
1163 ; SI-NEXT: s_waitcnt vmcnt(0)
1164 ; SI-NEXT: v_mul_hi_u32 v0, v0, s2
1165 ; SI-NEXT: v_lshrrev_b32_e32 v0, 25, v0
1166 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
1167 ; SI-NEXT: s_endpgm
1168 ;
1169 ; VI-LABEL: udiv_i32_div_k_even:
1170 ; VI: ; %bb.0:
1171 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1172 ; VI-NEXT: s_mov_b32 s7, 0xf000
1173 ; VI-NEXT: s_mov_b32 s6, -1
1174 ; VI-NEXT: s_mov_b32 s10, s6
1175 ; VI-NEXT: s_mov_b32 s11, s7
1176 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1177 ; VI-NEXT: s_mov_b32 s8, s2
1178 ; VI-NEXT: s_mov_b32 s9, s3
1179 ; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0
1180 ; VI-NEXT: s_mov_b32 s2, 0xfabbd9c1
1181 ; VI-NEXT: s_mov_b32 s4, s0
1182 ; VI-NEXT: s_mov_b32 s5, s1
1183 ; VI-NEXT: s_waitcnt vmcnt(0)
1184 ; VI-NEXT: v_mul_hi_u32 v0, v0, s2
1185 ; VI-NEXT: v_lshrrev_b32_e32 v0, 25, v0
1186 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
1187 ; VI-NEXT: s_endpgm
1188 ;
1189 ; GCN-LABEL: udiv_i32_div_k_even:
1190 ; GCN: ; %bb.0:
1191 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
1192 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
1193 ; GCN-NEXT: v_mov_b32_e32 v0, s2
1194 ; GCN-NEXT: v_mov_b32_e32 v1, s3
1195 ; GCN-NEXT: flat_load_dword v0, v[0:1]
1196 ; GCN-NEXT: s_mov_b32 s2, 0xfabbd9c1
1197 ; GCN-NEXT: v_mov_b32_e32 v1, s1
1198 ; GCN-NEXT: s_waitcnt vmcnt(0)
1199 ; GCN-NEXT: v_mul_hi_u32 v2, v0, s2
1200 ; GCN-NEXT: v_mov_b32_e32 v0, s0
1201 ; GCN-NEXT: v_lshrrev_b32_e32 v2, 25, v2
1202 ; GCN-NEXT: flat_store_dword v[0:1], v2
1203 ; GCN-NEXT: s_endpgm
1204 ;
1205 ; GFX1030-LABEL: udiv_i32_div_k_even:
1206 ; GFX1030: ; %bb.0:
1207 ; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
1208 ; GFX1030-NEXT: v_mov_b32_e32 v0, 0
1209 ; GFX1030-NEXT: s_waitcnt lgkmcnt(0)
1210 ; GFX1030-NEXT: global_load_dword v1, v0, s[2:3]
1211 ; GFX1030-NEXT: s_waitcnt vmcnt(0)
1212 ; GFX1030-NEXT: v_mul_hi_u32 v1, 0xfabbd9c1, v1
1213 ; GFX1030-NEXT: v_lshrrev_b32_e32 v1, 25, v1
1214 ; GFX1030-NEXT: global_store_dword v0, v1, s[0:1]
1215 ; GFX1030-NEXT: s_endpgm
1216 ;
1217 ; EG-LABEL: udiv_i32_div_k_even:
1218 ; EG: ; %bb.0:
1219 ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
1220 ; EG-NEXT: TEX 0 @6
1221 ; EG-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[]
1222 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
1223 ; EG-NEXT: CF_END
1224 ; EG-NEXT: PAD
1225 ; EG-NEXT: Fetch clause starting at 6:
1226 ; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
1227 ; EG-NEXT: ALU clause starting at 8:
1228 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
1229 ; EG-NEXT: ALU clause starting at 9:
1230 ; EG-NEXT: MULHI * T0.X, T0.X, literal.x,
1231 ; EG-NEXT: -88352319(-4.876880e+35), 0(0.000000e+00)
1232 ; EG-NEXT: LSHR T0.X, PS, literal.x,
1233 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
1234 ; EG-NEXT: 25(3.503246e-44), 2(2.802597e-45)
1235 %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
1236 %a = load i32, i32 addrspace(1)* %in
1237 %result = udiv i32 %a, 34259182
1238 store i32 %result, i32 addrspace(1)* %out
1239 ret void
1240 }
1242 define amdgpu_kernel void @udiv_i32_div_k_odd(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
1243 ; SI-LABEL: udiv_i32_div_k_odd:
1244 ; SI: ; %bb.0:
1245 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
1246 ; SI-NEXT: s_mov_b32 s7, 0xf000
1247 ; SI-NEXT: s_mov_b32 s6, -1
1248 ; SI-NEXT: s_mov_b32 s10, s6
1249 ; SI-NEXT: s_mov_b32 s11, s7
1250 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1251 ; SI-NEXT: s_mov_b32 s8, s2
1252 ; SI-NEXT: s_mov_b32 s9, s3
1253 ; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0
1254 ; SI-NEXT: s_mov_b32 s2, 0x7d5deca3
1255 ; SI-NEXT: s_mov_b32 s4, s0
1256 ; SI-NEXT: s_mov_b32 s5, s1
1257 ; SI-NEXT: s_waitcnt vmcnt(0)
1258 ; SI-NEXT: v_mul_hi_u32 v0, v0, s2
1259 ; SI-NEXT: v_lshrrev_b32_e32 v0, 24, v0
1260 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
1261 ; SI-NEXT: s_endpgm
1262 ;
1263 ; VI-LABEL: udiv_i32_div_k_odd:
1264 ; VI: ; %bb.0:
1265 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1266 ; VI-NEXT: s_mov_b32 s7, 0xf000
1267 ; VI-NEXT: s_mov_b32 s6, -1
1268 ; VI-NEXT: s_mov_b32 s10, s6
1269 ; VI-NEXT: s_mov_b32 s11, s7
1270 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1271 ; VI-NEXT: s_mov_b32 s8, s2
1272 ; VI-NEXT: s_mov_b32 s9, s3
1273 ; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0
1274 ; VI-NEXT: s_mov_b32 s2, 0x7d5deca3
1275 ; VI-NEXT: s_mov_b32 s4, s0
1276 ; VI-NEXT: s_mov_b32 s5, s1
1277 ; VI-NEXT: s_waitcnt vmcnt(0)
1278 ; VI-NEXT: v_mul_hi_u32 v0, v0, s2
1279 ; VI-NEXT: v_lshrrev_b32_e32 v0, 24, v0
1280 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
1281 ; VI-NEXT: s_endpgm
1282 ;
1283 ; GCN-LABEL: udiv_i32_div_k_odd:
1284 ; GCN: ; %bb.0:
1285 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
1286 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
1287 ; GCN-NEXT: v_mov_b32_e32 v0, s2
1288 ; GCN-NEXT: v_mov_b32_e32 v1, s3
1289 ; GCN-NEXT: flat_load_dword v0, v[0:1]
1290 ; GCN-NEXT: s_mov_b32 s2, 0x7d5deca3
1291 ; GCN-NEXT: v_mov_b32_e32 v1, s1
1292 ; GCN-NEXT: s_waitcnt vmcnt(0)
1293 ; GCN-NEXT: v_mul_hi_u32 v2, v0, s2
1294 ; GCN-NEXT: v_mov_b32_e32 v0, s0
1295 ; GCN-NEXT: v_lshrrev_b32_e32 v2, 24, v2
1296 ; GCN-NEXT: flat_store_dword v[0:1], v2
1297 ; GCN-NEXT: s_endpgm
1298 ;
1299 ; GFX1030-LABEL: udiv_i32_div_k_odd:
1300 ; GFX1030: ; %bb.0:
1301 ; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
1302 ; GFX1030-NEXT: v_mov_b32_e32 v0, 0
1303 ; GFX1030-NEXT: s_waitcnt lgkmcnt(0)
1304 ; GFX1030-NEXT: global_load_dword v1, v0, s[2:3]
1305 ; GFX1030-NEXT: s_waitcnt vmcnt(0)
1306 ; GFX1030-NEXT: v_mul_hi_u32 v1, 0x7d5deca3, v1
1307 ; GFX1030-NEXT: v_lshrrev_b32_e32 v1, 24, v1
1308 ; GFX1030-NEXT: global_store_dword v0, v1, s[0:1]
1309 ; GFX1030-NEXT: s_endpgm
1310 ;
1311 ; EG-LABEL: udiv_i32_div_k_odd:
1312 ; EG: ; %bb.0:
1313 ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
1314 ; EG-NEXT: TEX 0 @6
1315 ; EG-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[]
1316 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
1317 ; EG-NEXT: CF_END
1318 ; EG-NEXT: PAD
1319 ; EG-NEXT: Fetch clause starting at 6:
1320 ; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
1321 ; EG-NEXT: ALU clause starting at 8:
1322 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
1323 ; EG-NEXT: ALU clause starting at 9:
1324 ; EG-NEXT: MULHI * T0.X, T0.X, literal.x,
1325 ; EG-NEXT: 2103307427(1.843675e+37), 0(0.000000e+00)
1326 ; EG-NEXT: LSHR T0.X, PS, literal.x,
1327 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
1328 ; EG-NEXT: 24(3.363116e-44), 2(2.802597e-45)
1329 %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
1330 %a = load i32, i32 addrspace(1)* %in
1331 %result = udiv i32 %a, 34259183
1332 store i32 %result, i32 addrspace(1)* %out
1333 ret void
1334 }
1336 define amdgpu_kernel void @v_udiv_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
1337 ; SI-LABEL: v_udiv_i8:
1338 ; SI: ; %bb.0:
1339 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
1340 ; SI-NEXT: s_mov_b32 s7, 0xf000
1341 ; SI-NEXT: s_mov_b32 s6, -1
1342 ; SI-NEXT: s_mov_b32 s10, s6
1343 ; SI-NEXT: s_mov_b32 s11, s7
1344 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1345 ; SI-NEXT: s_mov_b32 s8, s2
1346 ; SI-NEXT: s_mov_b32 s9, s3
1347 ; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0 offset:1
1348 ; SI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0
1349 ; SI-NEXT: s_mov_b32 s4, s0
1350 ; SI-NEXT: s_mov_b32 s5, s1
1351 ; SI-NEXT: s_waitcnt vmcnt(1)
1352 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
1353 ; SI-NEXT: v_rcp_iflag_f32_e32 v2, v0
1354 ; SI-NEXT: s_waitcnt vmcnt(0)
1355 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1
1356 ; SI-NEXT: v_mul_f32_e32 v2, v1, v2
1357 ; SI-NEXT: v_trunc_f32_e32 v2, v2
1358 ; SI-NEXT: v_cvt_u32_f32_e32 v3, v2
1359 ; SI-NEXT: v_mad_f32 v1, -v2, v0, v1
1360 ; SI-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
1361 ; SI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
1362 ; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
1363 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
1364 ; SI-NEXT: s_endpgm
1365 ;
1366 ; VI-LABEL: v_udiv_i8:
1367 ; VI: ; %bb.0:
1368 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1369 ; VI-NEXT: s_mov_b32 s7, 0xf000
1370 ; VI-NEXT: s_mov_b32 s6, -1
1371 ; VI-NEXT: s_mov_b32 s10, s6
1372 ; VI-NEXT: s_mov_b32 s11, s7
1373 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1374 ; VI-NEXT: s_mov_b32 s8, s2
1375 ; VI-NEXT: s_mov_b32 s9, s3
1376 ; VI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0 offset:1
1377 ; VI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0
1378 ; VI-NEXT: s_mov_b32 s4, s0
1379 ; VI-NEXT: s_mov_b32 s5, s1
1380 ; VI-NEXT: s_waitcnt vmcnt(1)
1381 ; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
1382 ; VI-NEXT: v_rcp_iflag_f32_e32 v2, v0
1383 ; VI-NEXT: s_waitcnt vmcnt(0)
1384 ; VI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1
1385 ; VI-NEXT: v_mul_f32_e32 v2, v1, v2
1386 ; VI-NEXT: v_trunc_f32_e32 v2, v2
1387 ; VI-NEXT: v_cvt_u32_f32_e32 v3, v2
1388 ; VI-NEXT: v_mad_f32 v1, -v2, v0, v1
1389 ; VI-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
1390 ; VI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
1391 ; VI-NEXT: v_and_b32_e32 v0, 0xff, v0
1392 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
1393 ; VI-NEXT: s_endpgm
1394 ;
1395 ; GCN-LABEL: v_udiv_i8:
1396 ; GCN: ; %bb.0:
1397 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
1398 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
1399 ; GCN-NEXT: v_mov_b32_e32 v0, s2
1400 ; GCN-NEXT: v_mov_b32_e32 v1, s3
1401 ; GCN-NEXT: flat_load_ushort v2, v[0:1]
1402 ; GCN-NEXT: v_mov_b32_e32 v0, s0
1403 ; GCN-NEXT: v_mov_b32_e32 v1, s1
1404 ; GCN-NEXT: s_waitcnt vmcnt(0)
1405 ; GCN-NEXT: v_cvt_f32_ubyte1_e32 v3, v2
1406 ; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v3
1407 ; GCN-NEXT: v_cvt_f32_ubyte0_e32 v2, v2
1408 ; GCN-NEXT: v_mul_f32_e32 v4, v2, v4
1409 ; GCN-NEXT: v_trunc_f32_e32 v4, v4
1410 ; GCN-NEXT: v_cvt_u32_f32_e32 v5, v4
1411 ; GCN-NEXT: v_mad_f32 v2, -v4, v3, v2
1412 ; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v3
1413 ; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
1414 ; GCN-NEXT: v_and_b32_e32 v2, 0xff, v2
1415 ; GCN-NEXT: flat_store_dword v[0:1], v2
1416 ; GCN-NEXT: s_endpgm
1417 ;
1418 ; GFX1030-LABEL: v_udiv_i8:
1419 ; GFX1030: ; %bb.0:
1420 ; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
1421 ; GFX1030-NEXT: v_mov_b32_e32 v0, 0
1422 ; GFX1030-NEXT: s_waitcnt lgkmcnt(0)
1423 ; GFX1030-NEXT: global_load_ushort v1, v0, s[2:3]
1424 ; GFX1030-NEXT: s_waitcnt vmcnt(0)
1425 ; GFX1030-NEXT: v_cvt_f32_ubyte1_e32 v2, v1
1426 ; GFX1030-NEXT: v_cvt_f32_ubyte0_e32 v1, v1
1427 ; GFX1030-NEXT: v_rcp_iflag_f32_e32 v3, v2
1428 ; GFX1030-NEXT: v_mul_f32_e32 v3, v1, v3
1429 ; GFX1030-NEXT: v_trunc_f32_e32 v3, v3
1430 ; GFX1030-NEXT: v_fma_f32 v1, -v3, v2, v1
1431 ; GFX1030-NEXT: v_cvt_u32_f32_e32 v3, v3
1432 ; GFX1030-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v1|, v2
1433 ; GFX1030-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v3, vcc_lo
1434 ; GFX1030-NEXT: v_and_b32_e32 v1, 0xff, v1
1435 ; GFX1030-NEXT: global_store_dword v0, v1, s[0:1]
1436 ; GFX1030-NEXT: s_endpgm
1437 ;
1438 ; EG-LABEL: v_udiv_i8:
1439 ; EG: ; %bb.0:
1440 ; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
1441 ; EG-NEXT: TEX 1 @6
1442 ; EG-NEXT: ALU 14, @11, KC0[CB0:0-32], KC1[]
1443 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
1444 ; EG-NEXT: CF_END
1445 ; EG-NEXT: PAD
1446 ; EG-NEXT: Fetch clause starting at 6:
1447 ; EG-NEXT: VTX_READ_8 T1.X, T0.X, 1, #1
1448 ; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
1449 ; EG-NEXT: ALU clause starting at 10:
1450 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
1451 ; EG-NEXT: ALU clause starting at 11:
1452 ; EG-NEXT: UINT_TO_FLT * T0.Y, T1.X,
1453 ; EG-NEXT: RECIP_IEEE * T0.Z, PS,
1454 ; EG-NEXT: UINT_TO_FLT * T0.X, T0.X,
1455 ; EG-NEXT: MUL_IEEE * T0.W, PS, T0.Z,
1456 ; EG-NEXT: TRUNC * T0.W, PV.W,
1457 ; EG-NEXT: MULADD_IEEE T1.W, -PV.W, T0.Y, T0.X,
1458 ; EG-NEXT: TRUNC * T0.W, PV.W,
1459 ; EG-NEXT: SETGE * T1.W, |PV.W|, |T0.Y|,
1460 ; EG-NEXT: CNDE T1.W, PV.W, 0.0, literal.x,
1461 ; EG-NEXT: FLT_TO_UINT * T0.X, T0.W,
1462 ; EG-NEXT: 1(1.401298e-45), 0(0.000000e+00)
1463 ; EG-NEXT: ADD_INT * T0.W, PS, PV.W,
1464 ; EG-NEXT: AND_INT T0.X, PV.W, literal.x,
1465 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
1466 ; EG-NEXT: 255(3.573311e-43), 2(2.802597e-45)
1467 %den_ptr = getelementptr i8, i8 addrspace(1)* %in, i8 1
1468 %num = load i8, i8 addrspace(1) * %in
1469 %den = load i8, i8 addrspace(1) * %den_ptr
1470 %result = udiv i8 %num, %den
1471 %result.ext = zext i8 %result to i32
1472 store i32 %result.ext, i32 addrspace(1)* %out
1473 ret void
1474 }
1476 define amdgpu_kernel void @v_udiv_i16(i32 addrspace(1)* %out, i16 addrspace(1)* %in) {
1477 ; SI-LABEL: v_udiv_i16:
1478 ; SI: ; %bb.0:
1479 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
1480 ; SI-NEXT: s_mov_b32 s7, 0xf000
1481 ; SI-NEXT: s_mov_b32 s6, -1
1482 ; SI-NEXT: s_mov_b32 s10, s6
1483 ; SI-NEXT: s_mov_b32 s11, s7
1484 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1485 ; SI-NEXT: s_mov_b32 s8, s2
1486 ; SI-NEXT: s_mov_b32 s9, s3
1487 ; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 0 offset:2
1488 ; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0
1489 ; SI-NEXT: s_mov_b32 s4, s0
1490 ; SI-NEXT: s_mov_b32 s5, s1
1491 ; SI-NEXT: s_waitcnt vmcnt(1)
1492 ; SI-NEXT: v_cvt_f32_u32_e32 v0, v0
1493 ; SI-NEXT: s_waitcnt vmcnt(0)
1494 ; SI-NEXT: v_cvt_f32_u32_e32 v1, v1
1495 ; SI-NEXT: v_rcp_iflag_f32_e32 v2, v0
1496 ; SI-NEXT: v_mul_f32_e32 v2, v1, v2
1497 ; SI-NEXT: v_trunc_f32_e32 v2, v2
1498 ; SI-NEXT: v_cvt_u32_f32_e32 v3, v2
1499 ; SI-NEXT: v_mad_f32 v1, -v2, v0, v1
1500 ; SI-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
1501 ; SI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
1502 ; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
1503 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
1504 ; SI-NEXT: s_endpgm
1505 ;
1506 ; VI-LABEL: v_udiv_i16:
1507 ; VI: ; %bb.0:
1508 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1509 ; VI-NEXT: s_mov_b32 s7, 0xf000
1510 ; VI-NEXT: s_mov_b32 s6, -1
1511 ; VI-NEXT: s_mov_b32 s10, s6
1512 ; VI-NEXT: s_mov_b32 s11, s7
1513 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1514 ; VI-NEXT: s_mov_b32 s8, s2
1515 ; VI-NEXT: s_mov_b32 s9, s3
1516 ; VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0 offset:2
1517 ; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0
1518 ; VI-NEXT: s_mov_b32 s4, s0
1519 ; VI-NEXT: s_mov_b32 s5, s1
1520 ; VI-NEXT: s_waitcnt vmcnt(1)
1521 ; VI-NEXT: v_cvt_f32_u32_e32 v0, v0
1522 ; VI-NEXT: s_waitcnt vmcnt(0)
1523 ; VI-NEXT: v_cvt_f32_u32_e32 v1, v1
1524 ; VI-NEXT: v_rcp_iflag_f32_e32 v2, v0
1525 ; VI-NEXT: v_mul_f32_e32 v2, v1, v2
1526 ; VI-NEXT: v_trunc_f32_e32 v2, v2
1527 ; VI-NEXT: v_cvt_u32_f32_e32 v3, v2
1528 ; VI-NEXT: v_mad_f32 v1, -v2, v0, v1
1529 ; VI-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
1530 ; VI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
1531 ; VI-NEXT: v_and_b32_e32 v0, 0xffff, v0
1532 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
1533 ; VI-NEXT: s_endpgm
1534 ;
1535 ; GCN-LABEL: v_udiv_i16:
1536 ; GCN: ; %bb.0:
1537 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
1538 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
1539 ; GCN-NEXT: s_add_u32 s4, s2, 2
1540 ; GCN-NEXT: s_addc_u32 s5, s3, 0
1541 ; GCN-NEXT: v_mov_b32_e32 v0, s4
1542 ; GCN-NEXT: v_mov_b32_e32 v1, s5
1543 ; GCN-NEXT: flat_load_ushort v2, v[0:1]
1544 ; GCN-NEXT: v_mov_b32_e32 v0, s2
1545 ; GCN-NEXT: v_mov_b32_e32 v1, s3
1546 ; GCN-NEXT: flat_load_ushort v0, v[0:1]
1547 ; GCN-NEXT: v_mov_b32_e32 v1, s1
1548 ; GCN-NEXT: s_waitcnt vmcnt(1)
1549 ; GCN-NEXT: v_cvt_f32_u32_e32 v2, v2
1550 ; GCN-NEXT: s_waitcnt vmcnt(0)
1551 ; GCN-NEXT: v_cvt_f32_u32_e32 v3, v0
1552 ; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2
1553 ; GCN-NEXT: v_mov_b32_e32 v0, s0
1554 ; GCN-NEXT: v_mul_f32_e32 v4, v3, v4
1555 ; GCN-NEXT: v_trunc_f32_e32 v4, v4
1556 ; GCN-NEXT: v_cvt_u32_f32_e32 v5, v4
1557 ; GCN-NEXT: v_mad_f32 v3, -v4, v2, v3
1558 ; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v2
1559 ; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
1560 ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2
1561 ; GCN-NEXT: flat_store_dword v[0:1], v2
1562 ; GCN-NEXT: s_endpgm
1563 ;
1564 ; GFX1030-LABEL: v_udiv_i16:
1565 ; GFX1030: ; %bb.0:
1566 ; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
1567 ; GFX1030-NEXT: v_mov_b32_e32 v0, 0
1568 ; GFX1030-NEXT: s_waitcnt lgkmcnt(0)
1569 ; GFX1030-NEXT: s_clause 0x1
1570 ; GFX1030-NEXT: global_load_ushort v1, v0, s[2:3] offset:2
1571 ; GFX1030-NEXT: global_load_ushort v2, v0, s[2:3]
1572 ; GFX1030-NEXT: s_waitcnt vmcnt(1)
1573 ; GFX1030-NEXT: v_cvt_f32_u32_e32 v1, v1
1574 ; GFX1030-NEXT: s_waitcnt vmcnt(0)
1575 ; GFX1030-NEXT: v_cvt_f32_u32_e32 v2, v2
1576 ; GFX1030-NEXT: v_rcp_iflag_f32_e32 v3, v1
1577 ; GFX1030-NEXT: v_mul_f32_e32 v3, v2, v3
1578 ; GFX1030-NEXT: v_trunc_f32_e32 v3, v3
1579 ; GFX1030-NEXT: v_fma_f32 v2, -v3, v1, v2
1580 ; GFX1030-NEXT: v_cvt_u32_f32_e32 v3, v3
1581 ; GFX1030-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v2|, v1
1582 ; GFX1030-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v3, vcc_lo
1583 ; GFX1030-NEXT: v_and_b32_e32 v1, 0xffff, v1
1584 ; GFX1030-NEXT: global_store_dword v0, v1, s[0:1]
1585 ; GFX1030-NEXT: s_endpgm
1586 ;
1587 ; EG-LABEL: v_udiv_i16:
1588 ; EG: ; %bb.0:
1589 ; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
1590 ; EG-NEXT: TEX 1 @6
1591 ; EG-NEXT: ALU 14, @11, KC0[CB0:0-32], KC1[]
1592 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
1593 ; EG-NEXT: CF_END
1594 ; EG-NEXT: PAD
1595 ; EG-NEXT: Fetch clause starting at 6:
1596 ; EG-NEXT: VTX_READ_16 T1.X, T0.X, 2, #1
1597 ; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #1
1598 ; EG-NEXT: ALU clause starting at 10:
1599 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
1600 ; EG-NEXT: ALU clause starting at 11:
1601 ; EG-NEXT: UINT_TO_FLT * T0.Y, T1.X,
1602 ; EG-NEXT: RECIP_IEEE * T0.Z, PS,
1603 ; EG-NEXT: UINT_TO_FLT * T0.X, T0.X,
1604 ; EG-NEXT: MUL_IEEE * T0.W, PS, T0.Z,
1605 ; EG-NEXT: TRUNC * T0.W, PV.W,
1606 ; EG-NEXT: MULADD_IEEE T1.W, -PV.W, T0.Y, T0.X,
1607 ; EG-NEXT: TRUNC * T0.W, PV.W,
1608 ; EG-NEXT: SETGE * T1.W, |PV.W|, |T0.Y|,
1609 ; EG-NEXT: CNDE T1.W, PV.W, 0.0, literal.x,
1610 ; EG-NEXT: FLT_TO_UINT * T0.X, T0.W,
1611 ; EG-NEXT: 1(1.401298e-45), 0(0.000000e+00)
1612 ; EG-NEXT: ADD_INT * T0.W, PS, PV.W,
1613 ; EG-NEXT: AND_INT T0.X, PV.W, literal.x,
1614 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
1615 ; EG-NEXT: 65535(9.183409e-41), 2(2.802597e-45)
1616 %den_ptr = getelementptr i16, i16 addrspace(1)* %in, i16 1
1617 %num = load i16, i16 addrspace(1) * %in
1618 %den = load i16, i16 addrspace(1) * %den_ptr
1619 %result = udiv i16 %num, %den
1620 %result.ext = zext i16 %result to i32
1621 store i32 %result.ext, i32 addrspace(1)* %out
1622 ret void
1623 }
1625 define amdgpu_kernel void @v_udiv_i23(i32 addrspace(1)* %out, i23 addrspace(1)* %in) {
1626 ; SI-LABEL: v_udiv_i23:
1627 ; SI: ; %bb.0:
1628 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
1629 ; SI-NEXT: s_mov_b32 s7, 0xf000
1630 ; SI-NEXT: s_mov_b32 s6, -1
1631 ; SI-NEXT: s_mov_b32 s10, s6
1632 ; SI-NEXT: s_mov_b32 s11, s7
1633 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1634 ; SI-NEXT: s_mov_b32 s8, s2
1635 ; SI-NEXT: s_mov_b32 s9, s3
1636 ; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0 offset:6
1637 ; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 offset:4
1638 ; SI-NEXT: buffer_load_ubyte v2, off, s[8:11], 0 offset:2
1639 ; SI-NEXT: buffer_load_ushort v3, off, s[8:11], 0
1640 ; SI-NEXT: s_mov_b32 s4, s0
1641 ; SI-NEXT: s_mov_b32 s5, s1
1642 ; SI-NEXT: s_waitcnt vmcnt(3)
1643 ; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
1644 ; SI-NEXT: s_waitcnt vmcnt(2)
1645 ; SI-NEXT: v_or_b32_e32 v0, v1, v0
1646 ; SI-NEXT: v_cvt_f32_u32_e32 v0, v0
1647 ; SI-NEXT: s_waitcnt vmcnt(1)
1648 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
1649 ; SI-NEXT: s_waitcnt vmcnt(0)
1650 ; SI-NEXT: v_or_b32_e32 v1, v3, v1
1651 ; SI-NEXT: v_cvt_f32_u32_e32 v1, v1
1652 ; SI-NEXT: v_rcp_iflag_f32_e32 v2, v0
1653 ; SI-NEXT: v_mul_f32_e32 v2, v1, v2
1654 ; SI-NEXT: v_trunc_f32_e32 v2, v2
1655 ; SI-NEXT: v_cvt_u32_f32_e32 v3, v2
1656 ; SI-NEXT: v_mad_f32 v1, -v2, v0, v1
1657 ; SI-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
1658 ; SI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
1659 ; SI-NEXT: v_and_b32_e32 v0, 0x7fffff, v0
1660 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
1661 ; SI-NEXT: s_endpgm
1662 ;
1663 ; VI-LABEL: v_udiv_i23:
1664 ; VI: ; %bb.0:
1665 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1666 ; VI-NEXT: s_mov_b32 s7, 0xf000
1667 ; VI-NEXT: s_mov_b32 s6, -1
1668 ; VI-NEXT: s_mov_b32 s10, s6
1669 ; VI-NEXT: s_mov_b32 s11, s7
1670 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1671 ; VI-NEXT: s_mov_b32 s8, s2
1672 ; VI-NEXT: s_mov_b32 s9, s3
1673 ; VI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0 offset:6
1674 ; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 offset:4
1675 ; VI-NEXT: buffer_load_ubyte v2, off, s[8:11], 0 offset:2
1676 ; VI-NEXT: buffer_load_ushort v3, off, s[8:11], 0
1677 ; VI-NEXT: s_mov_b32 s4, s0
1678 ; VI-NEXT: s_mov_b32 s5, s1
1679 ; VI-NEXT: s_waitcnt vmcnt(3)
1680 ; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
1681 ; VI-NEXT: s_waitcnt vmcnt(2)
1682 ; VI-NEXT: v_or_b32_e32 v0, v1, v0
1683 ; VI-NEXT: v_cvt_f32_u32_e32 v0, v0
1684 ; VI-NEXT: s_waitcnt vmcnt(1)
1685 ; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
1686 ; VI-NEXT: s_waitcnt vmcnt(0)
1687 ; VI-NEXT: v_or_b32_e32 v1, v3, v1
1688 ; VI-NEXT: v_cvt_f32_u32_e32 v1, v1
1689 ; VI-NEXT: v_rcp_iflag_f32_e32 v2, v0
1690 ; VI-NEXT: v_mul_f32_e32 v2, v1, v2
1691 ; VI-NEXT: v_trunc_f32_e32 v2, v2
1692 ; VI-NEXT: v_cvt_u32_f32_e32 v3, v2
1693 ; VI-NEXT: v_mad_f32 v1, -v2, v0, v1
1694 ; VI-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
1695 ; VI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
1696 ; VI-NEXT: v_and_b32_e32 v0, 0x7fffff, v0
1697 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
1698 ; VI-NEXT: s_endpgm
1699 ;
1700 ; GCN-LABEL: v_udiv_i23:
1701 ; GCN: ; %bb.0:
1702 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
1703 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
1704 ; GCN-NEXT: s_add_u32 s4, s2, 4
1705 ; GCN-NEXT: s_addc_u32 s5, s3, 0
1706 ; GCN-NEXT: s_add_u32 s6, s2, 2
1707 ; GCN-NEXT: s_addc_u32 s7, s3, 0
1708 ; GCN-NEXT: v_mov_b32_e32 v0, s6
1709 ; GCN-NEXT: v_mov_b32_e32 v1, s7
1710 ; GCN-NEXT: s_add_u32 s6, s2, 6
1711 ; GCN-NEXT: s_addc_u32 s7, s3, 0
1712 ; GCN-NEXT: v_mov_b32_e32 v2, s6
1713 ; GCN-NEXT: v_mov_b32_e32 v3, s7
1714 ; GCN-NEXT: v_mov_b32_e32 v4, s4
1715 ; GCN-NEXT: v_mov_b32_e32 v5, s5
1716 ; GCN-NEXT: flat_load_ubyte v6, v[2:3]
1717 ; GCN-NEXT: flat_load_ushort v4, v[4:5]
1718 ; GCN-NEXT: v_mov_b32_e32 v2, s2
1719 ; GCN-NEXT: v_mov_b32_e32 v3, s3
1720 ; GCN-NEXT: flat_load_ubyte v0, v[0:1]
1721 ; GCN-NEXT: flat_load_ushort v1, v[2:3]
1722 ; GCN-NEXT: s_waitcnt vmcnt(3)
1723 ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v6
1724 ; GCN-NEXT: s_waitcnt vmcnt(2)
1725 ; GCN-NEXT: v_or_b32_e32 v2, v4, v2
1726 ; GCN-NEXT: v_cvt_f32_u32_e32 v2, v2
1727 ; GCN-NEXT: s_waitcnt vmcnt(1)
1728 ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
1729 ; GCN-NEXT: s_waitcnt vmcnt(0)
1730 ; GCN-NEXT: v_or_b32_e32 v0, v1, v0
1731 ; GCN-NEXT: v_cvt_f32_u32_e32 v3, v0
1732 ; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2
1733 ; GCN-NEXT: v_mov_b32_e32 v0, s0
1734 ; GCN-NEXT: v_mov_b32_e32 v1, s1
1735 ; GCN-NEXT: v_mul_f32_e32 v4, v3, v4
1736 ; GCN-NEXT: v_trunc_f32_e32 v4, v4
1737 ; GCN-NEXT: v_cvt_u32_f32_e32 v5, v4
1738 ; GCN-NEXT: v_mad_f32 v3, -v4, v2, v3
1739 ; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v2
1740 ; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
1741 ; GCN-NEXT: v_and_b32_e32 v2, 0x7fffff, v2
1742 ; GCN-NEXT: flat_store_dword v[0:1], v2
1743 ; GCN-NEXT: s_endpgm
1744 ;
1745 ; GFX1030-LABEL: v_udiv_i23:
1746 ; GFX1030: ; %bb.0:
1747 ; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
1748 ; GFX1030-NEXT: v_mov_b32_e32 v0, 0
1749 ; GFX1030-NEXT: s_waitcnt lgkmcnt(0)
1750 ; GFX1030-NEXT: s_clause 0x3
1751 ; GFX1030-NEXT: global_load_ubyte v1, v0, s[2:3] offset:6
1752 ; GFX1030-NEXT: global_load_ushort v2, v0, s[2:3] offset:4
1753 ; GFX1030-NEXT: global_load_ubyte v3, v0, s[2:3] offset:2
1754 ; GFX1030-NEXT: global_load_ushort v4, v0, s[2:3]
1755 ; GFX1030-NEXT: s_waitcnt vmcnt(3)
1756 ; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1
1757 ; GFX1030-NEXT: s_waitcnt vmcnt(2)
1758 ; GFX1030-NEXT: v_or_b32_e32 v1, v2, v1
1759 ; GFX1030-NEXT: s_waitcnt vmcnt(1)
1760 ; GFX1030-NEXT: v_lshlrev_b32_e32 v2, 16, v3
1761 ; GFX1030-NEXT: v_cvt_f32_u32_e32 v1, v1
1762 ; GFX1030-NEXT: s_waitcnt vmcnt(0)
1763 ; GFX1030-NEXT: v_or_b32_e32 v2, v4, v2
1764 ; GFX1030-NEXT: v_rcp_iflag_f32_e32 v3, v1
1765 ; GFX1030-NEXT: v_cvt_f32_u32_e32 v2, v2
1766 ; GFX1030-NEXT: v_mul_f32_e32 v3, v2, v3
1767 ; GFX1030-NEXT: v_trunc_f32_e32 v3, v3
1768 ; GFX1030-NEXT: v_fma_f32 v2, -v3, v1, v2
1769 ; GFX1030-NEXT: v_cvt_u32_f32_e32 v3, v3
1770 ; GFX1030-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v2|, v1
1771 ; GFX1030-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v3, vcc_lo
1772 ; GFX1030-NEXT: v_and_b32_e32 v1, 0x7fffff, v1
1773 ; GFX1030-NEXT: global_store_dword v0, v1, s[0:1]
1774 ; GFX1030-NEXT: s_endpgm
1775 ;
1776 ; EG-LABEL: v_udiv_i23:
1777 ; EG: ; %bb.0:
1778 ; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]
1779 ; EG-NEXT: TEX 3 @6
1780 ; EG-NEXT: ALU 20, @15, KC0[CB0:0-32], KC1[]
1781 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
1782 ; EG-NEXT: CF_END
1783 ; EG-NEXT: PAD
1784 ; EG-NEXT: Fetch clause starting at 6:
1785 ; EG-NEXT: VTX_READ_8 T1.X, T0.X, 6, #1
1786 ; EG-NEXT: VTX_READ_16 T2.X, T0.X, 0, #1
1787 ; EG-NEXT: VTX_READ_8 T3.X, T0.X, 2, #1
1788 ; EG-NEXT: VTX_READ_16 T0.X, T0.X, 4, #1
1789 ; EG-NEXT: ALU clause starting at 14:
1790 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
1791 ; EG-NEXT: ALU clause starting at 15:
1792 ; EG-NEXT: LSHL * T0.W, T1.X, literal.x,
1793 ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
1794 ; EG-NEXT: OR_INT T0.W, T0.X, PV.W,
1795 ; EG-NEXT: LSHL * T1.W, T3.X, literal.x,
1796 ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
1797 ; EG-NEXT: UINT_TO_FLT * T0.X, PV.W,
1798 ; EG-NEXT: OR_INT T0.W, T2.X, T1.W,
1799 ; EG-NEXT: RECIP_IEEE * T0.Y, PS,
1800 ; EG-NEXT: UINT_TO_FLT * T0.Z, PV.W,
1801 ; EG-NEXT: MUL_IEEE * T0.W, PS, T0.Y,
1802 ; EG-NEXT: TRUNC * T0.W, PV.W,
1803 ; EG-NEXT: MULADD_IEEE T1.W, -PV.W, T0.X, T0.Z,
1804 ; EG-NEXT: TRUNC * T0.W, PV.W,
1805 ; EG-NEXT: SETGE * T1.W, |PV.W|, |T0.X|,
1806 ; EG-NEXT: CNDE T1.W, PV.W, 0.0, literal.x,
1807 ; EG-NEXT: FLT_TO_UINT * T0.X, T0.W,
1808 ; EG-NEXT: 1(1.401298e-45), 0(0.000000e+00)
1809 ; EG-NEXT: ADD_INT * T0.W, PS, PV.W,
1810 ; EG-NEXT: AND_INT T0.X, PV.W, literal.x,
1811 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
1812 ; EG-NEXT: 8388607(1.175494e-38), 2(2.802597e-45)
1813 %den_ptr = getelementptr i23, i23 addrspace(1)* %in, i23 1
1814 %num = load i23, i23 addrspace(1) * %in
1815 %den = load i23, i23 addrspace(1) * %den_ptr
1816 %result = udiv i23 %num, %den
1817 %result.ext = zext i23 %result to i32
1818 store i32 %result.ext, i32 addrspace(1)* %out
1819 ret void
1820 }
1822 define amdgpu_kernel void @v_udiv_i24(i32 addrspace(1)* %out, i24 addrspace(1)* %in) {
1823 ; SI-LABEL: v_udiv_i24:
1824 ; SI: ; %bb.0:
1825 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
1826 ; SI-NEXT: s_mov_b32 s7, 0xf000
1827 ; SI-NEXT: s_mov_b32 s6, -1
1828 ; SI-NEXT: s_mov_b32 s10, s6
1829 ; SI-NEXT: s_mov_b32 s11, s7
1830 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1831 ; SI-NEXT: s_mov_b32 s8, s2
1832 ; SI-NEXT: s_mov_b32 s9, s3
1833 ; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0 offset:6
1834 ; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 offset:4
1835 ; SI-NEXT: buffer_load_ubyte v2, off, s[8:11], 0 offset:2
1836 ; SI-NEXT: buffer_load_ushort v3, off, s[8:11], 0
1837 ; SI-NEXT: s_mov_b32 s4, s0
1838 ; SI-NEXT: s_mov_b32 s5, s1
1839 ; SI-NEXT: s_waitcnt vmcnt(3)
1840 ; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
1841 ; SI-NEXT: s_waitcnt vmcnt(2)
1842 ; SI-NEXT: v_or_b32_e32 v0, v1, v0
1843 ; SI-NEXT: v_cvt_f32_u32_e32 v1, v0
1844 ; SI-NEXT: v_sub_i32_e32 v4, vcc, 0, v0
1845 ; SI-NEXT: s_waitcnt vmcnt(1)
1846 ; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
1847 ; SI-NEXT: v_rcp_iflag_f32_e32 v1, v1
1848 ; SI-NEXT: s_waitcnt vmcnt(0)
1849 ; SI-NEXT: v_or_b32_e32 v2, v3, v2
1850 ; SI-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
1851 ; SI-NEXT: v_cvt_u32_f32_e32 v1, v1
1852 ; SI-NEXT: v_mul_lo_u32 v4, v4, v1
1853 ; SI-NEXT: v_mul_hi_u32 v4, v1, v4
1854 ; SI-NEXT: v_add_i32_e32 v1, vcc, v1, v4
1855 ; SI-NEXT: v_mul_hi_u32 v1, v2, v1
1856 ; SI-NEXT: v_mul_lo_u32 v3, v1, v0
1857 ; SI-NEXT: v_add_i32_e32 v4, vcc, 1, v1
1858 ; SI-NEXT: v_subrev_i32_e32 v2, vcc, v3, v2
1859 ; SI-NEXT: v_cmp_ge_u32_e64 s[0:1], v2, v0
1860 ; SI-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1]
1861 ; SI-NEXT: v_subrev_i32_e32 v3, vcc, v0, v2
1862 ; SI-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
1863 ; SI-NEXT: v_add_i32_e32 v3, vcc, 1, v1
1864 ; SI-NEXT: v_cmp_ge_u32_e32 vcc, v2, v0
1865 ; SI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
1866 ; SI-NEXT: v_and_b32_e32 v0, 0xffffff, v0
1867 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
1868 ; SI-NEXT: s_endpgm
1869 ;
1870 ; VI-LABEL: v_udiv_i24:
1871 ; VI: ; %bb.0:
1872 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1873 ; VI-NEXT: s_mov_b32 s7, 0xf000
1874 ; VI-NEXT: s_mov_b32 s6, -1
1875 ; VI-NEXT: s_mov_b32 s10, s6
1876 ; VI-NEXT: s_mov_b32 s11, s7
1877 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1878 ; VI-NEXT: s_mov_b32 s8, s2
1879 ; VI-NEXT: s_mov_b32 s9, s3
1880 ; VI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0 offset:6
1881 ; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 offset:4
1882 ; VI-NEXT: buffer_load_ubyte v2, off, s[8:11], 0 offset:2
1883 ; VI-NEXT: buffer_load_ushort v3, off, s[8:11], 0
1884 ; VI-NEXT: s_mov_b32 s4, s0
1885 ; VI-NEXT: s_mov_b32 s5, s1
1886 ; VI-NEXT: s_waitcnt vmcnt(3)
1887 ; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
1888 ; VI-NEXT: s_waitcnt vmcnt(2)
1889 ; VI-NEXT: v_or_b32_e32 v0, v1, v0
1890 ; VI-NEXT: v_cvt_f32_u32_e32 v1, v0
1891 ; VI-NEXT: v_sub_u32_e32 v4, vcc, 0, v0
1892 ; VI-NEXT: s_waitcnt vmcnt(1)
1893 ; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
1894 ; VI-NEXT: v_rcp_iflag_f32_e32 v1, v1
1895 ; VI-NEXT: s_waitcnt vmcnt(0)
1896 ; VI-NEXT: v_or_b32_e32 v2, v3, v2
1897 ; VI-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
1898 ; VI-NEXT: v_cvt_u32_f32_e32 v1, v1
1899 ; VI-NEXT: v_mul_lo_u32 v4, v4, v1
1900 ; VI-NEXT: v_mul_hi_u32 v4, v1, v4
1901 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v4
1902 ; VI-NEXT: v_mul_hi_u32 v1, v2, v1
1903 ; VI-NEXT: v_mul_lo_u32 v3, v1, v0
1904 ; VI-NEXT: v_add_u32_e32 v4, vcc, 1, v1
1905 ; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v3
1906 ; VI-NEXT: v_cmp_ge_u32_e64 s[0:1], v2, v0
1907 ; VI-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1]
1908 ; VI-NEXT: v_sub_u32_e32 v3, vcc, v2, v0
1909 ; VI-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
1910 ; VI-NEXT: v_add_u32_e32 v3, vcc, 1, v1
1911 ; VI-NEXT: v_cmp_ge_u32_e32 vcc, v2, v0
1912 ; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
1913 ; VI-NEXT: v_and_b32_e32 v0, 0xffffff, v0
1914 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
1915 ; VI-NEXT: s_endpgm
1916 ;
1917 ; GCN-LABEL: v_udiv_i24:
1918 ; GCN: ; %bb.0:
1919 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
1920 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
1921 ; GCN-NEXT: s_add_u32 s4, s2, 4
1922 ; GCN-NEXT: s_addc_u32 s5, s3, 0
1923 ; GCN-NEXT: s_add_u32 s6, s2, 2
1924 ; GCN-NEXT: v_mov_b32_e32 v0, s4
1925 ; GCN-NEXT: s_addc_u32 s7, s3, 0
1926 ; GCN-NEXT: v_mov_b32_e32 v1, s5
1927 ; GCN-NEXT: s_add_u32 s4, s2, 6
1928 ; GCN-NEXT: s_addc_u32 s5, s3, 0
1929 ; GCN-NEXT: v_mov_b32_e32 v2, s4
1930 ; GCN-NEXT: v_mov_b32_e32 v3, s5
1931 ; GCN-NEXT: flat_load_ubyte v4, v[2:3]
1932 ; GCN-NEXT: flat_load_ushort v5, v[0:1]
1933 ; GCN-NEXT: v_mov_b32_e32 v2, s6
1934 ; GCN-NEXT: v_mov_b32_e32 v0, s2
1935 ; GCN-NEXT: v_mov_b32_e32 v3, s7
1936 ; GCN-NEXT: v_mov_b32_e32 v1, s3
1937 ; GCN-NEXT: flat_load_ubyte v2, v[2:3]
1938 ; GCN-NEXT: flat_load_ushort v0, v[0:1]
1939 ; GCN-NEXT: s_waitcnt vmcnt(3)
1940 ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v4
1941 ; GCN-NEXT: s_waitcnt vmcnt(2)
1942 ; GCN-NEXT: v_or_b32_e32 v3, v5, v1
1943 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, v3
1944 ; GCN-NEXT: v_sub_u32_e32 v4, vcc, 0, v3
1945 ; GCN-NEXT: s_waitcnt vmcnt(1)
1946 ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2
1947 ; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v1
1948 ; GCN-NEXT: s_waitcnt vmcnt(0)
1949 ; GCN-NEXT: v_or_b32_e32 v2, v0, v2
1950 ; GCN-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
1951 ; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
1952 ; GCN-NEXT: v_mul_lo_u32 v4, v4, v1
1953 ; GCN-NEXT: v_mul_hi_u32 v4, v1, v4
1954 ; GCN-NEXT: v_add_u32_e32 v0, vcc, v1, v4
1955 ; GCN-NEXT: v_mul_hi_u32 v4, v2, v0
1956 ; GCN-NEXT: v_mov_b32_e32 v0, s0
1957 ; GCN-NEXT: v_mov_b32_e32 v1, s1
1958 ; GCN-NEXT: v_mul_lo_u32 v5, v4, v3
1959 ; GCN-NEXT: v_add_u32_e32 v6, vcc, 1, v4
1960 ; GCN-NEXT: v_sub_u32_e32 v2, vcc, v2, v5
1961 ; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v2, v3
1962 ; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v6, s[0:1]
1963 ; GCN-NEXT: v_sub_u32_e32 v5, vcc, v2, v3
1964 ; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1]
1965 ; GCN-NEXT: v_add_u32_e32 v5, vcc, 1, v4
1966 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v2, v3
1967 ; GCN-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc
1968 ; GCN-NEXT: v_and_b32_e32 v2, 0xffffff, v2
1969 ; GCN-NEXT: flat_store_dword v[0:1], v2
1970 ; GCN-NEXT: s_endpgm
1971 ;
1972 ; GFX1030-LABEL: v_udiv_i24:
1973 ; GFX1030: ; %bb.0:
1974 ; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
1975 ; GFX1030-NEXT: v_mov_b32_e32 v0, 0
1976 ; GFX1030-NEXT: s_waitcnt lgkmcnt(0)
1977 ; GFX1030-NEXT: s_clause 0x3
1978 ; GFX1030-NEXT: global_load_ubyte v1, v0, s[2:3] offset:6
1979 ; GFX1030-NEXT: global_load_ushort v2, v0, s[2:3] offset:4
1980 ; GFX1030-NEXT: global_load_ubyte v3, v0, s[2:3] offset:2
1981 ; GFX1030-NEXT: global_load_ushort v4, v0, s[2:3]
1982 ; GFX1030-NEXT: s_waitcnt vmcnt(3)
1983 ; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1
1984 ; GFX1030-NEXT: s_waitcnt vmcnt(1)
1985 ; GFX1030-NEXT: v_lshlrev_b32_e32 v3, 16, v3
1986 ; GFX1030-NEXT: v_or_b32_e32 v1, v2, v1
1987 ; GFX1030-NEXT: s_waitcnt vmcnt(0)
1988 ; GFX1030-NEXT: v_or_b32_e32 v3, v4, v3
1989 ; GFX1030-NEXT: v_cvt_f32_u32_e32 v2, v1
1990 ; GFX1030-NEXT: v_sub_nc_u32_e32 v5, 0, v1
1991 ; GFX1030-NEXT: v_rcp_iflag_f32_e32 v2, v2
1992 ; GFX1030-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
1993 ; GFX1030-NEXT: v_cvt_u32_f32_e32 v2, v2
1994 ; GFX1030-NEXT: v_mul_lo_u32 v5, v5, v2
1995 ; GFX1030-NEXT: v_mul_hi_u32 v5, v2, v5
1996 ; GFX1030-NEXT: v_add_nc_u32_e32 v2, v2, v5
1997 ; GFX1030-NEXT: v_mul_hi_u32 v2, v3, v2
1998 ; GFX1030-NEXT: v_mul_lo_u32 v4, v2, v1
1999 ; GFX1030-NEXT: v_sub_nc_u32_e32 v3, v3, v4
2000 ; GFX1030-NEXT: v_add_nc_u32_e32 v4, 1, v2
2001 ; GFX1030-NEXT: v_sub_nc_u32_e32 v5, v3, v1
2002 ; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v3, v1
2003 ; GFX1030-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
2004 ; GFX1030-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
2005 ; GFX1030-NEXT: v_add_nc_u32_e32 v4, 1, v2
2006 ; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v3, v1
2007 ; GFX1030-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
2008 ; GFX1030-NEXT: v_and_b32_e32 v1, 0xffffff, v1
2009 ; GFX1030-NEXT: global_store_dword v0, v1, s[0:1]
2010 ; GFX1030-NEXT: s_endpgm
2011 ;
2012 ; EG-LABEL: v_udiv_i24:
2013 ; EG: ; %bb.0:
2014 ; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]
2015 ; EG-NEXT: TEX 3 @6
2016 ; EG-NEXT: ALU 23, @15, KC0[CB0:0-32], KC1[]
2017 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
2018 ; EG-NEXT: CF_END
2019 ; EG-NEXT: PAD
2020 ; EG-NEXT: Fetch clause starting at 6:
2021 ; EG-NEXT: VTX_READ_8 T1.X, T0.X, 6, #1
2022 ; EG-NEXT: VTX_READ_16 T2.X, T0.X, 0, #1
2023 ; EG-NEXT: VTX_READ_8 T3.X, T0.X, 2, #1
2024 ; EG-NEXT: VTX_READ_16 T0.X, T0.X, 4, #1
2025 ; EG-NEXT: ALU clause starting at 14:
2026 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
2027 ; EG-NEXT: ALU clause starting at 15:
2028 ; EG-NEXT: LSHL * T0.W, T1.X, literal.x,
2029 ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
2030 ; EG-NEXT: OR_INT * T0.W, T0.X, PV.W,
2031 ; EG-NEXT: SUB_INT T1.W, 0.0, PV.W,
2032 ; EG-NEXT: RECIP_UINT * T0.X, PV.W,
2033 ; EG-NEXT: MULLO_INT * T0.Y, PV.W, PS,
2034 ; EG-NEXT: LSHL T1.W, T3.X, literal.x,
2035 ; EG-NEXT: MULHI * T0.Y, T0.X, PS,
2036 ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
2037 ; EG-NEXT: ADD_INT T2.W, T0.X, PS,
2038 ; EG-NEXT: OR_INT * T1.W, T2.X, PV.W,
2039 ; EG-NEXT: MULHI * T0.X, PS, PV.W,
2040 ; EG-NEXT: MULLO_INT * T0.Y, PS, T0.W,
2041 ; EG-NEXT: SUB_INT * T1.W, T1.W, PS,
2042 ; EG-NEXT: ADD_INT T0.Z, T0.X, 1,
2043 ; EG-NEXT: SETGE_UINT T2.W, PV.W, T0.W,
2044 ; EG-NEXT: SUB_INT * T3.W, PV.W, T0.W,
2045 ; EG-NEXT: CNDE_INT T1.W, PV.W, T1.W, PS,
2046 ; EG-NEXT: CNDE_INT * T2.W, PV.W, T0.X, PV.Z,
2047 ; EG-NEXT: ADD_INT T3.W, PS, 1,
2048 ; EG-NEXT: SETGE_UINT * T0.W, PV.W, T0.W,
2049 ; EG-NEXT: CNDE_INT T0.X, PS, T2.W, PV.W,
2050 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
2051 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
2052 %den_ptr = getelementptr i24, i24 addrspace(1)* %in, i24 1
2053 %num = load i24, i24 addrspace(1) * %in
2054 %den = load i24, i24 addrspace(1) * %den_ptr
2055 %result = udiv i24 %num, %den
2056 %result.ext = zext i24 %result to i32
2057 store i32 %result.ext, i32 addrspace(1)* %out
2058 ret void
2059 }
2061 define amdgpu_kernel void @scalarize_mulhu_4xi32(<4 x i32> addrspace(1)* nocapture readonly %in, <4 x i32> addrspace(1)* nocapture %out) {
2062 ; SI-LABEL: scalarize_mulhu_4xi32:
2063 ; SI: ; %bb.0:
2064 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
2065 ; SI-NEXT: s_mov_b32 s7, 0xf000
2066 ; SI-NEXT: s_mov_b32 s6, -1
2067 ; SI-NEXT: s_waitcnt lgkmcnt(0)
2068 ; SI-NEXT: s_mov_b32 s4, s0
2069 ; SI-NEXT: s_mov_b32 s5, s1
2070 ; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 0
2071 ; SI-NEXT: s_mov_b32 s0, 0x1389c755
2072 ; SI-NEXT: s_mov_b32 s4, s2
2073 ; SI-NEXT: s_mov_b32 s5, s3
2074 ; SI-NEXT: s_waitcnt vmcnt(0)
2075 ; SI-NEXT: v_lshrrev_b32_e32 v0, 2, v0
2076 ; SI-NEXT: v_lshrrev_b32_e32 v1, 2, v1
2077 ; SI-NEXT: v_lshrrev_b32_e32 v2, 2, v2
2078 ; SI-NEXT: v_lshrrev_b32_e32 v3, 2, v3
2079 ; SI-NEXT: v_mul_hi_u32 v0, v0, s0
2080 ; SI-NEXT: v_mul_hi_u32 v1, v1, s0
2081 ; SI-NEXT: v_mul_hi_u32 v2, v2, s0
2082 ; SI-NEXT: v_mul_hi_u32 v3, v3, s0
2083 ; SI-NEXT: v_lshrrev_b32_e32 v0, 10, v0
2084 ; SI-NEXT: v_lshrrev_b32_e32 v1, 10, v1
2085 ; SI-NEXT: v_lshrrev_b32_e32 v2, 10, v2
2086 ; SI-NEXT: v_lshrrev_b32_e32 v3, 10, v3
2087 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
2088 ; SI-NEXT: s_endpgm
2089 ;
2090 ; VI-LABEL: scalarize_mulhu_4xi32:
2091 ; VI: ; %bb.0:
2092 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
2093 ; VI-NEXT: s_mov_b32 s7, 0xf000
2094 ; VI-NEXT: s_mov_b32 s6, -1
2095 ; VI-NEXT: s_waitcnt lgkmcnt(0)
2096 ; VI-NEXT: s_mov_b32 s4, s0
2097 ; VI-NEXT: s_mov_b32 s5, s1
2098 ; VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 0
2099 ; VI-NEXT: s_mov_b32 s0, 0x1389c755
2100 ; VI-NEXT: s_mov_b32 s4, s2
2101 ; VI-NEXT: s_mov_b32 s5, s3
2102 ; VI-NEXT: s_waitcnt vmcnt(0)
2103 ; VI-NEXT: v_lshrrev_b32_e32 v0, 2, v0
2104 ; VI-NEXT: v_lshrrev_b32_e32 v1, 2, v1
2105 ; VI-NEXT: v_lshrrev_b32_e32 v2, 2, v2
2106 ; VI-NEXT: v_lshrrev_b32_e32 v3, 2, v3
2107 ; VI-NEXT: v_mul_hi_u32 v0, v0, s0
2108 ; VI-NEXT: v_mul_hi_u32 v1, v1, s0
2109 ; VI-NEXT: v_mul_hi_u32 v2, v2, s0
2110 ; VI-NEXT: v_mul_hi_u32 v3, v3, s0
2111 ; VI-NEXT: v_lshrrev_b32_e32 v0, 10, v0
2112 ; VI-NEXT: v_lshrrev_b32_e32 v1, 10, v1
2113 ; VI-NEXT: v_lshrrev_b32_e32 v2, 10, v2
2114 ; VI-NEXT: v_lshrrev_b32_e32 v3, 10, v3
2115 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
2116 ; VI-NEXT: s_endpgm
2117 ;
2118 ; GCN-LABEL: scalarize_mulhu_4xi32:
2119 ; GCN: ; %bb.0:
2120 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
2121 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
2122 ; GCN-NEXT: v_mov_b32_e32 v0, s0
2123 ; GCN-NEXT: v_mov_b32_e32 v1, s1
2124 ; GCN-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
2125 ; GCN-NEXT: s_mov_b32 s0, 0x1389c755
2126 ; GCN-NEXT: v_mov_b32_e32 v4, s2
2127 ; GCN-NEXT: v_mov_b32_e32 v5, s3
2128 ; GCN-NEXT: s_waitcnt vmcnt(0)
2129 ; GCN-NEXT: v_lshrrev_b32_e32 v0, 2, v0
2130 ; GCN-NEXT: v_lshrrev_b32_e32 v1, 2, v1
2131 ; GCN-NEXT: v_lshrrev_b32_e32 v2, 2, v2
2132 ; GCN-NEXT: v_lshrrev_b32_e32 v3, 2, v3
2133 ; GCN-NEXT: v_mul_hi_u32 v0, v0, s0
2134 ; GCN-NEXT: v_mul_hi_u32 v1, v1, s0
2135 ; GCN-NEXT: v_mul_hi_u32 v2, v2, s0
2136 ; GCN-NEXT: v_mul_hi_u32 v3, v3, s0
2137 ; GCN-NEXT: v_lshrrev_b32_e32 v0, 10, v0
2138 ; GCN-NEXT: v_lshrrev_b32_e32 v1, 10, v1
2139 ; GCN-NEXT: v_lshrrev_b32_e32 v2, 10, v2
2140 ; GCN-NEXT: v_lshrrev_b32_e32 v3, 10, v3
2141 ; GCN-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
2142 ; GCN-NEXT: s_endpgm
2143 ;
2144 ; GFX1030-LABEL: scalarize_mulhu_4xi32:
2145 ; GFX1030: ; %bb.0:
2146 ; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
2147 ; GFX1030-NEXT: v_mov_b32_e32 v4, 0
2148 ; GFX1030-NEXT: s_waitcnt lgkmcnt(0)
2149 ; GFX1030-NEXT: global_load_dwordx4 v[0:3], v4, s[0:1]
2150 ; GFX1030-NEXT: s_waitcnt vmcnt(0)
2151 ; GFX1030-NEXT: v_lshrrev_b32_e32 v0, 2, v0
2152 ; GFX1030-NEXT: v_lshrrev_b32_e32 v1, 2, v1
2153 ; GFX1030-NEXT: v_lshrrev_b32_e32 v2, 2, v2
2154 ; GFX1030-NEXT: v_lshrrev_b32_e32 v3, 2, v3
2155 ; GFX1030-NEXT: v_mul_hi_u32 v0, 0x1389c755, v0
2156 ; GFX1030-NEXT: v_mul_hi_u32 v1, 0x1389c755, v1
2157 ; GFX1030-NEXT: v_mul_hi_u32 v2, 0x1389c755, v2
2158 ; GFX1030-NEXT: v_mul_hi_u32 v3, 0x1389c755, v3
2159 ; GFX1030-NEXT: v_lshrrev_b32_e32 v0, 10, v0
2160 ; GFX1030-NEXT: v_lshrrev_b32_e32 v1, 10, v1
2161 ; GFX1030-NEXT: v_lshrrev_b32_e32 v2, 10, v2
2162 ; GFX1030-NEXT: v_lshrrev_b32_e32 v3, 10, v3
2163 ; GFX1030-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
2164 ; GFX1030-NEXT: s_endpgm
2165 ;
2166 ; EG-LABEL: scalarize_mulhu_4xi32:
2167 ; EG: ; %bb.0:
2168 ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
2169 ; EG-NEXT: TEX 0 @6
2170 ; EG-NEXT: ALU 20, @9, KC0[CB0:0-32], KC1[]
2171 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
2172 ; EG-NEXT: CF_END
2173 ; EG-NEXT: PAD
2174 ; EG-NEXT: Fetch clause starting at 6:
2175 ; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
2176 ; EG-NEXT: ALU clause starting at 8:
2177 ; EG-NEXT: MOV * T0.X, KC0[2].Y,
2178 ; EG-NEXT: ALU clause starting at 9:
2179 ; EG-NEXT: LSHR T0.W, T0.W, literal.x,
2180 ; EG-NEXT: LSHR * T1.W, T0.Z, literal.x,
2181 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
2182 ; EG-NEXT: MULHI * T0.Z, PV.W, literal.x,
2183 ; EG-NEXT: 327796565(3.478022e-27), 0(0.000000e+00)
2184 ; EG-NEXT: LSHR T1.Z, T0.Y, literal.x,
2185 ; EG-NEXT: LSHR T0.W, PS, literal.y,
2186 ; EG-NEXT: MULHI * T0.Y, T1.W, literal.z,
2187 ; EG-NEXT: 2(2.802597e-45), 10(1.401298e-44)
2188 ; EG-NEXT: 327796565(3.478022e-27), 0(0.000000e+00)
2189 ; EG-NEXT: LSHR T0.Z, PS, literal.x,
2190 ; EG-NEXT: LSHR T1.W, T0.X, literal.y,
2191 ; EG-NEXT: MULHI * T0.X, PV.Z, literal.z,
2192 ; EG-NEXT: 10(1.401298e-44), 2(2.802597e-45)
2193 ; EG-NEXT: 327796565(3.478022e-27), 0(0.000000e+00)
2194 ; EG-NEXT: LSHR T0.Y, PS, literal.x,
2195 ; EG-NEXT: MULHI * T0.X, PV.W, literal.y,
2196 ; EG-NEXT: 10(1.401298e-44), 327796565(3.478022e-27)
2197 ; EG-NEXT: LSHR T0.X, PS, literal.x,
2198 ; EG-NEXT: LSHR * T1.X, KC0[2].Z, literal.y,
2199 ; EG-NEXT: 10(1.401298e-44), 2(2.802597e-45)
2200 %1 = load <4 x i32>, <4 x i32> addrspace(1)* %in, align 16
2201 %2 = udiv <4 x i32> %1, <i32 53668, i32 53668, i32 53668, i32 53668>
2202 store <4 x i32> %2, <4 x i32> addrspace(1)* %out, align 16
2203 ret void
2204 }
2206 define amdgpu_kernel void @test_udiv2(i32 %p) {
2207 ; SI-LABEL: test_udiv2:
2208 ; SI: ; %bb.0:
2209 ; SI-NEXT: s_load_dword s0, s[0:1], 0x9
2210 ; SI-NEXT: s_mov_b32 s3, 0xf000
2211 ; SI-NEXT: s_mov_b32 s2, -1
2212 ; SI-NEXT: s_waitcnt lgkmcnt(0)
2213 ; SI-NEXT: s_lshr_b32 s0, s0, 1
2214 ; SI-NEXT: v_mov_b32_e32 v0, s0
2215 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
2216 ; SI-NEXT: s_waitcnt vmcnt(0)
2217 ; SI-NEXT: s_endpgm
2218 ;
2219 ; VI-LABEL: test_udiv2:
2220 ; VI: ; %bb.0:
2221 ; VI-NEXT: s_load_dword s0, s[0:1], 0x24
2222 ; VI-NEXT: s_mov_b32 s3, 0xf000
2223 ; VI-NEXT: s_mov_b32 s2, -1
2224 ; VI-NEXT: s_waitcnt lgkmcnt(0)
2225 ; VI-NEXT: s_lshr_b32 s0, s0, 1
2226 ; VI-NEXT: v_mov_b32_e32 v0, s0
2227 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
2228 ; VI-NEXT: s_waitcnt vmcnt(0)
2229 ; VI-NEXT: s_endpgm
2230 ;
2231 ; GCN-LABEL: test_udiv2:
2232 ; GCN: ; %bb.0:
2233 ; GCN-NEXT: s_load_dword s0, s[4:5], 0x0
2234 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
2235 ; GCN-NEXT: s_lshr_b32 s0, s0, 1
2236 ; GCN-NEXT: v_mov_b32_e32 v0, s0
2237 ; GCN-NEXT: flat_store_dword v[0:1], v0
2238 ; GCN-NEXT: s_waitcnt vmcnt(0)
2239 ; GCN-NEXT: s_endpgm
2240 ;
2241 ; GFX1030-LABEL: test_udiv2:
2242 ; GFX1030: ; %bb.0:
2243 ; GFX1030-NEXT: s_load_dword s0, s[4:5], 0x0
2244 ; GFX1030-NEXT: s_waitcnt lgkmcnt(0)
2245 ; GFX1030-NEXT: s_lshr_b32 s0, s0, 1
2246 ; GFX1030-NEXT: v_mov_b32_e32 v0, s0
2247 ; GFX1030-NEXT: global_store_dword v[0:1], v0, off
2248 ; GFX1030-NEXT: s_waitcnt_vscnt null, 0x0
2249 ; GFX1030-NEXT: s_endpgm
2250 ;
2251 ; EG-LABEL: test_udiv2:
2252 ; EG: ; %bb.0:
2253 ; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
2254 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
2255 ; EG-NEXT: CF_END
2256 ; EG-NEXT: PAD
2257 ; EG-NEXT: ALU clause starting at 4:
2258 ; EG-NEXT: MOV T0.X, literal.x,
2259 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, 1,
2260 ; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00)
2261 %i = udiv i32 %p, 2
2262 store volatile i32 %i, i32 addrspace(1)* undef
2263 ret void
2264 }
2266 define amdgpu_kernel void @test_udiv_3_mulhu(i32 %p) {
2267 ; SI-LABEL: test_udiv_3_mulhu:
2268 ; SI: ; %bb.0:
2269 ; SI-NEXT: s_load_dword s0, s[0:1], 0x9
2270 ; SI-NEXT: v_mov_b32_e32 v0, 0xaaaaaaab
2271 ; SI-NEXT: s_mov_b32 s3, 0xf000
2272 ; SI-NEXT: s_mov_b32 s2, -1
2273 ; SI-NEXT: s_waitcnt lgkmcnt(0)
2274 ; SI-NEXT: v_mul_hi_u32 v0, s0, v0
2275 ; SI-NEXT: v_lshrrev_b32_e32 v0, 1, v0
2276 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
2277 ; SI-NEXT: s_waitcnt vmcnt(0)
2278 ; SI-NEXT: s_endpgm
2279 ;
2280 ; VI-LABEL: test_udiv_3_mulhu:
2281 ; VI: ; %bb.0:
2282 ; VI-NEXT: s_load_dword s0, s[0:1], 0x24
2283 ; VI-NEXT: v_mov_b32_e32 v0, 0xaaaaaaab
2284 ; VI-NEXT: s_mov_b32 s3, 0xf000
2285 ; VI-NEXT: s_mov_b32 s2, -1
2286 ; VI-NEXT: s_waitcnt lgkmcnt(0)
2287 ; VI-NEXT: v_mul_hi_u32 v0, s0, v0
2288 ; VI-NEXT: v_lshrrev_b32_e32 v0, 1, v0
2289 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
2290 ; VI-NEXT: s_waitcnt vmcnt(0)
2291 ; VI-NEXT: s_endpgm
2292 ;
2293 ; GCN-LABEL: test_udiv_3_mulhu:
2294 ; GCN: ; %bb.0:
2295 ; GCN-NEXT: s_load_dword s0, s[4:5], 0x0
2296 ; GCN-NEXT: v_mov_b32_e32 v0, 0xaaaaaaab
2297 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
2298 ; GCN-NEXT: v_mul_hi_u32 v0, s0, v0
2299 ; GCN-NEXT: v_lshrrev_b32_e32 v0, 1, v0
2300 ; GCN-NEXT: flat_store_dword v[0:1], v0
2301 ; GCN-NEXT: s_waitcnt vmcnt(0)
2302 ; GCN-NEXT: s_endpgm
2303 ;
2304 ; GFX1030-LABEL: test_udiv_3_mulhu:
2305 ; GFX1030: ; %bb.0:
2306 ; GFX1030-NEXT: s_load_dword s0, s[4:5], 0x0
2307 ; GFX1030-NEXT: s_waitcnt lgkmcnt(0)
2308 ; GFX1030-NEXT: s_mul_hi_u32 s0, s0, 0xaaaaaaab
2309 ; GFX1030-NEXT: s_lshr_b32 s0, s0, 1
2310 ; GFX1030-NEXT: v_mov_b32_e32 v0, s0
2311 ; GFX1030-NEXT: global_store_dword v[0:1], v0, off
2312 ; GFX1030-NEXT: s_waitcnt_vscnt null, 0x0
2313 ; GFX1030-NEXT: s_endpgm
2314 ;
2315 ; EG-LABEL: test_udiv_3_mulhu:
2316 ; EG: ; %bb.0:
2317 ; EG-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]
2318 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
2319 ; EG-NEXT: CF_END
2320 ; EG-NEXT: PAD
2321 ; EG-NEXT: ALU clause starting at 4:
2322 ; EG-NEXT: MULHI * T0.X, KC0[2].Y, literal.x,
2323 ; EG-NEXT: -1431655765(-3.031649e-13), 0(0.000000e+00)
2324 ; EG-NEXT: LSHR T0.X, PS, 1,
2325 ; EG-NEXT: MOV * T1.X, literal.x,
2326 ; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00)
2327 %i = udiv i32 %p, 3
2328 store volatile i32 %i, i32 addrspace(1)* undef
2329 ret void
2330 }
2332 define amdgpu_kernel void @fdiv_test_denormals(i8 addrspace(1)* nocapture readonly %arg) {
2333 ; SI-LABEL: fdiv_test_denormals:
2334 ; SI: ; %bb.0: ; %bb
2335 ; SI-NEXT: s_mov_b32 s0, 0
2336 ; SI-NEXT: s_mov_b32 s3, 0xf000
2337 ; SI-NEXT: s_mov_b32 s2, -1
2338 ; SI-NEXT: s_mov_b32 s1, s0
2339 ; SI-NEXT: buffer_load_sbyte v0, off, s[0:3], 0
2340 ; SI-NEXT: buffer_load_sbyte v1, off, s[0:3], 0
2341 ; SI-NEXT: s_waitcnt vmcnt(1)
2342 ; SI-NEXT: v_cvt_f32_i32_e32 v2, v0
2343 ; SI-NEXT: s_waitcnt vmcnt(0)
2344 ; SI-NEXT: v_cvt_f32_i32_e32 v3, v1
2345 ; SI-NEXT: v_xor_b32_e32 v0, v1, v0
2346 ; SI-NEXT: v_ashrrev_i32_e32 v0, 30, v0
2347 ; SI-NEXT: v_rcp_iflag_f32_e32 v4, v2
2348 ; SI-NEXT: v_or_b32_e32 v0, 1, v0
2349 ; SI-NEXT: v_mul_f32_e32 v1, v3, v4
2350 ; SI-NEXT: v_trunc_f32_e32 v1, v1
2351 ; SI-NEXT: v_mad_f32 v3, -v1, v2, v3
2352 ; SI-NEXT: v_cvt_i32_f32_e32 v1, v1
2353 ; SI-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v2|
2354 ; SI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
2355 ; SI-NEXT: v_add_i32_e32 v0, vcc, v0, v1
2356 ; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0
2357 ; SI-NEXT: s_endpgm
2358 ;
2359 ; VI-LABEL: fdiv_test_denormals:
2360 ; VI: ; %bb.0: ; %bb
2361 ; VI-NEXT: s_mov_b32 s0, 0
2362 ; VI-NEXT: s_mov_b32 s3, 0xf000
2363 ; VI-NEXT: s_mov_b32 s2, -1
2364 ; VI-NEXT: s_mov_b32 s1, s0
2365 ; VI-NEXT: buffer_load_sbyte v0, off, s[0:3], 0
2366 ; VI-NEXT: buffer_load_sbyte v1, off, s[0:3], 0
2367 ; VI-NEXT: s_waitcnt vmcnt(1)
2368 ; VI-NEXT: v_cvt_f32_i32_e32 v2, v0
2369 ; VI-NEXT: s_waitcnt vmcnt(0)
2370 ; VI-NEXT: v_cvt_f32_i32_e32 v3, v1
2371 ; VI-NEXT: v_xor_b32_e32 v0, v1, v0
2372 ; VI-NEXT: v_ashrrev_i32_e32 v0, 30, v0
2373 ; VI-NEXT: v_rcp_iflag_f32_e32 v4, v2
2374 ; VI-NEXT: v_or_b32_e32 v0, 1, v0
2375 ; VI-NEXT: v_mul_f32_e32 v1, v3, v4
2376 ; VI-NEXT: v_trunc_f32_e32 v1, v1
2377 ; VI-NEXT: v_mad_f32 v3, -v1, v2, v3
2378 ; VI-NEXT: v_cvt_i32_f32_e32 v1, v1
2379 ; VI-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v2|
2380 ; VI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
2381 ; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1
2382 ; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0
2383 ; VI-NEXT: s_endpgm
2384 ;
2385 ; GCN-LABEL: fdiv_test_denormals:
2386 ; GCN: ; %bb.0: ; %bb
2387 ; GCN-NEXT: flat_load_sbyte v2, v[0:1]
2388 ; GCN-NEXT: v_mov_b32_e32 v0, 0
2389 ; GCN-NEXT: v_mov_b32_e32 v1, 0
2390 ; GCN-NEXT: flat_load_sbyte v3, v[0:1]
2391 ; GCN-NEXT: s_waitcnt vmcnt(1)
2392 ; GCN-NEXT: v_cvt_f32_i32_e32 v4, v2
2393 ; GCN-NEXT: s_waitcnt vmcnt(0)
2394 ; GCN-NEXT: v_cvt_f32_i32_e32 v5, v3
2395 ; GCN-NEXT: v_rcp_iflag_f32_e32 v6, v4
2396 ; GCN-NEXT: v_xor_b32_e32 v2, v3, v2
2397 ; GCN-NEXT: v_ashrrev_i32_e32 v2, 30, v2
2398 ; GCN-NEXT: v_or_b32_e32 v2, 1, v2
2399 ; GCN-NEXT: v_mul_f32_e32 v3, v5, v6
2400 ; GCN-NEXT: v_trunc_f32_e32 v3, v3
2401 ; GCN-NEXT: v_mad_f32 v5, -v3, v4, v5
2402 ; GCN-NEXT: v_cvt_i32_f32_e32 v3, v3
2403 ; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v5|, |v4|
2404 ; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
2405 ; GCN-NEXT: v_add_u32_e32 v2, vcc, v2, v3
2406 ; GCN-NEXT: flat_store_byte v[0:1], v2
2407 ; GCN-NEXT: s_endpgm
2408 ;
2409 ; GFX1030-LABEL: fdiv_test_denormals:
2410 ; GFX1030: ; %bb.0: ; %bb
2411 ; GFX1030-NEXT: global_load_sbyte v2, v[0:1], off
2412 ; GFX1030-NEXT: v_mov_b32_e32 v0, 0
2413 ; GFX1030-NEXT: v_mov_b32_e32 v1, 0
2414 ; GFX1030-NEXT: global_load_sbyte v3, v[0:1], off
2415 ; GFX1030-NEXT: s_waitcnt vmcnt(1)
2416 ; GFX1030-NEXT: v_cvt_f32_i32_e32 v4, v2
2417 ; GFX1030-NEXT: v_rcp_iflag_f32_e32 v5, v4
2418 ; GFX1030-NEXT: s_waitcnt vmcnt(0)
2419 ; GFX1030-NEXT: v_cvt_f32_i32_e32 v6, v3
2420 ; GFX1030-NEXT: v_xor_b32_e32 v2, v3, v2
2421 ; GFX1030-NEXT: v_ashrrev_i32_e32 v2, 30, v2
2422 ; GFX1030-NEXT: v_mul_f32_e32 v5, v6, v5
2423 ; GFX1030-NEXT: v_or_b32_e32 v2, 1, v2
2424 ; GFX1030-NEXT: v_trunc_f32_e32 v3, v5
2425 ; GFX1030-NEXT: v_fma_f32 v5, -v3, v4, v6
2426 ; GFX1030-NEXT: v_cvt_i32_f32_e32 v3, v3
2427 ; GFX1030-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v5|, |v4|
2428 ; GFX1030-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc_lo
2429 ; GFX1030-NEXT: v_add_nc_u32_e32 v2, v3, v2
2430 ; GFX1030-NEXT: global_store_byte v[0:1], v2, off
2431 ; GFX1030-NEXT: s_endpgm
2432 ;
2433 ; EG-LABEL: fdiv_test_denormals:
2434 ; EG: ; %bb.0: ; %bb
2435 ; EG-NEXT: TEX 0 @6
2436 ; EG-NEXT: ALU 0, @10, KC0[], KC1[]
2437 ; EG-NEXT: TEX 0 @8
2438 ; EG-NEXT: ALU 25, @11, KC0[], KC1[]
2439 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
2440 ; EG-NEXT: CF_END
2441 ; EG-NEXT: Fetch clause starting at 6:
2442 ; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
2443 ; EG-NEXT: Fetch clause starting at 8:
2444 ; EG-NEXT: VTX_READ_8 T1.X, T1.X, 0, #1
2445 ; EG-NEXT: ALU clause starting at 10:
2446 ; EG-NEXT: MOV * T1.X, 0.0,
2447 ; EG-NEXT: ALU clause starting at 11:
2448 ; EG-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x,
2449 ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
2450 ; EG-NEXT: INT_TO_FLT * T0.X, PV.W,
2451 ; EG-NEXT: BFE_INT T1.W, T1.X, 0.0, literal.x,
2452 ; EG-NEXT: RECIP_IEEE * T0.Y, PS,
2453 ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
2454 ; EG-NEXT: INT_TO_FLT * T0.Z, PV.W,
2455 ; EG-NEXT: MUL_IEEE * T2.W, PS, T0.Y,
2456 ; EG-NEXT: TRUNC T2.W, PV.W,
2457 ; EG-NEXT: XOR_INT * T0.W, T1.W, T0.W,
2458 ; EG-NEXT: ASHR T0.W, PS, literal.x,
2459 ; EG-NEXT: MULADD_IEEE * T1.W, -PV.W, T0.X, T0.Z,
2460 ; EG-NEXT: 30(4.203895e-44), 0(0.000000e+00)
2461 ; EG-NEXT: TRUNC T0.Z, T2.W,
2462 ; EG-NEXT: SETGE T1.W, |PS|, |T0.X|,
2463 ; EG-NEXT: OR_INT * T0.W, PV.W, 1,
2464 ; EG-NEXT: CNDE T0.W, PV.W, 0.0, PS,
2465 ; EG-NEXT: FLT_TO_INT * T1.W, PV.Z,
2466 ; EG-NEXT: ADD_INT * T0.W, PS, PV.W,
2467 ; EG-NEXT: AND_INT T0.X, PV.W, literal.x,
2468 ; EG-NEXT: MOV * T0.W, literal.x,
2469 ; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
2470 ; EG-NEXT: MOV T0.Y, 0.0,
2471 ; EG-NEXT: MOV * T0.Z, 0.0,
2472 ; EG-NEXT: MOV * T1.X, literal.x,
2473 ; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00)
2474 bb:
2475 %tmp = load i8, i8 addrspace(1)* null, align 1
2476 %tmp1 = sext i8 %tmp to i32
2477 %tmp2 = getelementptr inbounds i8, i8 addrspace(1)* %arg, i64 undef
2478 %tmp3 = load i8, i8 addrspace(1)* %tmp2, align 1
2479 %tmp4 = sext i8 %tmp3 to i32
2480 %tmp5 = sdiv i32 %tmp1, %tmp4
2481 %tmp6 = trunc i32 %tmp5 to i8
2482 store i8 %tmp6, i8 addrspace(1)* null, align 1
2483 ret void
2484 }
2486 define i64 @v_test_udiv64_mulhi_fold(i64 %arg) {
2487 ; SI-LABEL: v_test_udiv64_mulhi_fold:
2488 ; SI: ; %bb.0:
2489 ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2490 ; SI-NEXT: v_mov_b32_e32 v2, 0x4f800000
2491 ; SI-NEXT: v_madak_f32 v2, 0, v2, 0x47c35000
2492 ; SI-NEXT: v_rcp_f32_e32 v2, v2
2493 ; SI-NEXT: s_mov_b32 s4, 0xfffe7960
2494 ; SI-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
2495 ; SI-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
2496 ; SI-NEXT: v_trunc_f32_e32 v3, v3
2497 ; SI-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
2498 ; SI-NEXT: v_cvt_u32_f32_e32 v2, v2
2499 ; SI-NEXT: v_cvt_u32_f32_e32 v3, v3
2500 ; SI-NEXT: v_mul_hi_u32 v4, v2, s4
2501 ; SI-NEXT: v_mul_lo_u32 v6, v3, s4
2502 ; SI-NEXT: v_mul_lo_u32 v5, v2, s4
2503 ; SI-NEXT: v_sub_i32_e32 v4, vcc, v4, v2
2504 ; SI-NEXT: v_add_i32_e32 v4, vcc, v4, v6
2505 ; SI-NEXT: v_mul_hi_u32 v7, v2, v5
2506 ; SI-NEXT: v_mul_lo_u32 v6, v2, v4
2507 ; SI-NEXT: v_mul_hi_u32 v8, v2, v4
2508 ; SI-NEXT: v_mul_hi_u32 v9, v3, v4
2509 ; SI-NEXT: v_mul_lo_u32 v4, v3, v4
2510 ; SI-NEXT: v_add_i32_e32 v6, vcc, v7, v6
2511 ; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc
2512 ; SI-NEXT: v_mul_lo_u32 v8, v3, v5
2513 ; SI-NEXT: v_mul_hi_u32 v5, v3, v5
2514 ; SI-NEXT: v_add_i32_e32 v6, vcc, v6, v8
2515 ; SI-NEXT: v_addc_u32_e32 v5, vcc, v7, v5, vcc
2516 ; SI-NEXT: v_addc_u32_e32 v6, vcc, 0, v9, vcc
2517 ; SI-NEXT: v_add_i32_e32 v4, vcc, v5, v4
2518 ; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
2519 ; SI-NEXT: v_add_i32_e32 v2, vcc, v2, v4
2520 ; SI-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc
2521 ; SI-NEXT: v_mul_hi_u32 v4, v2, s4
2522 ; SI-NEXT: v_mul_lo_u32 v5, v3, s4
2523 ; SI-NEXT: v_mul_lo_u32 v6, v2, s4
2524 ; SI-NEXT: s_mov_b32 s4, 0x186a0
2525 ; SI-NEXT: v_subrev_i32_e32 v4, vcc, v2, v4
2526 ; SI-NEXT: v_add_i32_e32 v4, vcc, v4, v5
2527 ; SI-NEXT: v_mul_lo_u32 v5, v2, v4
2528 ; SI-NEXT: v_mul_hi_u32 v7, v2, v6
2529 ; SI-NEXT: v_mul_hi_u32 v8, v2, v4
2530 ; SI-NEXT: v_mul_hi_u32 v9, v3, v4
2531 ; SI-NEXT: v_mul_lo_u32 v4, v3, v4
2532 ; SI-NEXT: v_add_i32_e32 v5, vcc, v7, v5
2533 ; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc
2534 ; SI-NEXT: v_mul_lo_u32 v8, v3, v6
2535 ; SI-NEXT: v_mul_hi_u32 v6, v3, v6
2536 ; SI-NEXT: v_add_i32_e32 v5, vcc, v5, v8
2537 ; SI-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc
2538 ; SI-NEXT: v_addc_u32_e32 v6, vcc, 0, v9, vcc
2539 ; SI-NEXT: v_add_i32_e32 v4, vcc, v5, v4
2540 ; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
2541 ; SI-NEXT: v_add_i32_e32 v2, vcc, v2, v4
2542 ; SI-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc
2543 ; SI-NEXT: v_mul_lo_u32 v4, v0, v3
2544 ; SI-NEXT: v_mul_hi_u32 v5, v0, v2
2545 ; SI-NEXT: v_mul_hi_u32 v6, v0, v3
2546 ; SI-NEXT: v_mul_hi_u32 v7, v1, v3
2547 ; SI-NEXT: v_mul_lo_u32 v3, v1, v3
2548 ; SI-NEXT: v_add_i32_e32 v4, vcc, v5, v4
2549 ; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
2550 ; SI-NEXT: v_mul_lo_u32 v6, v1, v2
2551 ; SI-NEXT: v_mul_hi_u32 v2, v1, v2
2552 ; SI-NEXT: v_add_i32_e32 v4, vcc, v4, v6
2553 ; SI-NEXT: v_addc_u32_e32 v2, vcc, v5, v2, vcc
2554 ; SI-NEXT: v_addc_u32_e32 v4, vcc, 0, v7, vcc
2555 ; SI-NEXT: v_add_i32_e32 v2, vcc, v2, v3
2556 ; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
2557 ; SI-NEXT: v_mul_lo_u32 v4, v3, s4
2558 ; SI-NEXT: v_mul_hi_u32 v5, v2, s4
2559 ; SI-NEXT: v_mul_lo_u32 v6, v2, s4
2560 ; SI-NEXT: s_mov_b32 s4, 0x1869f
2561 ; SI-NEXT: v_add_i32_e32 v4, vcc, v5, v4
2562 ; SI-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
2563 ; SI-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc
2564 ; SI-NEXT: v_subrev_i32_e32 v4, vcc, 0x186a0, v0
2565 ; SI-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v1, vcc
2566 ; SI-NEXT: v_cmp_lt_u32_e32 vcc, s4, v4
2567 ; SI-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
2568 ; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
2569 ; SI-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc
2570 ; SI-NEXT: v_add_i32_e32 v5, vcc, 2, v2
2571 ; SI-NEXT: v_addc_u32_e32 v6, vcc, 0, v3, vcc
2572 ; SI-NEXT: v_add_i32_e32 v7, vcc, 1, v2
2573 ; SI-NEXT: v_cmp_lt_u32_e64 s[4:5], s4, v0
2574 ; SI-NEXT: v_addc_u32_e32 v8, vcc, 0, v3, vcc
2575 ; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[4:5]
2576 ; SI-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
2577 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
2578 ; SI-NEXT: v_cndmask_b32_e64 v0, -1, v0, s[4:5]
2579 ; SI-NEXT: v_cndmask_b32_e32 v4, v7, v5, vcc
2580 ; SI-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0
2581 ; SI-NEXT: v_cndmask_b32_e32 v1, v8, v6, vcc
2582 ; SI-NEXT: v_cndmask_b32_e64 v0, v2, v4, s[4:5]
2583 ; SI-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[4:5]
2584 ; SI-NEXT: s_setpc_b64 s[30:31]
2585 ;
2586 ; VI-LABEL: v_test_udiv64_mulhi_fold:
2587 ; VI: ; %bb.0:
2588 ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2589 ; VI-NEXT: v_mov_b32_e32 v2, 0x4f800000
2590 ; VI-NEXT: v_madak_f32 v2, 0, v2, 0x47c35000
2591 ; VI-NEXT: v_rcp_f32_e32 v2, v2
2592 ; VI-NEXT: s_mov_b32 s6, 0xfffe7960
2593 ; VI-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
2594 ; VI-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
2595 ; VI-NEXT: v_trunc_f32_e32 v3, v3
2596 ; VI-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
2597 ; VI-NEXT: v_cvt_u32_f32_e32 v6, v2
2598 ; VI-NEXT: v_cvt_u32_f32_e32 v7, v3
2599 ; VI-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v6, s6, 0
2600 ; VI-NEXT: v_mul_lo_u32 v4, v7, s6
2601 ; VI-NEXT: v_subrev_u32_e32 v3, vcc, v6, v3
2602 ; VI-NEXT: v_add_u32_e32 v8, vcc, v3, v4
2603 ; VI-NEXT: v_mul_hi_u32 v5, v6, v2
2604 ; VI-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v6, v8, 0
2605 ; VI-NEXT: v_add_u32_e32 v9, vcc, v5, v3
2606 ; VI-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v7, v2, 0
2607 ; VI-NEXT: v_addc_u32_e32 v10, vcc, 0, v4, vcc
2608 ; VI-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v7, v8, 0
2609 ; VI-NEXT: v_add_u32_e32 v2, vcc, v9, v2
2610 ; VI-NEXT: v_addc_u32_e32 v2, vcc, v10, v3, vcc
2611 ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
2612 ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v4
2613 ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
2614 ; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v2
2615 ; VI-NEXT: v_addc_u32_e32 v7, vcc, v7, v3, vcc
2616 ; VI-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v6, s6, 0
2617 ; VI-NEXT: v_mul_lo_u32 v4, v7, s6
2618 ; VI-NEXT: v_subrev_u32_e32 v3, vcc, v6, v3
2619 ; VI-NEXT: v_add_u32_e32 v5, vcc, v3, v4
2620 ; VI-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v6, v5, 0
2621 ; VI-NEXT: v_mul_hi_u32 v8, v6, v2
2622 ; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v3
2623 ; VI-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v7, v2, 0
2624 ; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v4, vcc
2625 ; VI-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v7, v5, 0
2626 ; VI-NEXT: v_add_u32_e32 v2, vcc, v8, v2
2627 ; VI-NEXT: v_addc_u32_e32 v2, vcc, v9, v3, vcc
2628 ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
2629 ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v4
2630 ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
2631 ; VI-NEXT: v_add_u32_e32 v4, vcc, v6, v2
2632 ; VI-NEXT: v_addc_u32_e32 v5, vcc, v7, v3, vcc
2633 ; VI-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, v5, 0
2634 ; VI-NEXT: v_mul_hi_u32 v6, v0, v4
2635 ; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v2
2636 ; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc
2637 ; VI-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, v4, 0
2638 ; VI-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, v5, 0
2639 ; VI-NEXT: v_add_u32_e32 v2, vcc, v6, v2
2640 ; VI-NEXT: v_addc_u32_e32 v2, vcc, v7, v3, vcc
2641 ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
2642 ; VI-NEXT: v_add_u32_e32 v4, vcc, v2, v4
2643 ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v3, vcc
2644 ; VI-NEXT: s_mov_b32 s4, 0x186a0
2645 ; VI-NEXT: v_mul_lo_u32 v6, v5, s4
2646 ; VI-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, s4, 0
2647 ; VI-NEXT: s_mov_b32 s4, 0x1869f
2648 ; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v6
2649 ; VI-NEXT: v_sub_u32_e32 v0, vcc, v0, v2
2650 ; VI-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
2651 ; VI-NEXT: v_subrev_u32_e32 v2, vcc, 0x186a0, v0
2652 ; VI-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v1, vcc
2653 ; VI-NEXT: v_cmp_lt_u32_e32 vcc, s4, v2
2654 ; VI-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
2655 ; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
2656 ; VI-NEXT: v_cndmask_b32_e32 v2, -1, v2, vcc
2657 ; VI-NEXT: v_add_u32_e32 v3, vcc, 2, v4
2658 ; VI-NEXT: v_addc_u32_e32 v6, vcc, 0, v5, vcc
2659 ; VI-NEXT: v_add_u32_e32 v7, vcc, 1, v4
2660 ; VI-NEXT: v_cmp_lt_u32_e64 s[4:5], s4, v0
2661 ; VI-NEXT: v_addc_u32_e32 v8, vcc, 0, v5, vcc
2662 ; VI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[4:5]
2663 ; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
2664 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
2665 ; VI-NEXT: v_cndmask_b32_e64 v0, -1, v0, s[4:5]
2666 ; VI-NEXT: v_cndmask_b32_e32 v2, v7, v3, vcc
2667 ; VI-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0
2668 ; VI-NEXT: v_cndmask_b32_e32 v1, v8, v6, vcc
2669 ; VI-NEXT: v_cndmask_b32_e64 v0, v4, v2, s[4:5]
2670 ; VI-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[4:5]
2671 ; VI-NEXT: s_setpc_b64 s[30:31]
2672 ;
2673 ; GCN-LABEL: v_test_udiv64_mulhi_fold:
2674 ; GCN: ; %bb.0:
2675 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2676 ; GCN-NEXT: v_mov_b32_e32 v2, 0x4f800000
2677 ; GCN-NEXT: v_madak_f32 v2, 0, v2, 0x47c35000
2678 ; GCN-NEXT: v_rcp_f32_e32 v2, v2
2679 ; GCN-NEXT: s_mov_b32 s6, 0xfffe7960
2680 ; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
2681 ; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
2682 ; GCN-NEXT: v_trunc_f32_e32 v3, v3
2683 ; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
2684 ; GCN-NEXT: v_cvt_u32_f32_e32 v6, v2
2685 ; GCN-NEXT: v_cvt_u32_f32_e32 v7, v3
2686 ; GCN-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v6, s6, 0
2687 ; GCN-NEXT: v_mul_lo_u32 v4, v7, s6
2688 ; GCN-NEXT: v_subrev_u32_e32 v3, vcc, v6, v3
2689 ; GCN-NEXT: v_add_u32_e32 v8, vcc, v3, v4
2690 ; GCN-NEXT: v_mul_hi_u32 v5, v6, v2
2691 ; GCN-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v6, v8, 0
2692 ; GCN-NEXT: v_add_u32_e32 v9, vcc, v5, v3
2693 ; GCN-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v7, v2, 0
2694 ; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v4, vcc
2695 ; GCN-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v7, v8, 0
2696 ; GCN-NEXT: v_add_u32_e32 v2, vcc, v9, v2
2697 ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v10, v3, vcc
2698 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
2699 ; GCN-NEXT: v_add_u32_e32 v2, vcc, v2, v4
2700 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
2701 ; GCN-NEXT: v_add_u32_e32 v6, vcc, v6, v2
2702 ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v3, vcc
2703 ; GCN-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v6, s6, 0
2704 ; GCN-NEXT: v_mul_lo_u32 v4, v7, s6
2705 ; GCN-NEXT: v_subrev_u32_e32 v3, vcc, v6, v3
2706 ; GCN-NEXT: v_add_u32_e32 v5, vcc, v3, v4
2707 ; GCN-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v6, v5, 0
2708 ; GCN-NEXT: v_mul_hi_u32 v8, v6, v2
2709 ; GCN-NEXT: v_add_u32_e32 v8, vcc, v8, v3
2710 ; GCN-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v7, v2, 0
2711 ; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v4, vcc
2712 ; GCN-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v7, v5, 0
2713 ; GCN-NEXT: v_add_u32_e32 v2, vcc, v8, v2
2714 ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v9, v3, vcc
2715 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
2716 ; GCN-NEXT: v_add_u32_e32 v2, vcc, v2, v4
2717 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
2718 ; GCN-NEXT: v_add_u32_e32 v4, vcc, v6, v2
2719 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v3, vcc
2720 ; GCN-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, v5, 0
2721 ; GCN-NEXT: v_mul_hi_u32 v6, v0, v4
2722 ; GCN-NEXT: v_add_u32_e32 v6, vcc, v6, v2
2723 ; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc
2724 ; GCN-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, v4, 0
2725 ; GCN-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, v5, 0
2726 ; GCN-NEXT: v_add_u32_e32 v2, vcc, v6, v2
2727 ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v3, vcc
2728 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
2729 ; GCN-NEXT: v_add_u32_e32 v4, vcc, v2, v4
2730 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v3, vcc
2731 ; GCN-NEXT: s_mov_b32 s4, 0x186a0
2732 ; GCN-NEXT: v_mul_lo_u32 v6, v5, s4
2733 ; GCN-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, s4, 0
2734 ; GCN-NEXT: s_mov_b32 s4, 0x1869f
2735 ; GCN-NEXT: v_add_u32_e32 v3, vcc, v3, v6
2736 ; GCN-NEXT: v_sub_u32_e32 v0, vcc, v0, v2
2737 ; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
2738 ; GCN-NEXT: v_subrev_u32_e32 v2, vcc, 0x186a0, v0
2739 ; GCN-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v1, vcc
2740 ; GCN-NEXT: v_cmp_lt_u32_e32 vcc, s4, v2
2741 ; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
2742 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
2743 ; GCN-NEXT: v_cndmask_b32_e32 v2, -1, v2, vcc
2744 ; GCN-NEXT: v_add_u32_e32 v3, vcc, 2, v4
2745 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v5, vcc
2746 ; GCN-NEXT: v_add_u32_e32 v7, vcc, 1, v4
2747 ; GCN-NEXT: v_cmp_lt_u32_e64 s[4:5], s4, v0
2748 ; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v5, vcc
2749 ; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[4:5]
2750 ; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
2751 ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
2752 ; GCN-NEXT: v_cndmask_b32_e64 v0, -1, v0, s[4:5]
2753 ; GCN-NEXT: v_cndmask_b32_e32 v2, v7, v3, vcc
2754 ; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0
2755 ; GCN-NEXT: v_cndmask_b32_e32 v1, v8, v6, vcc
2756 ; GCN-NEXT: v_cndmask_b32_e64 v0, v4, v2, s[4:5]
2757 ; GCN-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[4:5]
2758 ; GCN-NEXT: s_setpc_b64 s[30:31]
2759 ;
2760 ; GFX1030-LABEL: v_test_udiv64_mulhi_fold:
2761 ; GFX1030: ; %bb.0:
2762 ; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2763 ; GFX1030-NEXT: s_waitcnt_vscnt null, 0x0
2764 ; GFX1030-NEXT: s_mov_b32 s4, 0x346d900
2765 ; GFX1030-NEXT: s_add_u32 s4, 0x4237, s4
2766 ; GFX1030-NEXT: s_addc_u32 s5, 0, 0
2767 ; GFX1030-NEXT: v_add_co_u32 v2, s4, 0xa9000000, s4
2768 ; GFX1030-NEXT: s_cmpk_lg_u32 s4, 0x0
2769 ; GFX1030-NEXT: s_addc_u32 s5, s5, 0xa7c5
2770 ; GFX1030-NEXT: v_readfirstlane_b32 s4, v2
2771 ; GFX1030-NEXT: s_mul_i32 s6, s5, 0xfffe7960
2772 ; GFX1030-NEXT: s_mul_hi_u32 s7, s4, 0xfffe7960
2773 ; GFX1030-NEXT: s_mul_i32 s8, s4, 0xfffe7960
2774 ; GFX1030-NEXT: s_sub_i32 s7, s7, s4
2775 ; GFX1030-NEXT: s_mul_hi_u32 s9, s4, s8
2776 ; GFX1030-NEXT: s_add_i32 s7, s7, s6
2777 ; GFX1030-NEXT: s_mul_hi_u32 s10, s5, s8
2778 ; GFX1030-NEXT: s_mul_i32 s6, s5, s8
2779 ; GFX1030-NEXT: s_mul_hi_u32 s8, s4, s7
2780 ; GFX1030-NEXT: s_mul_i32 s4, s4, s7
2781 ; GFX1030-NEXT: s_mul_hi_u32 s11, s5, s7
2782 ; GFX1030-NEXT: s_add_u32 s4, s9, s4
2783 ; GFX1030-NEXT: s_addc_u32 s8, 0, s8
2784 ; GFX1030-NEXT: s_add_u32 s4, s4, s6
2785 ; GFX1030-NEXT: s_mul_i32 s7, s5, s7
2786 ; GFX1030-NEXT: s_addc_u32 s4, s8, s10
2787 ; GFX1030-NEXT: s_addc_u32 s6, s11, 0
2788 ; GFX1030-NEXT: s_add_u32 s4, s4, s7
2789 ; GFX1030-NEXT: s_addc_u32 s6, 0, s6
2790 ; GFX1030-NEXT: v_add_co_u32 v4, s4, v2, s4
2791 ; GFX1030-NEXT: s_cmpk_lg_u32 s4, 0x0
2792 ; GFX1030-NEXT: s_addc_u32 s4, s5, s6
2793 ; GFX1030-NEXT: v_mul_hi_u32 v8, v0, v4
2794 ; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, v0, s4, 0
2795 ; GFX1030-NEXT: v_mad_u64_u32 v[4:5], null, v1, v4, 0
2796 ; GFX1030-NEXT: v_mad_u64_u32 v[6:7], null, v1, s4, 0
2797 ; GFX1030-NEXT: v_add_co_u32 v2, vcc_lo, v8, v2
2798 ; GFX1030-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
2799 ; GFX1030-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4
2800 ; GFX1030-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v3, v5, vcc_lo
2801 ; GFX1030-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v7, vcc_lo
2802 ; GFX1030-NEXT: v_add_co_u32 v5, vcc_lo, v2, v6
2803 ; GFX1030-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, 0, v3, vcc_lo
2804 ; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0x186a0, v5, 0
2805 ; GFX1030-NEXT: v_mad_u64_u32 v[3:4], null, 0x186a0, v6, v[3:4]
2806 ; GFX1030-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v2
2807 ; GFX1030-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
2808 ; GFX1030-NEXT: v_subrev_co_u32 v2, vcc_lo, 0x186a0, v0
2809 ; GFX1030-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
2810 ; GFX1030-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x1869f, v2
2811 ; GFX1030-NEXT: v_cmp_eq_u32_e64 s4, 0, v1
2812 ; GFX1030-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc_lo
2813 ; GFX1030-NEXT: v_add_co_u32 v4, vcc_lo, v5, 2
2814 ; GFX1030-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v6, vcc_lo
2815 ; GFX1030-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x1869f, v0
2816 ; GFX1030-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
2817 ; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v3
2818 ; GFX1030-NEXT: v_cndmask_b32_e64 v0, -1, v0, s4
2819 ; GFX1030-NEXT: v_cndmask_b32_e32 v2, -1, v2, vcc_lo
2820 ; GFX1030-NEXT: v_add_co_u32 v3, vcc_lo, v5, 1
2821 ; GFX1030-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v6, vcc_lo
2822 ; GFX1030-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
2823 ; GFX1030-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc_lo
2824 ; GFX1030-NEXT: v_cndmask_b32_e32 v2, v8, v7, vcc_lo
2825 ; GFX1030-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
2826 ; GFX1030-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc_lo
2827 ; GFX1030-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc_lo
2828 ; GFX1030-NEXT: s_setpc_b64 s[30:31]
2829 ;
2830 ; EG-LABEL: v_test_udiv64_mulhi_fold:
2831 ; EG: ; %bb.0:
2832 ; EG-NEXT: CF_END
2833 ; EG-NEXT: PAD
2834 %d = udiv i64 %arg, 100000
2835 ret i64 %d
2836 }