1 ; RUN: llc -march=mipsel < %s | FileCheck %s
2 ; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic < %s -asm-show-inst | FileCheck %s -check-prefix=MMR6
4 @g1 = external global i32
7 ; CHECK: sltiu ${{[0-9]+}}, $4, 1
8 ; MMR6: sltiu ${{[0-9]+}}, $4, 1
9 ; MMR6: <MCInst #{{[0-9]+}} SLTiu_MM
11 define i32 @seteq0(i32 %a) {
13 %cmp = icmp eq i32 %a, 0
14 %conv = zext i1 %cmp to i32
18 ; CHECK-LABEL: setne0:
19 ; CHECK: sltu ${{[0-9]+}}, $zero, $4
20 ; MMR6: sltu ${{[0-9]+}}, $zero, $4
21 ; MMR6: <MCInst #{{[0-9]+}} SLTu_MM
23 define i32 @setne0(i32 %a) {
25 %cmp = icmp ne i32 %a, 0
26 %conv = zext i1 %cmp to i32
30 ; CHECK-LABEL: slti_beq0:
31 ; CHECK: slti $[[R0:[0-9]+]], $4, -32768
32 ; MMR6: slti $[[R0:[0-9]+]], $4, -32768
33 ; MMR6: <MCInst #{{[0-9]+}} SLTi_MM
36 define void @slti_beq0(i32 %a) {
38 %cmp = icmp slt i32 %a, -32768
39 br i1 %cmp, label %if.then, label %if.end
42 store i32 %a, i32* @g1, align 4
49 ; CHECK-LABEL: slti_beq1:
50 ; CHECK: slt ${{[0-9]+}}
51 ; MMR6: slt ${{[0-9]+}}
52 ; MMR6: <MCInst #{{[0-9]+}} SLT_MM
54 define void @slti_beq1(i32 %a) {
56 %cmp = icmp slt i32 %a, -32769
57 br i1 %cmp, label %if.then, label %if.end
60 store i32 %a, i32* @g1, align 4
67 ; CHECK-LABEL: slti_beq2:
68 ; CHECK: slti $[[R0:[0-9]+]], $4, 32767
69 ; MMR6: slti $[[R0:[0-9]+]], $4, 32767
70 ; MMR6: <MCInst #{{[0-9]+}} SLTi_MM
73 define void @slti_beq2(i32 %a) {
75 %cmp = icmp slt i32 %a, 32767
76 br i1 %cmp, label %if.then, label %if.end
79 store i32 %a, i32* @g1, align 4
86 ; CHECK-LABEL: slti_beq3:
87 ; CHECK: slt ${{[0-9]+}}
88 ; MMR6: slt ${{[0-9]+}}
89 ; MMR6: <MCInst #{{[0-9]+}} SLT_MM
91 define void @slti_beq3(i32 %a) {
93 %cmp = icmp slt i32 %a, 32768
94 br i1 %cmp, label %if.then, label %if.end
97 store i32 %a, i32* @g1, align 4
104 ; CHECK-LABEL: sltiu_beq0:
105 ; CHECK: sltiu $[[R0:[0-9]+]], $4, 32767
106 ; MMR6: sltiu $[[R0:[0-9]+]], $4, 32767
107 ; MMR6: <MCInst #{{[0-9]+}} SLTiu_MM
108 ; CHECK: beqz $[[R0]]
110 define void @sltiu_beq0(i32 %a) {
112 %cmp = icmp ult i32 %a, 32767
113 br i1 %cmp, label %if.then, label %if.end
116 store i32 %a, i32* @g1, align 4
123 ; CHECK-LABEL: sltiu_beq1:
124 ; CHECK: sltu ${{[0-9]+}}
125 ; MMR6: sltu ${{[0-9]+}}
126 ; MMR6: <MCInst #{{[0-9]+}} SLTu_MM
128 define void @sltiu_beq1(i32 %a) {
130 %cmp = icmp ult i32 %a, 32768
131 br i1 %cmp, label %if.then, label %if.end
134 store i32 %a, i32* @g1, align 4
141 ; CHECK-LABEL: sltiu_beq2:
142 ; CHECK: sltiu $[[R0:[0-9]+]], $4, -32768
143 ; MMR6: sltiu $[[R0:[0-9]+]], $4, -32768
144 ; MMR6: <MCInst #{{[0-9]+}} SLTiu_MM
145 ; CHECK: beqz $[[R0]]
147 define void @sltiu_beq2(i32 %a) {
149 %cmp = icmp ult i32 %a, -32768
150 br i1 %cmp, label %if.then, label %if.end
153 store i32 %a, i32* @g1, align 4
160 ; CHECK-LABEL: sltiu_beq3:
161 ; CHECK: sltu ${{[0-9]+}}
162 ; MMR6: sltu ${{[0-9]+}}
163 ; MMR6: <MCInst #{{[0-9]+}} SLTu_MM
165 define void @sltiu_beq3(i32 %a) {
167 %cmp = icmp ult i32 %a, -32769
168 br i1 %cmp, label %if.then, label %if.end
171 store i32 %a, i32* @g1, align 4